diff mbox series

[v2,2/7] i3c: Add core I3C infrastructure

Message ID 20171214151610.19153-3-boris.brezillon@free-electrons.com
State Not Applicable
Headers show
Series Add the I3C subsystem | expand

Commit Message

Boris Brezillon Dec. 14, 2017, 3:16 p.m. UTC 
Add core infrastructure to support I3C in Linux and document it.

This infrastructure is not complete yet and will be extended over
time.

There are a few design choices that are worth mentioning because they
impact the way I3C device drivers can interact with their devices:

- all functions used to send I3C/I2C frames must be called in
  non-atomic context. Mainly done this way to ease implementation, but
  this is still open to discussion. Please let me know if you think
  it's worth considering an asynchronous model here
- the bus element is a separate object and is not implicitly described
  by the master (as done in I2C). The reason is that I want to be able
  to handle multiple master connected to the same bus and visible to
  Linux.
  In this situation, we should only have one instance of the device and
  not one per master, and sharing the bus object would be part of the
  solution to gracefully handle this case.
  I'm not sure we will ever need to deal with multiple masters
  controlling the same bus and exposed under Linux, but separating the
  bus and master concept is pretty easy, hence the decision to do it
  like that.
  The other benefit of separating the bus and master concepts is that
  master devices appear under the bus directory in sysfs.
- I2C backward compatibility has been designed to be transparent to I2C
  drivers and the I2C subsystem. The I3C master just registers an I2C
  adapter which creates a new I2C bus. I'd say that, from a
  representation PoV it's not ideal because what should appear as a
  single I3C bus exposing I3C and I2C devices here appears as 2
  different busses connected to each other through the parenting (the
  I3C master is the parent of the I2C and I3C busses).
  On the other hand, I don't see a better solution if we want something
  that is not invasive.

Missing features in this preliminary version:
- no support for multi-master and the associated concepts (mastership
  handover, support for secondary masters, ...)
- I2C devices can only be described using DT because this is the only
  use case I have. However, the framework can easily be extended with
  ACPI and board info support
- I3C slave framework. This has been completely omitted, but shouldn't
  have a huge impact on the I3C framework because I3C slaves don't see
  the whole bus, it's only about handling master requests and generating
  IBIs. Some of the struct, constant and enum definitions could be
  shared, but most of the I3C slave framework logic will be different

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
---
Changes in v2:
- Fix a bunch of mistake I made with the device model (pointed by GKH)
- Move the documentation out of this commit (pointed by GKH)
- only source drivers/i3c/master/Kconfig when CONFIG_I3C is enabled
  (pointed by GKH)
- Add IBI infrastructure
- Add helpers to ease support for Hot Join (most of the logic is
  delegated to I3C controller drivers)
- move the doc out of this commit to improve readability
- Fix a few bugs in device probing/remove (detected after trying to
  load/unload modules in various orders)
- Add a module_i3c_i2c_driver() macro to ease integration of drivers
  for devices that support both I3C and I2C mode
---
 drivers/Kconfig                 |    2 +
 drivers/Makefile                |    2 +-
 drivers/i3c/Kconfig             |   24 +
 drivers/i3c/Makefile            |    4 +
 drivers/i3c/core.c              |  573 ++++++++++++++++
 drivers/i3c/device.c            |  344 ++++++++++
 drivers/i3c/internals.h         |   34 +
 drivers/i3c/master.c            | 1433 +++++++++++++++++++++++++++++++++++++++
 drivers/i3c/master/Kconfig      |    0
 drivers/i3c/master/Makefile     |    0
 include/linux/i3c/ccc.h         |  380 +++++++++++
 include/linux/i3c/device.h      |  321 +++++++++
 include/linux/i3c/master.h      |  564 +++++++++++++++
 include/linux/mod_devicetable.h |   17 +
 14 files changed, 3697 insertions(+), 1 deletion(-)
 create mode 100644 drivers/i3c/Kconfig
 create mode 100644 drivers/i3c/Makefile
 create mode 100644 drivers/i3c/core.c
 create mode 100644 drivers/i3c/device.c
 create mode 100644 drivers/i3c/internals.h
 create mode 100644 drivers/i3c/master.c
 create mode 100644 drivers/i3c/master/Kconfig
 create mode 100644 drivers/i3c/master/Makefile
 create mode 100644 include/linux/i3c/ccc.h
 create mode 100644 include/linux/i3c/device.h
 create mode 100644 include/linux/i3c/master.h

Comments

Randy Dunlap Dec. 17, 2017, 10:32 p.m. UTC | #1 
On 12/14/17 07:16, Boris Brezillon wrote:
> Add core infrastructure to support I3C in Linux and document it.
> 
> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
> ---
>  drivers/Kconfig                 |    2 +
>  drivers/Makefile                |    2 +-
>  drivers/i3c/Kconfig             |   24 +
>  drivers/i3c/Makefile            |    4 +
>  drivers/i3c/core.c              |  573 ++++++++++++++++
>  drivers/i3c/device.c            |  344 ++++++++++
>  drivers/i3c/internals.h         |   34 +
>  drivers/i3c/master.c            | 1433 +++++++++++++++++++++++++++++++++++++++
>  drivers/i3c/master/Kconfig      |    0
>  drivers/i3c/master/Makefile     |    0
>  include/linux/i3c/ccc.h         |  380 +++++++++++
>  include/linux/i3c/device.h      |  321 +++++++++
>  include/linux/i3c/master.h      |  564 +++++++++++++++
>  include/linux/mod_devicetable.h |   17 +
>  14 files changed, 3697 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/i3c/Kconfig
>  create mode 100644 drivers/i3c/Makefile
>  create mode 100644 drivers/i3c/core.c
>  create mode 100644 drivers/i3c/device.c
>  create mode 100644 drivers/i3c/internals.h
>  create mode 100644 drivers/i3c/master.c
>  create mode 100644 drivers/i3c/master/Kconfig
>  create mode 100644 drivers/i3c/master/Makefile
>  create mode 100644 include/linux/i3c/ccc.h
>  create mode 100644 include/linux/i3c/device.h
>  create mode 100644 include/linux/i3c/master.h
> 
> diff --git a/drivers/i3c/Kconfig b/drivers/i3c/Kconfig
> new file mode 100644
> index 000000000000..cf3752412ae9
> --- /dev/null
> +++ b/drivers/i3c/Kconfig
> @@ -0,0 +1,24 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +menuconfig I3C
> +	tristate "I3C support"
> +	select I2C
> +	help
> +	  I3C is a serial protocol standardized by the MIPI alliance.
> +
> +	  It's supposed to be backward compatible with I2C while providing
> +	  support for high speed transfers and native interrupt support
> +	  without the need for extra pins.
> +
> +	  The I3C protocol also standardizes the slave device types and is
> +	  mainly design to communicate with sensors.
> +
> +	  If you want I3C support, you should say Y here and also to the
> +	  specific driver for your bus adapter(s) below.
> +
> +	  This I3C support can also be built as a module.  If so, the module
> +	  will be called i3c.
> +
> +if I3C
> +source "drivers/i3c/master/Kconfig"
> +endif # I3C

> diff --git a/drivers/i3c/core.c b/drivers/i3c/core.c
> new file mode 100644
> index 000000000000..7eb8e84acd33
> --- /dev/null
> +++ b/drivers/i3c/core.c
> @@ -0,0 +1,573 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2017 Cadence Design Systems Inc.
> + *
> + * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
> + */
> +
> +#include <linux/idr.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/slab.h>

#include <linux/device.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/mutex.h>
#include <linux/rwsem.h>


> +#include "internals.h"
> +
> +static DEFINE_IDR(i3c_bus_idr);
> +static DEFINE_MUTEX(i3c_core_lock);
> +

> +/**
> + * i3c_bus_maintenance_lock - Release the bus lock after a maintenance

                          unlock

> + *			      operation
> + * @bus: I3C bus to release the lock on
> + *
> + * Should be called when the bus maintenance operation is done. See
> + * i3c_bus_maintenance_lock() for more details on what these maintenance
> + * operations are.
> + */
> +void i3c_bus_maintenance_unlock(struct i3c_bus *bus)
> +{
> +	up_write(&bus->lock);
> +}
> +EXPORT_SYMBOL_GPL(i3c_bus_maintenance_unlock);
> +

> +/**
> + * i3c_bus_normaluse_lock - Release the bus lock after a normal operation

                        unlock

> + * @bus: I3C bus to release the lock on
> + *
> + * Should be called when a normal operation is done. See
> + * i3c_bus_normaluse_lock() for more details on what these normal operations
> + * are.
> + */
> +void i3c_bus_normaluse_unlock(struct i3c_bus *bus)
> +{
> +	up_read(&bus->lock);
> +}
> +EXPORT_SYMBOL_GPL(i3c_bus_normaluse_unlock);



> +static int i3c_device_match(struct device *dev, struct device_driver *drv)

bool?

> +{
> +	struct i3c_device *i3cdev;
> +	struct i3c_driver *i3cdrv;
> +
> +	if (dev->type != &i3c_device_type)
> +		return 0;
> +
> +	i3cdev = dev_to_i3cdev(dev);
> +	i3cdrv = drv_to_i3cdrv(drv);
> +	if (i3c_device_match_id(i3cdev, i3cdrv->id_table))
> +		return 1;
> +
> +	return 0;
> +}


> diff --git a/drivers/i3c/device.c b/drivers/i3c/device.c
> new file mode 100644
> index 000000000000..dcf51150b7cb
> --- /dev/null
> +++ b/drivers/i3c/device.c
> @@ -0,0 +1,344 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2017 Cadence Design Systems Inc.
> + *
> + * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
> + */
> +
> +#include <linux/slab.h>

#include <linux/atomic.h>
#include <linux/bug.h>
#include <linux/completion.h>
#include <linux/device.h>
#include <linux/mutex.h>

> +#include "internals.h"



> diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c
> new file mode 100644
> index 000000000000..1c85abac08d5
> --- /dev/null
> +++ b/drivers/i3c/master.c
> @@ -0,0 +1,1433 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2017 Cadence Design Systems Inc.
> + *
> + * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
> + */

#include <linux/atomic.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/of.h>

> +#include <linux/slab.h>

#include <linux/spinlock.h>
#include <linux/workqueue.h>

#include <asm-generic/bug.h>

> +#include "internals.h"


and I probably missed a few.




> diff --git a/include/linux/i3c/ccc.h b/include/linux/i3c/ccc.h
> new file mode 100644
> index 000000000000..ff3e1a3e2c4c
> --- /dev/null
> +++ b/include/linux/i3c/ccc.h
> @@ -0,0 +1,380 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2017 Cadence Design Systems Inc.
> + *
> + * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
> + */

> +/**
> + * struct i3c_ccc_dev_desc - I3C/I3C device descriptor used for DEFSLVS

Is one of those I3C above supposed to be I2C?

> + *
> + * @dyn_addr: dynamic address assigned to the I3C slave or 0 if the entry is
> + *	      describing an I2C slave.
> + * @dcr: DCR value (not applicable to entries describing I2C devices)
> + * @lvr: LVR value (not applicable to entries describing I3C devices)
> + * @bcr: BCR value or 0 if this entry is describing an I2C slave
> + * @static_addr: static address or 0 if the device does not have a static
> + *		 address
> + *
> + * The DEFSLVS command should be passed an array of i3c_ccc_dev_desc
> + * descriptors (one entry per I3C/I2C dev controlled by the master).
> + */
> +struct i3c_ccc_dev_desc {
> +	u8 dyn_addr;
> +	union {
> +		u8 dcr;
> +		u8 lvr;
> +	};
> +	u8 bcr;
> +	u8 static_addr;
> +} __packed;


Needs bitops.h

> diff --git a/include/linux/i3c/device.h b/include/linux/i3c/device.h
> new file mode 100644
> index 000000000000..83958d3a02e2
> --- /dev/null
> +++ b/include/linux/i3c/device.h
> @@ -0,0 +1,321 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2017 Cadence Design Systems Inc.
> + *
> + * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
> + */
> +
> +#ifndef I3C_DEV_H
> +#define I3C_DEV_H
> +
> +#include <linux/device.h>
> +#include <linux/i2c.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/module.h>


Needs bitops.h, kconfig.h.


> diff --git a/include/linux/i3c/master.h b/include/linux/i3c/master.h
> new file mode 100644
> index 000000000000..7ec9a4821bac
> --- /dev/null
> +++ b/include/linux/i3c/master.h
> @@ -0,0 +1,564 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2017 Cadence Design Systems Inc.
> + *
> + * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
> + */
> +
> +#ifndef I3C_MASTER_H
> +#define I3C_MASTER_H
> +
> +#include <linux/i2c.h>
> +#include <linux/i3c/ccc.h>
> +#include <linux/i3c/device.h>
> +#include <linux/spinlock.h>
> +
> +#define I3C_HOT_JOIN_ADDR		0x2
> +#define I3C_BROADCAST_ADDR		0x7e
> +#define I3C_MAX_ADDR			GENMASK(6, 0)
> +

Needs bitops.h, workqueue.h, rwsem.h


Needs <asm-generic/bitsperlong.h>



> diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h
> index abb6dc2ebbf8..e59da92d8ac9 100644
> --- a/include/linux/mod_devicetable.h
> +++ b/include/linux/mod_devicetable.h
> @@ -442,6 +442,23 @@ struct pci_epf_device_id {
>  	kernel_ulong_t driver_data;
>  };
>  
> +/* i3c */
> +
> +#define I3C_MATCH_DCR			BIT(0)
> +#define I3C_MATCH_MANUF			BIT(1)
> +#define I3C_MATCH_PART			BIT(2)
> +#define I3C_MATCH_EXTRA_INFO		BIT(3)

Needs bitops.h.

> +struct i3c_device_id {
> +	__u8 match_flags;
> +	__u8 dcr;
> +	__u16 manuf_id;
> +	__u16 part_id;
> +	__u16 extra_info;
> +
> +	const void *data;
> +};
> +
>  /* spi */
>  
>  #define SPI_NAME_SIZE	32
>
Boris Brezillon Dec. 18, 2017, 8:37 a.m. UTC | #2 
On Sun, 17 Dec 2017 14:32:04 -0800
Randy Dunlap <rdunlap@infradead.org> wrote:

> On 12/14/17 07:16, Boris Brezillon wrote:
> > Add core infrastructure to support I3C in Linux and document it.
> > 
> > Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
> > ---
> >  drivers/Kconfig                 |    2 +
> >  drivers/Makefile                |    2 +-
> >  drivers/i3c/Kconfig             |   24 +
> >  drivers/i3c/Makefile            |    4 +
> >  drivers/i3c/core.c              |  573 ++++++++++++++++
> >  drivers/i3c/device.c            |  344 ++++++++++
> >  drivers/i3c/internals.h         |   34 +
> >  drivers/i3c/master.c            | 1433 +++++++++++++++++++++++++++++++++++++++
> >  drivers/i3c/master/Kconfig      |    0
> >  drivers/i3c/master/Makefile     |    0
> >  include/linux/i3c/ccc.h         |  380 +++++++++++
> >  include/linux/i3c/device.h      |  321 +++++++++
> >  include/linux/i3c/master.h      |  564 +++++++++++++++
> >  include/linux/mod_devicetable.h |   17 +
> >  14 files changed, 3697 insertions(+), 1 deletion(-)
> >  create mode 100644 drivers/i3c/Kconfig
> >  create mode 100644 drivers/i3c/Makefile
> >  create mode 100644 drivers/i3c/core.c
> >  create mode 100644 drivers/i3c/device.c
> >  create mode 100644 drivers/i3c/internals.h
> >  create mode 100644 drivers/i3c/master.c
> >  create mode 100644 drivers/i3c/master/Kconfig
> >  create mode 100644 drivers/i3c/master/Makefile
> >  create mode 100644 include/linux/i3c/ccc.h
> >  create mode 100644 include/linux/i3c/device.h
> >  create mode 100644 include/linux/i3c/master.h
> > 
> > diff --git a/drivers/i3c/Kconfig b/drivers/i3c/Kconfig
> > new file mode 100644
> > index 000000000000..cf3752412ae9
> > --- /dev/null
> > +++ b/drivers/i3c/Kconfig
> > @@ -0,0 +1,24 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +
> > +menuconfig I3C
> > +	tristate "I3C support"
> > +	select I2C
> > +	help
> > +	  I3C is a serial protocol standardized by the MIPI alliance.
> > +
> > +	  It's supposed to be backward compatible with I2C while providing
> > +	  support for high speed transfers and native interrupt support
> > +	  without the need for extra pins.
> > +
> > +	  The I3C protocol also standardizes the slave device types and is
> > +	  mainly design to communicate with sensors.
> > +
> > +	  If you want I3C support, you should say Y here and also to the
> > +	  specific driver for your bus adapter(s) below.
> > +
> > +	  This I3C support can also be built as a module.  If so, the module
> > +	  will be called i3c.
> > +
> > +if I3C
> > +source "drivers/i3c/master/Kconfig"
> > +endif # I3C  
> 
> > diff --git a/drivers/i3c/core.c b/drivers/i3c/core.c
> > new file mode 100644
> > index 000000000000..7eb8e84acd33
> > --- /dev/null
> > +++ b/drivers/i3c/core.c
> > @@ -0,0 +1,573 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2017 Cadence Design Systems Inc.
> > + *
> > + * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
> > + */
> > +
> > +#include <linux/idr.h>
> > +#include <linux/module.h>
> > +#include <linux/of_device.h>
> > +#include <linux/slab.h>  
> 
> #include <linux/device.h>
> #include <linux/init.h>
> #include <linux/list.h>
> #include <linux/mutex.h>
> #include <linux/rwsem.h>

Do you have a tool to detect those missing inclusions?

> 
> 
> > +#include "internals.h"
> > +
> > +static DEFINE_IDR(i3c_bus_idr);
> > +static DEFINE_MUTEX(i3c_core_lock);
> > +  
> 
> > +/**
> > + * i3c_bus_maintenance_lock - Release the bus lock after a maintenance  
> 
>                           unlock
> 

Will fix that.

> > + *			      operation
> > + * @bus: I3C bus to release the lock on
> > + *
> > + * Should be called when the bus maintenance operation is done. See
> > + * i3c_bus_maintenance_lock() for more details on what these maintenance
> > + * operations are.
> > + */
> > +void i3c_bus_maintenance_unlock(struct i3c_bus *bus)
> > +{
> > +	up_write(&bus->lock);
> > +}
> > +EXPORT_SYMBOL_GPL(i3c_bus_maintenance_unlock);
> > +  
> 
> > +/**
> > + * i3c_bus_normaluse_lock - Release the bus lock after a normal operation  
> 
>                         unlock

Ditto.

> 
> > + * @bus: I3C bus to release the lock on
> > + *
> > + * Should be called when a normal operation is done. See
> > + * i3c_bus_normaluse_lock() for more details on what these normal operations
> > + * are.
> > + */
> > +void i3c_bus_normaluse_unlock(struct i3c_bus *bus)
> > +{
> > +	up_read(&bus->lock);
> > +}
> > +EXPORT_SYMBOL_GPL(i3c_bus_normaluse_unlock);  
> 
> 
> 
> > +static int i3c_device_match(struct device *dev, struct device_driver *drv)  
> 
> bool?
> 
> > +{
> > +	struct i3c_device *i3cdev;
> > +	struct i3c_driver *i3cdrv;
> > +
> > +	if (dev->type != &i3c_device_type)
> > +		return 0;
> > +
> > +	i3cdev = dev_to_i3cdev(dev);
> > +	i3cdrv = drv_to_i3cdrv(drv);
> > +	if (i3c_device_match_id(i3cdev, i3cdrv->id_table))
> > +		return 1;
> > +
> > +	return 0;
> > +}  
> 
> 
> > diff --git a/drivers/i3c/device.c b/drivers/i3c/device.c
> > new file mode 100644
> > index 000000000000..dcf51150b7cb
> > --- /dev/null
> > +++ b/drivers/i3c/device.c
> > @@ -0,0 +1,344 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2017 Cadence Design Systems Inc.
> > + *
> > + * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
> > + */
> > +
> > +#include <linux/slab.h>  
> 
> #include <linux/atomic.h>
> #include <linux/bug.h>
> #include <linux/completion.h>
> #include <linux/device.h>
> #include <linux/mutex.h>
> 
> > +#include "internals.h"  
> 
> 
> 
> > diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c
> > new file mode 100644
> > index 000000000000..1c85abac08d5
> > --- /dev/null
> > +++ b/drivers/i3c/master.c
> > @@ -0,0 +1,1433 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2017 Cadence Design Systems Inc.
> > + *
> > + * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
> > + */  
> 
> #include <linux/atomic.h>
> #include <linux/device.h>
> #include <linux/err.h>
> #include <linux/export.h>
> #include <linux/kernel.h>
> #include <linux/list.h>
> #include <linux/of.h>
> 
> > +#include <linux/slab.h>  
> 
> #include <linux/spinlock.h>
> #include <linux/workqueue.h>
> 
> #include <asm-generic/bug.h>
> 
> > +#include "internals.h"  
> 
> 
> and I probably missed a few.
> 
> 
> 
> 
> > diff --git a/include/linux/i3c/ccc.h b/include/linux/i3c/ccc.h
> > new file mode 100644
> > index 000000000000..ff3e1a3e2c4c
> > --- /dev/null
> > +++ b/include/linux/i3c/ccc.h
> > @@ -0,0 +1,380 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (C) 2017 Cadence Design Systems Inc.
> > + *
> > + * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
> > + */  
> 
> > +/**
> > + * struct i3c_ccc_dev_desc - I3C/I3C device descriptor used for DEFSLVS  
> 
> Is one of those I3C above supposed to be I2C?

Indeed, should be I2C/I3C.

> 
> > + *
> > + * @dyn_addr: dynamic address assigned to the I3C slave or 0 if the entry is
> > + *	      describing an I2C slave.
> > + * @dcr: DCR value (not applicable to entries describing I2C devices)
> > + * @lvr: LVR value (not applicable to entries describing I3C devices)
> > + * @bcr: BCR value or 0 if this entry is describing an I2C slave
> > + * @static_addr: static address or 0 if the device does not have a static
> > + *		 address
> > + *
> > + * The DEFSLVS command should be passed an array of i3c_ccc_dev_desc
> > + * descriptors (one entry per I3C/I2C dev controlled by the master).
> > + */
> > +struct i3c_ccc_dev_desc {
> > +	u8 dyn_addr;
> > +	union {
> > +		u8 dcr;
> > +		u8 lvr;
> > +	};
> > +	u8 bcr;
> > +	u8 static_addr;
> > +} __packed;  
> 
> 
> Needs bitops.h
> 
> > diff --git a/include/linux/i3c/device.h b/include/linux/i3c/device.h
> > new file mode 100644
> > index 000000000000..83958d3a02e2
> > --- /dev/null
> > +++ b/include/linux/i3c/device.h
> > @@ -0,0 +1,321 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (C) 2017 Cadence Design Systems Inc.
> > + *
> > + * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
> > + */
> > +
> > +#ifndef I3C_DEV_H
> > +#define I3C_DEV_H
> > +
> > +#include <linux/device.h>
> > +#include <linux/i2c.h>
> > +#include <linux/mod_devicetable.h>
> > +#include <linux/module.h>  
> 
> 
> Needs bitops.h, kconfig.h.
> 
> 
> > diff --git a/include/linux/i3c/master.h b/include/linux/i3c/master.h
> > new file mode 100644
> > index 000000000000..7ec9a4821bac
> > --- /dev/null
> > +++ b/include/linux/i3c/master.h
> > @@ -0,0 +1,564 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (C) 2017 Cadence Design Systems Inc.
> > + *
> > + * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
> > + */
> > +
> > +#ifndef I3C_MASTER_H
> > +#define I3C_MASTER_H
> > +
> > +#include <linux/i2c.h>
> > +#include <linux/i3c/ccc.h>
> > +#include <linux/i3c/device.h>
> > +#include <linux/spinlock.h>
> > +
> > +#define I3C_HOT_JOIN_ADDR		0x2
> > +#define I3C_BROADCAST_ADDR		0x7e
> > +#define I3C_MAX_ADDR			GENMASK(6, 0)
> > +  
> 
> Needs bitops.h, workqueue.h, rwsem.h
> 
> 
> Needs <asm-generic/bitsperlong.h>

Okay, that's really weird to directly include a header from the
asm-generic directory, are you sure this is the right thing to do here?

> 
> 
> 
> > diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h
> > index abb6dc2ebbf8..e59da92d8ac9 100644
> > --- a/include/linux/mod_devicetable.h
> > +++ b/include/linux/mod_devicetable.h
> > @@ -442,6 +442,23 @@ struct pci_epf_device_id {
> >  	kernel_ulong_t driver_data;
> >  };
> >  
> > +/* i3c */
> > +
> > +#define I3C_MATCH_DCR			BIT(0)
> > +#define I3C_MATCH_MANUF			BIT(1)
> > +#define I3C_MATCH_PART			BIT(2)
> > +#define I3C_MATCH_EXTRA_INFO		BIT(3)
> 
> Needs bitops.h.

I think I'll just avoid using BIT() here, as done for other definitions
in this file.

> 
> > +struct i3c_device_id {
> > +	__u8 match_flags;
> > +	__u8 dcr;
> > +	__u16 manuf_id;
> > +	__u16 part_id;
> > +	__u16 extra_info;
> > +
> > +	const void *data;
> > +};
> > +
> >  /* spi */
> >  
> >  #define SPI_NAME_SIZE	32
> >   
> 
>
Randy Dunlap Dec. 18, 2017, 6:22 p.m. UTC | #3 
On 12/18/2017 12:37 AM, Boris Brezillon wrote:
> On Sun, 17 Dec 2017 14:32:04 -0800
> Randy Dunlap <rdunlap@infradead.org> wrote:
> 
>> On 12/14/17 07:16, Boris Brezillon wrote:
>>> Add core infrastructure to support I3C in Linux and document it.
>>>
>>> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
>>> ---
>>>  drivers/Kconfig                 |    2 +
>>>  drivers/Makefile                |    2 +-
>>>  drivers/i3c/Kconfig             |   24 +
>>>  drivers/i3c/Makefile            |    4 +
>>>  drivers/i3c/core.c              |  573 ++++++++++++++++
>>>  drivers/i3c/device.c            |  344 ++++++++++
>>>  drivers/i3c/internals.h         |   34 +
>>>  drivers/i3c/master.c            | 1433 +++++++++++++++++++++++++++++++++++++++
>>>  drivers/i3c/master/Kconfig      |    0
>>>  drivers/i3c/master/Makefile     |    0
>>>  include/linux/i3c/ccc.h         |  380 +++++++++++
>>>  include/linux/i3c/device.h      |  321 +++++++++
>>>  include/linux/i3c/master.h      |  564 +++++++++++++++
>>>  include/linux/mod_devicetable.h |   17 +
>>>  14 files changed, 3697 insertions(+), 1 deletion(-)
>>>  create mode 100644 drivers/i3c/Kconfig
>>>  create mode 100644 drivers/i3c/Makefile
>>>  create mode 100644 drivers/i3c/core.c
>>>  create mode 100644 drivers/i3c/device.c
>>>  create mode 100644 drivers/i3c/internals.h
>>>  create mode 100644 drivers/i3c/master.c
>>>  create mode 100644 drivers/i3c/master/Kconfig
>>>  create mode 100644 drivers/i3c/master/Makefile
>>>  create mode 100644 include/linux/i3c/ccc.h
>>>  create mode 100644 include/linux/i3c/device.h
>>>  create mode 100644 include/linux/i3c/master.h


>>> diff --git a/drivers/i3c/core.c b/drivers/i3c/core.c
>>> new file mode 100644
>>> index 000000000000..7eb8e84acd33
>>> --- /dev/null
>>> +++ b/drivers/i3c/core.c
>>> @@ -0,0 +1,573 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +/*
>>> + * Copyright (C) 2017 Cadence Design Systems Inc.
>>> + *
>>> + * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
>>> + */
>>> +
>>> +#include <linux/idr.h>
>>> +#include <linux/module.h>
>>> +#include <linux/of_device.h>
>>> +#include <linux/slab.h>  
>>
>> #include <linux/device.h>
>> #include <linux/init.h>
>> #include <linux/list.h>
>> #include <linux/mutex.h>
>> #include <linux/rwsem.h>
> 
> Do you have a tool to detect those missing inclusions?

Nope, I've often wanted one, but for now it's just slow reading.



>>> diff --git a/include/linux/i3c/master.h b/include/linux/i3c/master.h
>>> new file mode 100644
>>> index 000000000000..7ec9a4821bac
>>> --- /dev/null
>>> +++ b/include/linux/i3c/master.h
>>> @@ -0,0 +1,564 @@
>>> +/* SPDX-License-Identifier: GPL-2.0 */
>>> +/*
>>> + * Copyright (C) 2017 Cadence Design Systems Inc.
>>> + *
>>> + * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
>>> + */
>>> +
>>> +#ifndef I3C_MASTER_H
>>> +#define I3C_MASTER_H
>>> +
>>> +#include <linux/i2c.h>
>>> +#include <linux/i3c/ccc.h>
>>> +#include <linux/i3c/device.h>
>>> +#include <linux/spinlock.h>
>>> +
>>> +#define I3C_HOT_JOIN_ADDR		0x2
>>> +#define I3C_BROADCAST_ADDR		0x7e
>>> +#define I3C_MAX_ADDR			GENMASK(6, 0)
>>> +  
>>
>> Needs bitops.h, workqueue.h, rwsem.h
>>
>>
>> Needs <asm-generic/bitsperlong.h>
> 
> Okay, that's really weird to directly include a header from the
> asm-generic directory, are you sure this is the right thing to do here?

Looks like it should be <asm/bitsperlong.h>, which will grab the correct one.
Greg KH Dec. 19, 2017, 8:52 a.m. UTC | #4 
On Thu, Dec 14, 2017 at 04:16:05PM +0100, Boris Brezillon wrote:
> +/**
> + * i3c_device_match_id() - Find the I3C device ID entry matching an I3C dev
> + * @i3cdev: the I3C device we're searching a match for
> + * @id_table: the I3C device ID table
> + *
> + * Return: a pointer to the first entry matching @i3cdev, or NULL if there's
> + *	   no match.
> + */
> +const struct i3c_device_id *
> +i3c_device_match_id(struct i3c_device *i3cdev,
> +		    const struct i3c_device_id *id_table)
> +{
> +	const struct i3c_device_id *id;
> +
> +	/*
> +	 * The lower 32bits of the provisional ID is just filled with a random
> +	 * value, try to match using DCR info.
> +	 */
> +	if (!I3C_PID_RND_LOWER_32BITS(i3cdev->info.pid)) {
> +		u16 manuf = I3C_PID_MANUF_ID(i3cdev->info.pid);
> +		u16 part = I3C_PID_PART_ID(i3cdev->info.pid);
> +		u16 ext_info = I3C_PID_EXTRA_INFO(i3cdev->info.pid);
> +
> +		/* First try to match by manufacturer/part ID. */
> +		for (id = id_table; id->match_flags != 0; id++) {
> +			if ((id->match_flags & I3C_MATCH_MANUF_AND_PART) !=
> +			    I3C_MATCH_MANUF_AND_PART)
> +				continue;
> +
> +			if (manuf != id->manuf_id || part != id->part_id)
> +				continue;
> +
> +			if ((id->match_flags & I3C_MATCH_EXTRA_INFO) &&
> +			    ext_info != id->extra_info)
> +				continue;
> +
> +			return id;
> +		}
> +	}
> +
> +	/* Fallback to DCR match. */
> +	for (id = id_table; id->match_flags != 0; id++) {
> +		if ((id->match_flags & I3C_MATCH_DCR) &&
> +		    id->dcr == i3cdev->info.dcr)
> +			return id;
> +	}
> +
> +	return NULL;
> +}
> +EXPORT_SYMBOL_GPL(i3c_device_match_id);

I just picked one random export here, but it feels like you are
exporting a bunch of symbols you don't need to.  Why would something
outside of the i3c "core" need to call this function?  Have you looked
to see if you really have callers for everything you are exporting?

Other than that, the driver core interaction looks good now, nice job.

greg k-h
Boris Brezillon Dec. 19, 2017, 9:09 a.m. UTC | #5 
On Tue, 19 Dec 2017 09:52:50 +0100
Greg Kroah-Hartman <gregkh@linuxfoundation.org> wrote:

> On Thu, Dec 14, 2017 at 04:16:05PM +0100, Boris Brezillon wrote:
> > +/**
> > + * i3c_device_match_id() - Find the I3C device ID entry matching an I3C dev
> > + * @i3cdev: the I3C device we're searching a match for
> > + * @id_table: the I3C device ID table
> > + *
> > + * Return: a pointer to the first entry matching @i3cdev, or NULL if there's
> > + *	   no match.
> > + */
> > +const struct i3c_device_id *
> > +i3c_device_match_id(struct i3c_device *i3cdev,
> > +		    const struct i3c_device_id *id_table)
> > +{
> > +	const struct i3c_device_id *id;
> > +
> > +	/*
> > +	 * The lower 32bits of the provisional ID is just filled with a random
> > +	 * value, try to match using DCR info.
> > +	 */
> > +	if (!I3C_PID_RND_LOWER_32BITS(i3cdev->info.pid)) {
> > +		u16 manuf = I3C_PID_MANUF_ID(i3cdev->info.pid);
> > +		u16 part = I3C_PID_PART_ID(i3cdev->info.pid);
> > +		u16 ext_info = I3C_PID_EXTRA_INFO(i3cdev->info.pid);
> > +
> > +		/* First try to match by manufacturer/part ID. */
> > +		for (id = id_table; id->match_flags != 0; id++) {
> > +			if ((id->match_flags & I3C_MATCH_MANUF_AND_PART) !=
> > +			    I3C_MATCH_MANUF_AND_PART)
> > +				continue;
> > +
> > +			if (manuf != id->manuf_id || part != id->part_id)
> > +				continue;
> > +
> > +			if ((id->match_flags & I3C_MATCH_EXTRA_INFO) &&
> > +			    ext_info != id->extra_info)
> > +				continue;
> > +
> > +			return id;
> > +		}
> > +	}
> > +
> > +	/* Fallback to DCR match. */
> > +	for (id = id_table; id->match_flags != 0; id++) {
> > +		if ((id->match_flags & I3C_MATCH_DCR) &&
> > +		    id->dcr == i3cdev->info.dcr)
> > +			return id;
> > +	}
> > +
> > +	return NULL;
> > +}
> > +EXPORT_SYMBOL_GPL(i3c_device_match_id);  
> 
> I just picked one random export here, but it feels like you are
> exporting a bunch of symbols you don't need to.  Why would something
> outside of the i3c "core" need to call this function?

Because I'm not passing the i3c_device_id to the ->probe() method, and
if the driver is supporting different variants of the device, it may
want to know which one is being probed.

I considered retrieving this information in the core just before probing
the driver and passing it to the ->probe() function, but it means
having an extra i3c_device_match_id() call for everyone even those who
don't care about the device_id information, so I thought exporting this
function was a good alternative (device drivers can use it when they
actually need to retrieve the device_id).

Anyway, that's something I can change if you think passing the
i3c_device_id to the ->probe() method is preferable.

> Have you looked
> to see if you really have callers for everything you are exporting?

Yes, I tried to only export functions that I think will be needed by
I3C device drivers and I3C master drivers. Note that I didn't post the
dummy device driver I developed to test the framework (partly because
this is 

> 
> Other than that, the driver core interaction looks good now, nice job.

Thanks.

Boris
Boris Brezillon Dec. 19, 2017, 9:13 a.m. UTC | #6 
On Tue, 19 Dec 2017 10:09:00 +0100
Boris Brezillon <boris.brezillon@free-electrons.com> wrote:

> On Tue, 19 Dec 2017 09:52:50 +0100
> Greg Kroah-Hartman <gregkh@linuxfoundation.org> wrote:
> 
> > On Thu, Dec 14, 2017 at 04:16:05PM +0100, Boris Brezillon wrote:  
> > > +/**
> > > + * i3c_device_match_id() - Find the I3C device ID entry matching an I3C dev
> > > + * @i3cdev: the I3C device we're searching a match for
> > > + * @id_table: the I3C device ID table
> > > + *
> > > + * Return: a pointer to the first entry matching @i3cdev, or NULL if there's
> > > + *	   no match.
> > > + */
> > > +const struct i3c_device_id *
> > > +i3c_device_match_id(struct i3c_device *i3cdev,
> > > +		    const struct i3c_device_id *id_table)
> > > +{
> > > +	const struct i3c_device_id *id;
> > > +
> > > +	/*
> > > +	 * The lower 32bits of the provisional ID is just filled with a random
> > > +	 * value, try to match using DCR info.
> > > +	 */
> > > +	if (!I3C_PID_RND_LOWER_32BITS(i3cdev->info.pid)) {
> > > +		u16 manuf = I3C_PID_MANUF_ID(i3cdev->info.pid);
> > > +		u16 part = I3C_PID_PART_ID(i3cdev->info.pid);
> > > +		u16 ext_info = I3C_PID_EXTRA_INFO(i3cdev->info.pid);
> > > +
> > > +		/* First try to match by manufacturer/part ID. */
> > > +		for (id = id_table; id->match_flags != 0; id++) {
> > > +			if ((id->match_flags & I3C_MATCH_MANUF_AND_PART) !=
> > > +			    I3C_MATCH_MANUF_AND_PART)
> > > +				continue;
> > > +
> > > +			if (manuf != id->manuf_id || part != id->part_id)
> > > +				continue;
> > > +
> > > +			if ((id->match_flags & I3C_MATCH_EXTRA_INFO) &&
> > > +			    ext_info != id->extra_info)
> > > +				continue;
> > > +
> > > +			return id;
> > > +		}
> > > +	}
> > > +
> > > +	/* Fallback to DCR match. */
> > > +	for (id = id_table; id->match_flags != 0; id++) {
> > > +		if ((id->match_flags & I3C_MATCH_DCR) &&
> > > +		    id->dcr == i3cdev->info.dcr)
> > > +			return id;
> > > +	}
> > > +
> > > +	return NULL;
> > > +}
> > > +EXPORT_SYMBOL_GPL(i3c_device_match_id);    
> > 
> > I just picked one random export here, but it feels like you are
> > exporting a bunch of symbols you don't need to.  Why would something
> > outside of the i3c "core" need to call this function?  
> 
> Because I'm not passing the i3c_device_id to the ->probe() method, and
> if the driver is supporting different variants of the device, it may
> want to know which one is being probed.
> 
> I considered retrieving this information in the core just before probing
> the driver and passing it to the ->probe() function, but it means
> having an extra i3c_device_match_id() call for everyone even those who
> don't care about the device_id information, so I thought exporting this
> function was a good alternative (device drivers can use it when they
> actually need to retrieve the device_id).
> 
> Anyway, that's something I can change if you think passing the
> i3c_device_id to the ->probe() method is preferable.
> 
> > Have you looked
> > to see if you really have callers for everything you are exporting?  
> 
> Yes, I tried to only export functions that I think will be needed by
> I3C device drivers and I3C master drivers. Note that I didn't post the
> dummy device driver I developed to test the framework (partly because
> this is 

Sorry, I hit the send button before finishing my sentence :-).

"
Note that I didn't post the dummy device driver [1] I developed to test
the framework (partly because the quality of the code does not meet
mainline standards and I was ashamed of posting it publicly :-)), but
this driver is using some of the exported functions.
"

[1]https://github.com/bbrezillon/linux-0day/commit/10054caf3493524b6ae352a1bdcb71e82c885a6e
Greg KH Dec. 19, 2017, 9:21 a.m. UTC | #7 
On Tue, Dec 19, 2017 at 10:13:36AM +0100, Boris Brezillon wrote:
> On Tue, 19 Dec 2017 10:09:00 +0100
> Boris Brezillon <boris.brezillon@free-electrons.com> wrote:
> 
> > On Tue, 19 Dec 2017 09:52:50 +0100
> > Greg Kroah-Hartman <gregkh@linuxfoundation.org> wrote:
> > 
> > > On Thu, Dec 14, 2017 at 04:16:05PM +0100, Boris Brezillon wrote:  
> > > > +/**
> > > > + * i3c_device_match_id() - Find the I3C device ID entry matching an I3C dev
> > > > + * @i3cdev: the I3C device we're searching a match for
> > > > + * @id_table: the I3C device ID table
> > > > + *
> > > > + * Return: a pointer to the first entry matching @i3cdev, or NULL if there's
> > > > + *	   no match.
> > > > + */
> > > > +const struct i3c_device_id *
> > > > +i3c_device_match_id(struct i3c_device *i3cdev,
> > > > +		    const struct i3c_device_id *id_table)
> > > > +{
> > > > +	const struct i3c_device_id *id;
> > > > +
> > > > +	/*
> > > > +	 * The lower 32bits of the provisional ID is just filled with a random
> > > > +	 * value, try to match using DCR info.
> > > > +	 */
> > > > +	if (!I3C_PID_RND_LOWER_32BITS(i3cdev->info.pid)) {
> > > > +		u16 manuf = I3C_PID_MANUF_ID(i3cdev->info.pid);
> > > > +		u16 part = I3C_PID_PART_ID(i3cdev->info.pid);
> > > > +		u16 ext_info = I3C_PID_EXTRA_INFO(i3cdev->info.pid);
> > > > +
> > > > +		/* First try to match by manufacturer/part ID. */
> > > > +		for (id = id_table; id->match_flags != 0; id++) {
> > > > +			if ((id->match_flags & I3C_MATCH_MANUF_AND_PART) !=
> > > > +			    I3C_MATCH_MANUF_AND_PART)
> > > > +				continue;
> > > > +
> > > > +			if (manuf != id->manuf_id || part != id->part_id)
> > > > +				continue;
> > > > +
> > > > +			if ((id->match_flags & I3C_MATCH_EXTRA_INFO) &&
> > > > +			    ext_info != id->extra_info)
> > > > +				continue;
> > > > +
> > > > +			return id;
> > > > +		}
> > > > +	}
> > > > +
> > > > +	/* Fallback to DCR match. */
> > > > +	for (id = id_table; id->match_flags != 0; id++) {
> > > > +		if ((id->match_flags & I3C_MATCH_DCR) &&
> > > > +		    id->dcr == i3cdev->info.dcr)
> > > > +			return id;
> > > > +	}
> > > > +
> > > > +	return NULL;
> > > > +}
> > > > +EXPORT_SYMBOL_GPL(i3c_device_match_id);    
> > > 
> > > I just picked one random export here, but it feels like you are
> > > exporting a bunch of symbols you don't need to.  Why would something
> > > outside of the i3c "core" need to call this function?  
> > 
> > Because I'm not passing the i3c_device_id to the ->probe() method, and
> > if the driver is supporting different variants of the device, it may
> > want to know which one is being probed.
> > 
> > I considered retrieving this information in the core just before probing
> > the driver and passing it to the ->probe() function, but it means
> > having an extra i3c_device_match_id() call for everyone even those who
> > don't care about the device_id information, so I thought exporting this
> > function was a good alternative (device drivers can use it when they
> > actually need to retrieve the device_id).
> > 
> > Anyway, that's something I can change if you think passing the
> > i3c_device_id to the ->probe() method is preferable.
> > 
> > > Have you looked
> > > to see if you really have callers for everything you are exporting?  
> > 
> > Yes, I tried to only export functions that I think will be needed by
> > I3C device drivers and I3C master drivers. Note that I didn't post the
> > dummy device driver I developed to test the framework (partly because
> > this is 
> 
> Sorry, I hit the send button before finishing my sentence :-).
> 
> "
> Note that I didn't post the dummy device driver [1] I developed to test
> the framework (partly because the quality of the code does not meet
> mainline standards and I was ashamed of posting it publicly :-)), but
> this driver is using some of the exported functions.
> "

We don't export functions that has no in-kernel users :)

thanks,

greg k-h
Boris Brezillon Dec. 19, 2017, 9:28 a.m. UTC | #8 
On Tue, 19 Dec 2017 10:21:19 +0100
Greg Kroah-Hartman <gregkh@linuxfoundation.org> wrote:

> On Tue, Dec 19, 2017 at 10:13:36AM +0100, Boris Brezillon wrote:
> > On Tue, 19 Dec 2017 10:09:00 +0100
> > Boris Brezillon <boris.brezillon@free-electrons.com> wrote:
> >   
> > > On Tue, 19 Dec 2017 09:52:50 +0100
> > > Greg Kroah-Hartman <gregkh@linuxfoundation.org> wrote:
> > >   
> > > > On Thu, Dec 14, 2017 at 04:16:05PM +0100, Boris Brezillon wrote:    
> > > > > +/**
> > > > > + * i3c_device_match_id() - Find the I3C device ID entry matching an I3C dev
> > > > > + * @i3cdev: the I3C device we're searching a match for
> > > > > + * @id_table: the I3C device ID table
> > > > > + *
> > > > > + * Return: a pointer to the first entry matching @i3cdev, or NULL if there's
> > > > > + *	   no match.
> > > > > + */
> > > > > +const struct i3c_device_id *
> > > > > +i3c_device_match_id(struct i3c_device *i3cdev,
> > > > > +		    const struct i3c_device_id *id_table)
> > > > > +{
> > > > > +	const struct i3c_device_id *id;
> > > > > +
> > > > > +	/*
> > > > > +	 * The lower 32bits of the provisional ID is just filled with a random
> > > > > +	 * value, try to match using DCR info.
> > > > > +	 */
> > > > > +	if (!I3C_PID_RND_LOWER_32BITS(i3cdev->info.pid)) {
> > > > > +		u16 manuf = I3C_PID_MANUF_ID(i3cdev->info.pid);
> > > > > +		u16 part = I3C_PID_PART_ID(i3cdev->info.pid);
> > > > > +		u16 ext_info = I3C_PID_EXTRA_INFO(i3cdev->info.pid);
> > > > > +
> > > > > +		/* First try to match by manufacturer/part ID. */
> > > > > +		for (id = id_table; id->match_flags != 0; id++) {
> > > > > +			if ((id->match_flags & I3C_MATCH_MANUF_AND_PART) !=
> > > > > +			    I3C_MATCH_MANUF_AND_PART)
> > > > > +				continue;
> > > > > +
> > > > > +			if (manuf != id->manuf_id || part != id->part_id)
> > > > > +				continue;
> > > > > +
> > > > > +			if ((id->match_flags & I3C_MATCH_EXTRA_INFO) &&
> > > > > +			    ext_info != id->extra_info)
> > > > > +				continue;
> > > > > +
> > > > > +			return id;
> > > > > +		}
> > > > > +	}
> > > > > +
> > > > > +	/* Fallback to DCR match. */
> > > > > +	for (id = id_table; id->match_flags != 0; id++) {
> > > > > +		if ((id->match_flags & I3C_MATCH_DCR) &&
> > > > > +		    id->dcr == i3cdev->info.dcr)
> > > > > +			return id;
> > > > > +	}
> > > > > +
> > > > > +	return NULL;
> > > > > +}
> > > > > +EXPORT_SYMBOL_GPL(i3c_device_match_id);      
> > > > 
> > > > I just picked one random export here, but it feels like you are
> > > > exporting a bunch of symbols you don't need to.  Why would something
> > > > outside of the i3c "core" need to call this function?    
> > > 
> > > Because I'm not passing the i3c_device_id to the ->probe() method, and
> > > if the driver is supporting different variants of the device, it may
> > > want to know which one is being probed.
> > > 
> > > I considered retrieving this information in the core just before probing
> > > the driver and passing it to the ->probe() function, but it means
> > > having an extra i3c_device_match_id() call for everyone even those who
> > > don't care about the device_id information, so I thought exporting this
> > > function was a good alternative (device drivers can use it when they
> > > actually need to retrieve the device_id).
> > > 
> > > Anyway, that's something I can change if you think passing the
> > > i3c_device_id to the ->probe() method is preferable.
> > >   
> > > > Have you looked
> > > > to see if you really have callers for everything you are exporting?    
> > > 
> > > Yes, I tried to only export functions that I think will be needed by
> > > I3C device drivers and I3C master drivers. Note that I didn't post the
> > > dummy device driver I developed to test the framework (partly because
> > > this is   
> > 
> > Sorry, I hit the send button before finishing my sentence :-).
> > 
> > "
> > Note that I didn't post the dummy device driver [1] I developed to test
> > the framework (partly because the quality of the code does not meet
> > mainline standards and I was ashamed of posting it publicly :-)), but
> > this driver is using some of the exported functions.
> > "  
> 
> We don't export functions that has no in-kernel users :)

But then, I can't export device driver related functions, because
there's no official device driver yet :-). So what should I do?
Greg KH Dec. 19, 2017, 9:36 a.m. UTC | #9 
On Tue, Dec 19, 2017 at 10:28:58AM +0100, Boris Brezillon wrote:
> On Tue, 19 Dec 2017 10:21:19 +0100
> Greg Kroah-Hartman <gregkh@linuxfoundation.org> wrote:
> 
> > On Tue, Dec 19, 2017 at 10:13:36AM +0100, Boris Brezillon wrote:
> > > On Tue, 19 Dec 2017 10:09:00 +0100
> > > Boris Brezillon <boris.brezillon@free-electrons.com> wrote:
> > >   
> > > > On Tue, 19 Dec 2017 09:52:50 +0100
> > > > Greg Kroah-Hartman <gregkh@linuxfoundation.org> wrote:
> > > >   
> > > > > On Thu, Dec 14, 2017 at 04:16:05PM +0100, Boris Brezillon wrote:    
> > > > > > +/**
> > > > > > + * i3c_device_match_id() - Find the I3C device ID entry matching an I3C dev
> > > > > > + * @i3cdev: the I3C device we're searching a match for
> > > > > > + * @id_table: the I3C device ID table
> > > > > > + *
> > > > > > + * Return: a pointer to the first entry matching @i3cdev, or NULL if there's
> > > > > > + *	   no match.
> > > > > > + */
> > > > > > +const struct i3c_device_id *
> > > > > > +i3c_device_match_id(struct i3c_device *i3cdev,
> > > > > > +		    const struct i3c_device_id *id_table)
> > > > > > +{
> > > > > > +	const struct i3c_device_id *id;
> > > > > > +
> > > > > > +	/*
> > > > > > +	 * The lower 32bits of the provisional ID is just filled with a random
> > > > > > +	 * value, try to match using DCR info.
> > > > > > +	 */
> > > > > > +	if (!I3C_PID_RND_LOWER_32BITS(i3cdev->info.pid)) {
> > > > > > +		u16 manuf = I3C_PID_MANUF_ID(i3cdev->info.pid);
> > > > > > +		u16 part = I3C_PID_PART_ID(i3cdev->info.pid);
> > > > > > +		u16 ext_info = I3C_PID_EXTRA_INFO(i3cdev->info.pid);
> > > > > > +
> > > > > > +		/* First try to match by manufacturer/part ID. */
> > > > > > +		for (id = id_table; id->match_flags != 0; id++) {
> > > > > > +			if ((id->match_flags & I3C_MATCH_MANUF_AND_PART) !=
> > > > > > +			    I3C_MATCH_MANUF_AND_PART)
> > > > > > +				continue;
> > > > > > +
> > > > > > +			if (manuf != id->manuf_id || part != id->part_id)
> > > > > > +				continue;
> > > > > > +
> > > > > > +			if ((id->match_flags & I3C_MATCH_EXTRA_INFO) &&
> > > > > > +			    ext_info != id->extra_info)
> > > > > > +				continue;
> > > > > > +
> > > > > > +			return id;
> > > > > > +		}
> > > > > > +	}
> > > > > > +
> > > > > > +	/* Fallback to DCR match. */
> > > > > > +	for (id = id_table; id->match_flags != 0; id++) {
> > > > > > +		if ((id->match_flags & I3C_MATCH_DCR) &&
> > > > > > +		    id->dcr == i3cdev->info.dcr)
> > > > > > +			return id;
> > > > > > +	}
> > > > > > +
> > > > > > +	return NULL;
> > > > > > +}
> > > > > > +EXPORT_SYMBOL_GPL(i3c_device_match_id);      
> > > > > 
> > > > > I just picked one random export here, but it feels like you are
> > > > > exporting a bunch of symbols you don't need to.  Why would something
> > > > > outside of the i3c "core" need to call this function?    
> > > > 
> > > > Because I'm not passing the i3c_device_id to the ->probe() method, and
> > > > if the driver is supporting different variants of the device, it may
> > > > want to know which one is being probed.
> > > > 
> > > > I considered retrieving this information in the core just before probing
> > > > the driver and passing it to the ->probe() function, but it means
> > > > having an extra i3c_device_match_id() call for everyone even those who
> > > > don't care about the device_id information, so I thought exporting this
> > > > function was a good alternative (device drivers can use it when they
> > > > actually need to retrieve the device_id).
> > > > 
> > > > Anyway, that's something I can change if you think passing the
> > > > i3c_device_id to the ->probe() method is preferable.
> > > >   
> > > > > Have you looked
> > > > > to see if you really have callers for everything you are exporting?    
> > > > 
> > > > Yes, I tried to only export functions that I think will be needed by
> > > > I3C device drivers and I3C master drivers. Note that I didn't post the
> > > > dummy device driver I developed to test the framework (partly because
> > > > this is   
> > > 
> > > Sorry, I hit the send button before finishing my sentence :-).
> > > 
> > > "
> > > Note that I didn't post the dummy device driver [1] I developed to test
> > > the framework (partly because the quality of the code does not meet
> > > mainline standards and I was ashamed of posting it publicly :-)), but
> > > this driver is using some of the exported functions.
> > > "  
> > 
> > We don't export functions that has no in-kernel users :)
> 
> But then, I can't export device driver related functions, because
> there's no official device driver yet :-). So what should I do?

Export them when you have a driver.  Or better yet, submit a driver as
part of the patch series.  Why would we want infrastructure that no one
uses?

thanks,

greg k-h
Boris Brezillon Feb. 21, 2018, 2:22 p.m. UTC | #10 
Hi Greg,

On Tue, 19 Dec 2017 10:36:43 +0100
Greg Kroah-Hartman <gregkh@linuxfoundation.org> wrote:

> On Tue, Dec 19, 2017 at 10:28:58AM +0100, Boris Brezillon wrote:
> > On Tue, 19 Dec 2017 10:21:19 +0100
> > Greg Kroah-Hartman <gregkh@linuxfoundation.org> wrote:
> >   
> > > On Tue, Dec 19, 2017 at 10:13:36AM +0100, Boris Brezillon wrote:  
> > > > On Tue, 19 Dec 2017 10:09:00 +0100
> > > > Boris Brezillon <boris.brezillon@free-electrons.com> wrote:
> > > >     
> > > > > On Tue, 19 Dec 2017 09:52:50 +0100
> > > > > Greg Kroah-Hartman <gregkh@linuxfoundation.org> wrote:
> > > > >     
> > > > > > On Thu, Dec 14, 2017 at 04:16:05PM +0100, Boris Brezillon wrote:      
> > > > > > > +/**
> > > > > > > + * i3c_device_match_id() - Find the I3C device ID entry matching an I3C dev
> > > > > > > + * @i3cdev: the I3C device we're searching a match for
> > > > > > > + * @id_table: the I3C device ID table
> > > > > > > + *
> > > > > > > + * Return: a pointer to the first entry matching @i3cdev, or NULL if there's
> > > > > > > + *	   no match.
> > > > > > > + */
> > > > > > > +const struct i3c_device_id *
> > > > > > > +i3c_device_match_id(struct i3c_device *i3cdev,
> > > > > > > +		    const struct i3c_device_id *id_table)
> > > > > > > +{
> > > > > > > +	const struct i3c_device_id *id;
> > > > > > > +
> > > > > > > +	/*
> > > > > > > +	 * The lower 32bits of the provisional ID is just filled with a random
> > > > > > > +	 * value, try to match using DCR info.
> > > > > > > +	 */
> > > > > > > +	if (!I3C_PID_RND_LOWER_32BITS(i3cdev->info.pid)) {
> > > > > > > +		u16 manuf = I3C_PID_MANUF_ID(i3cdev->info.pid);
> > > > > > > +		u16 part = I3C_PID_PART_ID(i3cdev->info.pid);
> > > > > > > +		u16 ext_info = I3C_PID_EXTRA_INFO(i3cdev->info.pid);
> > > > > > > +
> > > > > > > +		/* First try to match by manufacturer/part ID. */
> > > > > > > +		for (id = id_table; id->match_flags != 0; id++) {
> > > > > > > +			if ((id->match_flags & I3C_MATCH_MANUF_AND_PART) !=
> > > > > > > +			    I3C_MATCH_MANUF_AND_PART)
> > > > > > > +				continue;
> > > > > > > +
> > > > > > > +			if (manuf != id->manuf_id || part != id->part_id)
> > > > > > > +				continue;
> > > > > > > +
> > > > > > > +			if ((id->match_flags & I3C_MATCH_EXTRA_INFO) &&
> > > > > > > +			    ext_info != id->extra_info)
> > > > > > > +				continue;
> > > > > > > +
> > > > > > > +			return id;
> > > > > > > +		}
> > > > > > > +	}
> > > > > > > +
> > > > > > > +	/* Fallback to DCR match. */
> > > > > > > +	for (id = id_table; id->match_flags != 0; id++) {
> > > > > > > +		if ((id->match_flags & I3C_MATCH_DCR) &&
> > > > > > > +		    id->dcr == i3cdev->info.dcr)
> > > > > > > +			return id;
> > > > > > > +	}
> > > > > > > +
> > > > > > > +	return NULL;
> > > > > > > +}
> > > > > > > +EXPORT_SYMBOL_GPL(i3c_device_match_id);        
> > > > > > 
> > > > > > I just picked one random export here, but it feels like you are
> > > > > > exporting a bunch of symbols you don't need to.  Why would something
> > > > > > outside of the i3c "core" need to call this function?      
> > > > > 
> > > > > Because I'm not passing the i3c_device_id to the ->probe() method, and
> > > > > if the driver is supporting different variants of the device, it may
> > > > > want to know which one is being probed.
> > > > > 
> > > > > I considered retrieving this information in the core just before probing
> > > > > the driver and passing it to the ->probe() function, but it means
> > > > > having an extra i3c_device_match_id() call for everyone even those who
> > > > > don't care about the device_id information, so I thought exporting this
> > > > > function was a good alternative (device drivers can use it when they
> > > > > actually need to retrieve the device_id).
> > > > > 
> > > > > Anyway, that's something I can change if you think passing the
> > > > > i3c_device_id to the ->probe() method is preferable.
> > > > >     
> > > > > > Have you looked
> > > > > > to see if you really have callers for everything you are exporting?      
> > > > > 
> > > > > Yes, I tried to only export functions that I think will be needed by
> > > > > I3C device drivers and I3C master drivers. Note that I didn't post the
> > > > > dummy device driver I developed to test the framework (partly because
> > > > > this is     
> > > > 
> > > > Sorry, I hit the send button before finishing my sentence :-).
> > > > 
> > > > "
> > > > Note that I didn't post the dummy device driver [1] I developed to test
> > > > the framework (partly because the quality of the code does not meet
> > > > mainline standards and I was ashamed of posting it publicly :-)), but
> > > > this driver is using some of the exported functions.
> > > > "    
> > > 
> > > We don't export functions that has no in-kernel users :)  
> > 
> > But then, I can't export device driver related functions, because
> > there's no official device driver yet :-). So what should I do?  
> 
> Export them when you have a driver.  Or better yet, submit a driver as
> part of the patch series.  Why would we want infrastructure that no one
> uses?

I understand your point of view, it may sound odd to add a framework
for a bus that we have no slave devices for. But, as far as I can tell,
many vendors (both IP vendors and sensor manufacturers) are working
actively on creating master and slave I3C devices. Actually, I've even
been contacted privately by an IP vendor after posting this patchset.
So, I think one argument for pushing the current framework with no
users yet is that it may help others develop drivers for their device
early on, or even help them test those devices more easily than if they
had to develop baremetal code.

The kernel community has been asking hardware vendors for a long time to
upstream their code as early as possible. And this is exactly what is
happening with I3C: even before actual devices are shipping, we have
the opportunity to start merging support for I3C in the mainline
kernel. It would be good to merge it before vendors spend time working
on competing implementations, which will take even more time to
reconcile when they will be submitted for upstream inclusion.

Also, we're not talking about some random bus/protocol, I3C spec is
developed and pushed by MIPI, and for once, they decided to open the
spec, so anyone can actually make sure the framework is matching the
protocol description if they want to.

Now, if you still think an I3C device driver is needed to consider
merging these patches, I can provide one. As I said earlier, I
developed a driver for a dummy device to test the various features I
add support for in this series, it's just that this device will never
ever be available in real life and it's not even fitting in any of the
subsystem we have in the kernel, hence my initial decision to not
upstream it.

Regards,

Boris
Greg KH Feb. 21, 2018, 2:38 p.m. UTC | #11 
On Wed, Feb 21, 2018 at 03:22:48PM +0100, Boris Brezillon wrote:
> Hi Greg,
> 
> On Tue, 19 Dec 2017 10:36:43 +0100
> Greg Kroah-Hartman <gregkh@linuxfoundation.org> wrote:
> 
> > On Tue, Dec 19, 2017 at 10:28:58AM +0100, Boris Brezillon wrote:
> > > On Tue, 19 Dec 2017 10:21:19 +0100
> > > Greg Kroah-Hartman <gregkh@linuxfoundation.org> wrote:
> > >   
> > > > On Tue, Dec 19, 2017 at 10:13:36AM +0100, Boris Brezillon wrote:  
> > > > > On Tue, 19 Dec 2017 10:09:00 +0100
> > > > > Boris Brezillon <boris.brezillon@free-electrons.com> wrote:
> > > > >     
> > > > > > On Tue, 19 Dec 2017 09:52:50 +0100
> > > > > > Greg Kroah-Hartman <gregkh@linuxfoundation.org> wrote:
> > > > > >     
> > > > > > > On Thu, Dec 14, 2017 at 04:16:05PM +0100, Boris Brezillon wrote:      
> > > > > > > > +/**
> > > > > > > > + * i3c_device_match_id() - Find the I3C device ID entry matching an I3C dev
> > > > > > > > + * @i3cdev: the I3C device we're searching a match for
> > > > > > > > + * @id_table: the I3C device ID table
> > > > > > > > + *
> > > > > > > > + * Return: a pointer to the first entry matching @i3cdev, or NULL if there's
> > > > > > > > + *	   no match.
> > > > > > > > + */
> > > > > > > > +const struct i3c_device_id *
> > > > > > > > +i3c_device_match_id(struct i3c_device *i3cdev,
> > > > > > > > +		    const struct i3c_device_id *id_table)
> > > > > > > > +{
> > > > > > > > +	const struct i3c_device_id *id;
> > > > > > > > +
> > > > > > > > +	/*
> > > > > > > > +	 * The lower 32bits of the provisional ID is just filled with a random
> > > > > > > > +	 * value, try to match using DCR info.
> > > > > > > > +	 */
> > > > > > > > +	if (!I3C_PID_RND_LOWER_32BITS(i3cdev->info.pid)) {
> > > > > > > > +		u16 manuf = I3C_PID_MANUF_ID(i3cdev->info.pid);
> > > > > > > > +		u16 part = I3C_PID_PART_ID(i3cdev->info.pid);
> > > > > > > > +		u16 ext_info = I3C_PID_EXTRA_INFO(i3cdev->info.pid);
> > > > > > > > +
> > > > > > > > +		/* First try to match by manufacturer/part ID. */
> > > > > > > > +		for (id = id_table; id->match_flags != 0; id++) {
> > > > > > > > +			if ((id->match_flags & I3C_MATCH_MANUF_AND_PART) !=
> > > > > > > > +			    I3C_MATCH_MANUF_AND_PART)
> > > > > > > > +				continue;
> > > > > > > > +
> > > > > > > > +			if (manuf != id->manuf_id || part != id->part_id)
> > > > > > > > +				continue;
> > > > > > > > +
> > > > > > > > +			if ((id->match_flags & I3C_MATCH_EXTRA_INFO) &&
> > > > > > > > +			    ext_info != id->extra_info)
> > > > > > > > +				continue;
> > > > > > > > +
> > > > > > > > +			return id;
> > > > > > > > +		}
> > > > > > > > +	}
> > > > > > > > +
> > > > > > > > +	/* Fallback to DCR match. */
> > > > > > > > +	for (id = id_table; id->match_flags != 0; id++) {
> > > > > > > > +		if ((id->match_flags & I3C_MATCH_DCR) &&
> > > > > > > > +		    id->dcr == i3cdev->info.dcr)
> > > > > > > > +			return id;
> > > > > > > > +	}
> > > > > > > > +
> > > > > > > > +	return NULL;
> > > > > > > > +}
> > > > > > > > +EXPORT_SYMBOL_GPL(i3c_device_match_id);        
> > > > > > > 
> > > > > > > I just picked one random export here, but it feels like you are
> > > > > > > exporting a bunch of symbols you don't need to.  Why would something
> > > > > > > outside of the i3c "core" need to call this function?      
> > > > > > 
> > > > > > Because I'm not passing the i3c_device_id to the ->probe() method, and
> > > > > > if the driver is supporting different variants of the device, it may
> > > > > > want to know which one is being probed.
> > > > > > 
> > > > > > I considered retrieving this information in the core just before probing
> > > > > > the driver and passing it to the ->probe() function, but it means
> > > > > > having an extra i3c_device_match_id() call for everyone even those who
> > > > > > don't care about the device_id information, so I thought exporting this
> > > > > > function was a good alternative (device drivers can use it when they
> > > > > > actually need to retrieve the device_id).
> > > > > > 
> > > > > > Anyway, that's something I can change if you think passing the
> > > > > > i3c_device_id to the ->probe() method is preferable.
> > > > > >     
> > > > > > > Have you looked
> > > > > > > to see if you really have callers for everything you are exporting?      
> > > > > > 
> > > > > > Yes, I tried to only export functions that I think will be needed by
> > > > > > I3C device drivers and I3C master drivers. Note that I didn't post the
> > > > > > dummy device driver I developed to test the framework (partly because
> > > > > > this is     
> > > > > 
> > > > > Sorry, I hit the send button before finishing my sentence :-).
> > > > > 
> > > > > "
> > > > > Note that I didn't post the dummy device driver [1] I developed to test
> > > > > the framework (partly because the quality of the code does not meet
> > > > > mainline standards and I was ashamed of posting it publicly :-)), but
> > > > > this driver is using some of the exported functions.
> > > > > "    
> > > > 
> > > > We don't export functions that has no in-kernel users :)  
> > > 
> > > But then, I can't export device driver related functions, because
> > > there's no official device driver yet :-). So what should I do?  
> > 
> > Export them when you have a driver.  Or better yet, submit a driver as
> > part of the patch series.  Why would we want infrastructure that no one
> > uses?
> 
> I understand your point of view, it may sound odd to add a framework
> for a bus that we have no slave devices for. But, as far as I can tell,
> many vendors (both IP vendors and sensor manufacturers) are working
> actively on creating master and slave I3C devices. Actually, I've even
> been contacted privately by an IP vendor after posting this patchset.
> So, I think one argument for pushing the current framework with no
> users yet is that it may help others develop drivers for their device
> early on, or even help them test those devices more easily than if they
> had to develop baremetal code.
> 
> The kernel community has been asking hardware vendors for a long time to
> upstream their code as early as possible. And this is exactly what is
> happening with I3C: even before actual devices are shipping, we have
> the opportunity to start merging support for I3C in the mainline
> kernel. It would be good to merge it before vendors spend time working
> on competing implementations, which will take even more time to
> reconcile when they will be submitted for upstream inclusion.

But without real users of an api, you do not even know if it works or
not at all.  In reality, you need at least 3 users of an api to know if
it is correct.  How do you even know this works or not?

Again, we don't merge "frameworks" that no one uses.

> Also, we're not talking about some random bus/protocol, I3C spec is
> developed and pushed by MIPI, and for once, they decided to open the
> spec, so anyone can actually make sure the framework is matching the
> protocol description if they want to.

One might consider i3c any "random" bus, given that there are no devices
for it yet :)

> Now, if you still think an I3C device driver is needed to consider
> merging these patches, I can provide one. As I said earlier, I
> developed a driver for a dummy device to test the various features I
> add support for in this series, it's just that this device will never
> ever be available in real life and it's not even fitting in any of the
> subsystem we have in the kernel, hence my initial decision to not
> upstream it.

What is stopping you from working with one of those aformentioned
companies to get a driver working for their hardware?  Without that type
of testing, you don't even know if your framework is correct or not.
Dummy drivers are nice, but those are written to fit into your framework
more than they are to driver an actual device, which might require
changes to the framework.

So please, just work with those companies, get a real driver, and then
I will be glad to merge it all, driver included.

thanks,

greg k-h
Vitor Soares Feb. 23, 2018, 4:56 p.m. UTC | #12 
Hi Boris,

Às 3:16 PM de 12/14/2017, Boris Brezillon escreveu:
> +
> +enum i3c_addr_slot_status i3c_bus_get_addr_slot_status(struct i3c_bus *bus,
> +						       u16 addr)
> +{
> +	int status, bitpos = addr * 2;
> +
> +	if (addr > I2C_MAX_ADDR)
> +		return I3C_ADDR_SLOT_RSVD;
> +
> +	status = bus->addrslots[bitpos / BITS_PER_LONG];
> +	status >>= bitpos % BITS_PER_LONG;
> +
> +	return status & I3C_ADDR_SLOT_STATUS_MASK;
> +}

I don't understand the size of addr. The I3C only allow 7-bit addresses.

Is the addrslots used to store the addresses and its status?

> +
> +void i3c_bus_set_addr_slot_status(struct i3c_bus *bus, u16 addr,
> +				  enum i3c_addr_slot_status status)
> +{
> +	int bitpos = addr * 2;
> +	unsigned long *ptr;
> +
> +	if (addr > I2C_MAX_ADDR)
> +		return;
> +
> +	ptr = bus->addrslots + (bitpos / BITS_PER_LONG);
> +	*ptr &= ~(I3C_ADDR_SLOT_STATUS_MASK << (bitpos % BITS_PER_LONG));
> +	*ptr |= status << (bitpos % BITS_PER_LONG);
> +}
> +
> +bool i3c_bus_dev_addr_is_avail(struct i3c_bus *bus, u8 addr)
> +{
> +	enum i3c_addr_slot_status status;
> +
> +	status = i3c_bus_get_addr_slot_status(bus, addr);
> +
> +	return status == I3C_ADDR_SLOT_FREE;
> +}
> +
> +int i3c_bus_get_free_addr(struct i3c_bus *bus, u8 start_addr)
> +{
> +	enum i3c_addr_slot_status status;
> +	u8 addr;
> +
> +	for (addr = start_addr; addr < I3C_MAX_ADDR; addr++) {
> +		status = i3c_bus_get_addr_slot_status(bus, addr);
> +		if (status == I3C_ADDR_SLOT_FREE)
> +			return addr;
> +	}
> +
> +	return -ENOMEM;
> +}
> +
> +static void i3c_bus_init_addrslots(struct i3c_bus *bus)
> +{
> +	int i;
> +
> +	/* Addresses 0 to 7 are reserved. */
> +	for (i = 0; i < 8; i++)
> +		i3c_bus_set_addr_slot_status(bus, i, I3C_ADDR_SLOT_RSVD);
> +
> +	/*
> +	 * Reserve broadcast address and all addresses that might collide
> +	 * with the broadcast address when facing a single bit error.
> +	 */
> +	i3c_bus_set_addr_slot_status(bus, I3C_BROADCAST_ADDR,
> +				     I3C_ADDR_SLOT_RSVD);
> +	for (i = 0; i < 7; i++)
> +		i3c_bus_set_addr_slot_status(bus, I3C_BROADCAST_ADDR ^ BIT(i),
> +					     I3C_ADDR_SLOT_RSVD);
> +}
> +
> +static const char * const i3c_bus_mode_strings[] = {
> +	[I3C_BUS_MODE_PURE] = "pure",
> +	[I3C_BUS_MODE_MIXED_FAST] = "mixed-fast",
> +	[I3C_BUS_MODE_MIXED_SLOW] = "mixed-slow",
> +};
> +
> +static ssize_t mode_show(struct device *dev,
> +			 struct device_attribute *da,
> +			 char *buf)
> +{
> +	struct i3c_bus *i3cbus = container_of(dev, struct i3c_bus, dev);
> +	ssize_t ret;
> +
> +	i3c_bus_normaluse_lock(i3cbus);
> +	if (i3cbus->mode < 0 ||
> +	    i3cbus->mode > ARRAY_SIZE(i3c_bus_mode_strings) ||
> +	    !i3c_bus_mode_strings[i3cbus->mode])
> +		ret = sprintf(buf, "unknown\n");
> +	else
> +		ret = sprintf(buf, "%s\n", i3c_bus_mode_strings[i3cbus->mode]);
> +	i3c_bus_normaluse_unlock(i3cbus);
> +
> +	return ret;
> +}
> +static DEVICE_ATTR_RO(mode);
> +
> +static ssize_t current_master_show(struct device *dev,
> +				   struct device_attribute *da,
> +				   char *buf)
> +{
> +	struct i3c_bus *i3cbus = container_of(dev, struct i3c_bus, dev);
> +	ssize_t ret;
> +
> +	i3c_bus_normaluse_lock(i3cbus);
> +	ret = sprintf(buf, "%s\n", dev_name(&i3cbus->cur_master->dev));
> +	i3c_bus_normaluse_unlock(i3cbus);
> +
> +	return ret;
> +}
> +static DEVICE_ATTR_RO(current_master);
> +
> +static ssize_t i3c_scl_frequency_show(struct device *dev,
> +				      struct device_attribute *da,
> +				      char *buf)
> +{
> +	struct i3c_bus *i3cbus = container_of(dev, struct i3c_bus, dev);
> +	ssize_t ret;
> +
> +	i3c_bus_normaluse_lock(i3cbus);
> +	ret = sprintf(buf, "%ld\n", i3cbus->scl_rate.i3c);
> +	i3c_bus_normaluse_unlock(i3cbus);
> +
> +	return ret;
> +}
> +static DEVICE_ATTR_RO(i3c_scl_frequency);
> +
> +static ssize_t i2c_scl_frequency_show(struct device *dev,
> +				      struct device_attribute *da,
> +				      char *buf)
> +{
> +	struct i3c_bus *i3cbus = container_of(dev, struct i3c_bus, dev);
> +	ssize_t ret;
> +
> +	i3c_bus_normaluse_lock(i3cbus);
> +	ret = sprintf(buf, "%ld\n", i3cbus->scl_rate.i2c);
> +	i3c_bus_normaluse_unlock(i3cbus);
> +
> +	return ret;
> +}
> +static DEVICE_ATTR_RO(i2c_scl_frequency);
> +
> +static struct attribute *i3c_busdev_attrs[] = {
> +	&dev_attr_mode.attr,
> +	&dev_attr_current_master.attr,
> +	&dev_attr_i3c_scl_frequency.attr,
> +	&dev_attr_i2c_scl_frequency.attr,
> +	NULL,
> +};
> +ATTRIBUTE_GROUPS(i3c_busdev);
> +
> +static void i3c_busdev_release(struct device *dev)
> +{
> +	struct i3c_bus *bus = container_of(dev, struct i3c_bus, dev);
> +
> +	while (!list_empty(&bus->devs.i2c)) {
> +		struct i2c_device *i2cdev;
> +
> +		i2cdev = list_first_entry(&bus->devs.i2c, struct i2c_device,
> +					  common.node);
> +		list_del(&i2cdev->common.node);
> +		of_node_put(i2cdev->info.of_node);
> +		kfree(i2cdev);
> +	}
> +
> +	while (!list_empty(&bus->devs.i3c)) {
> +		struct i3c_device *i3cdev;
> +
> +		i3cdev = list_first_entry(&bus->devs.i3c, struct i3c_device,
> +					  common.node);
> +		list_del(&i3cdev->common.node);
> +		put_device(&i3cdev->dev);
> +	}
> +
> +	mutex_lock(&i3c_core_lock);
> +	idr_remove(&i3c_bus_idr, bus->id);
> +	mutex_unlock(&i3c_core_lock);
> +
> +	of_node_put(bus->dev.of_node);
> +	kfree(bus);
> +}
> +
> +static const struct device_type i3c_busdev_type = {
> +	.groups	= i3c_busdev_groups,
> +};
> +
> +void i3c_bus_unref(struct i3c_bus *bus)
> +{
> +	put_device(&bus->dev);
> +}
> +
> +struct i3c_bus *i3c_bus_create(struct device *parent)
> +{
> +	struct i3c_bus *i3cbus;
> +	int ret;
> +
> +	i3cbus = kzalloc(sizeof(*i3cbus), GFP_KERNEL);
> +	if (!i3cbus)
> +		return ERR_PTR(-ENOMEM);
> +
> +	init_rwsem(&i3cbus->lock);
> +	INIT_LIST_HEAD(&i3cbus->devs.i2c);
> +	INIT_LIST_HEAD(&i3cbus->devs.i3c);
> +	i3c_bus_init_addrslots(i3cbus);
> +	i3cbus->mode = I3C_BUS_MODE_PURE;
> +	i3cbus->dev.parent = parent;
> +	i3cbus->dev.of_node = of_node_get(parent->of_node);
> +	i3cbus->dev.bus = &i3c_bus_type;
> +	i3cbus->dev.type = &i3c_busdev_type;
> +	i3cbus->dev.release = i3c_busdev_release;
> +
> +	mutex_lock(&i3c_core_lock);
> +	ret = idr_alloc(&i3c_bus_idr, i3cbus, 0, 0, GFP_KERNEL);
> +	mutex_unlock(&i3c_core_lock);
> +	if (ret < 0)
> +		goto err_free_bus;
> +
> +	i3cbus->id = ret;
> +	device_initialize(&i3cbus->dev);
> +
> +	return i3cbus;
> +
> +err_free_bus:
> +	kfree(i3cbus);
> +
> +	return ERR_PTR(ret);
> +}
> +
> +void i3c_bus_unregister(struct i3c_bus *bus)
> +{
> +	device_unregister(&bus->dev);
> +}
> +
> +int i3c_bus_register(struct i3c_bus *i3cbus)
> +{
> +	struct i2c_device *i2cdev;
> +
> +	i3c_bus_for_each_i2cdev(i3cbus, i2cdev) {
> +		switch (i2cdev->lvr & I3C_LVR_I2C_INDEX_MASK) {
> +		case I3C_LVR_I2C_INDEX(0):
> +			if (i3cbus->mode < I3C_BUS_MODE_MIXED_FAST)
> +				i3cbus->mode = I3C_BUS_MODE_MIXED_FAST;
> +			break;
> +
> +		case I3C_LVR_I2C_INDEX(1):
> +		case I3C_LVR_I2C_INDEX(2):
> +			if (i3cbus->mode < I3C_BUS_MODE_MIXED_SLOW)
> +				i3cbus->mode = I3C_BUS_MODE_MIXED_SLOW;
> +			break;
> +
> +		default:
> +			return -EINVAL;
> +		}
> +	}
> +
> +	if (!i3cbus->scl_rate.i3c)
> +		i3cbus->scl_rate.i3c = I3C_BUS_TYP_I3C_SCL_RATE;
> +
> +	if (!i3cbus->scl_rate.i2c) {
> +		if (i3cbus->mode == I3C_BUS_MODE_MIXED_SLOW)
> +			i3cbus->scl_rate.i2c = I3C_BUS_I2C_FM_SCL_RATE;
> +		else
> +			i3cbus->scl_rate.i2c = I3C_BUS_I2C_FM_PLUS_SCL_RATE;
> +	}
> +
> +	/*
> +	 * I3C/I2C frequency may have been overridden, check that user-provided
> +	 * values are not exceeding max possible frequency.
> +	 */
> +	if (i3cbus->scl_rate.i3c > I3C_BUS_MAX_I3C_SCL_RATE ||
> +	    i3cbus->scl_rate.i2c > I3C_BUS_I2C_FM_PLUS_SCL_RATE) {
> +		return -EINVAL;
> +	}
> +
> +	dev_set_name(&i3cbus->dev, "i3c-%d", i3cbus->id);
> +
> +	return device_add(&i3cbus->dev);
> +}
> +
> +static int __init i3c_init(void)
> +{
> +	return bus_register(&i3c_bus_type);
> +}
> +subsys_initcall(i3c_init);
> +
> +static void __exit i3c_exit(void)
> +{
> +	idr_destroy(&i3c_bus_idr);
> +	bus_unregister(&i3c_bus_type);
> +}
> +module_exit(i3c_exit);
> +
> +MODULE_AUTHOR("Boris Brezillon<boris.brezillon@free-electrons.com>");
> +MODULE_DESCRIPTION("I3C core");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/i3c/device.c b/drivers/i3c/device.c
> new file mode 100644
> index 000000000000..dcf51150b7cb
> --- /dev/null
> +++ b/drivers/i3c/device.c
> @@ -0,0 +1,344 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2017 Cadence Design Systems Inc.
> + *
> + * Author: Boris Brezillon<boris.brezillon@free-electrons.com>
> + */
> +
> +#include <linux/slab.h>
> +
> +#include "internals.h"
> +
> +/**
> + * i3c_device_do_priv_xfers() - do I3C SDR private transfers directed to a
> + *				specific device
> + *
> + * @dev: device with which the transfers should be done
> + * @xfers: array of transfers
> + * @nxfers: number of transfers
> + *
> + * Initiate one or several private SDR transfers with @dev.
> + *
> + * This function can sleep and thus cannot be called in atomic context.
> + *
> + * Return: 0 in case of success, a negative error core otherwise.
> + */
> +int i3c_device_do_priv_xfers(struct i3c_device *dev,
> +			     struct i3c_priv_xfer *xfers,
> +			     int nxfers)
> +{
> +	struct i3c_master_controller *master;
> +	int i, ret;
> +
> +	master = i3c_device_get_master(dev);
> +	if (!master)
> +		return -EINVAL;
> +
> +	i3c_bus_normaluse_lock(master->bus);
> +	for (i = 0; i < nxfers; i++)
> +		xfers[i].addr = dev->info.dyn_addr;
> +
> +	ret = i3c_master_do_priv_xfers_locked(master, xfers, nxfers);
> +	i3c_bus_normaluse_unlock(master->bus);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(i3c_device_do_priv_xfers);

 The controller should know the speed mode for each xfer. The SDR0 mode 
is used by default but if any device have read or write speed 
limitations the controller can use SDRx.

This could be also applied to i2c transfers.
> +#endif /* I3C_INTERNAL_H */
> diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c
> new file mode 100644
> index 000000000000..1c85abac08d5
> --- /dev/null
> +++ b/drivers/i3c/master.c
> @@ -0,0 +1,1433 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2017 Cadence Design Systems Inc.
> + *
> + * Author: Boris Brezillon<boris.brezillon@free-electrons.com>
> + */
> +
> +#include <linux/slab.h>
> +
> +#include "internals.h"
> +
> +/**
> + * i3c_master_entdaa_locked() - start a DAA (Dynamic Address Assignment)
> + *				procedure
> + * @master: master used to send frames on the bus
> + *
> + * Send a ENTDAA CCC command to start a DAA procedure.
> + *
> + * Note that this function only sends the ENTDAA CCC command, all the logic
> + * behind dynamic address assignment has to be handled in the I3C master
> + * driver.
> + *
> + * This function must be called with the bus lock held in write mode.
> + *
> + * Return: 0 in case of success, a negative error code otherwise.
> + */
> +int i3c_master_entdaa_locked(struct i3c_master_controller *master)
> +{
> +	struct i3c_ccc_cmd_dest dest = { };
> +	struct i3c_ccc_cmd cmd = { };
> +	int ret;
> +
> +	dest.addr = I3C_BROADCAST_ADDR;
> +	cmd.dests = &dest;
> +	cmd.ndests = 1;
> +	cmd.rnw = false;
> +	cmd.id = I3C_CCC_ENTDAA;
> +
> +	ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
> +	if (ret)
> +		return ret;
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(i3c_master_entdaa_locked);

 can you explain the process?  the command is only execute once, what if 
there is more devices on the bus?

 > +
> +/**
> + * i3c_master_defslvs_locked() - send a DEFSLVS CCC command
> + * @master: master used to send frames on the bus
> + *
> + * Send a DEFSLVS CCC command containing all the devices known to the @master.
> + * This is useful when you have secondary masters on the bus to propagate
> + * device information.
> + *
> + * This should be called after all I3C devices have been discovered (in other
> + * words, after the DAA procedure has finished) and instantiated in
> + * i3c_master_controller_ops->bus_init().
> + * It should also be called if a master ACKed an Hot-Join request and assigned
> + * a dynamic address to the device joining the bus.
> + *
> + * This function must be called with the bus lock held in write mode.
> + *
> + * Return: 0 in case of success, a negative error code otherwise.
> + */
> +int i3c_master_defslvs_locked(struct i3c_master_controller *master)
> +{
> +	struct i3c_ccc_cmd_dest dest = {
> +		.addr = I3C_BROADCAST_ADDR,
> +	};
> +	struct i3c_ccc_cmd cmd = {
> +		.id = I3C_CCC_DEFSLVS,
> +		.dests = &dest,
> +		.ndests = 1,
> +	};
> +	struct i3c_ccc_defslvs *defslvs;
> +	struct i3c_ccc_dev_desc *desc;
> +	struct i3c_device *i3cdev;
> +	struct i2c_device *i2cdev;
> +	struct i3c_bus *bus;
> +	bool send = false;
> +	int ndevs = 0, ret;
> +
> +	if (!master)
> +		return -EINVAL;
> +
> +	bus = i3c_master_get_bus(master);
> +	i3c_bus_for_each_i3cdev(bus, i3cdev) {
> +		ndevs++;
> +		if (I3C_BCR_DEVICE_ROLE(i3cdev->info.bcr) == I3C_BCR_I3C_MASTER)
> +			send = true;
> +	}
> +
> +	/* No other master on the bus, skip DEFSLVS. */
> +	if (!send)
> +		return 0;
> +
> +	i3c_bus_for_each_i2cdev(bus, i2cdev)
> +		ndevs++;
> +
> +	dest.payload.len = sizeof(*defslvs) +
> +			   ((ndevs - 1) * sizeof(struct i3c_ccc_dev_desc));
> +	defslvs = kzalloc(dest.payload.len, GFP_KERNEL);
> +	if (!defslvs)
> +		return -ENOMEM;
> +
> +	dest.payload.data = defslvs;
> +
> +	defslvs->count = ndevs;
> +	defslvs->master.bcr = master->this->info.bcr;
> +	defslvs->master.dcr = master->this->info.dcr;
> +	defslvs->master.dyn_addr = master->this->info.dyn_addr;
> +	defslvs->master.static_addr = I3C_BROADCAST_ADDR;

 Why defslvs->master.static_addr = I3C_BROADCAST_ADDR?

 > +
> +	desc = defslvs->slaves;
> +	i3c_bus_for_each_i2cdev(bus, i2cdev) {
> +		desc->lvr = i2cdev->lvr;
> +		desc->static_addr = i2cdev->info.addr;
> +		desc++;
> +	}
> +
> +	i3c_bus_for_each_i3cdev(bus, i3cdev) {
> +		/* Skip the I3C dev representing this master. */
> +		if (i3cdev == master->this)
> +			continue;
> +
> +		desc->bcr = i3cdev->info.bcr;
> +		desc->dcr = i3cdev->info.dcr;
> +		desc->dyn_addr = i3cdev->info.dyn_addr;
> +		desc->static_addr = i3cdev->info.static_addr;
> +		desc++;
> +	}
> +
> +	ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
> +	kfree(defslvs);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(i3c_master_defslvs_locked);
> +
> +
> +static int i3c_master_i2c_adapter_xfer(struct i2c_adapter *adap,
> +				       struct i2c_msg *xfers, int nxfers)
> +{
> +	struct i3c_master_controller *master = i2c_adapter_to_i3c_master(adap);
> +	int i, ret;
> +
> +	for (i = 0; i < nxfers; i++) {
> +		enum i3c_addr_slot_status status;
> +
> +		status = i3c_bus_get_addr_slot_status(master->bus,
> +						      xfers[i].addr);
> +		if (status != I3C_ADDR_SLOT_I2C_DEV)
> +			return -EINVAL;
> +	}
> +
> +	ret = i3c_master_do_i2c_xfers(master, xfers, nxfers);
> +	if (ret)
> +		return ret;
> +
> +	return nxfers;
> +}
> +
> +static u32 i3c_master_i2c_functionalities(struct i2c_adapter *adap)
> +{
> +	return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR;
> +}

 Is I2C_FUNC_10BIT_ADDR allowed ?

 > diff --git a/drivers/i3c/master/Kconfig b/drivers/i3c/master/Kconfig
> new file mode 100644
> index 000000000000..e69de29bb2d1
> diff --git a/drivers/i3c/master/Makefile b/drivers/i3c/master/Makefile
> new file mode 100644
> index 000000000000..e69de29bb2d1
> diff --git a/include/linux/i3c/ccc.h b/include/linux/i3c/ccc.h
> new file mode 100644
> index 000000000000..ff3e1a3e2c4c
> --- /dev/null
> +++ b/include/linux/i3c/ccc.h
> @@ -0,0 +1,380 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2017 Cadence Design Systems Inc.
> + *
> + * Author: Boris Brezillon<boris.brezillon@free-electrons.com>
> + */
> +
> +
> +/**
> + * enum i3c_ccc_test_mode - enum listing all available test modes
> + *
> + * @I3C_CCC_EXIT_TEST_MODE: exit test mode
> + * @I3C_CCC_VENDOR_TEST_MODE: enter vendor test mode
> + */
> +enum i3c_ccc_test_mode {
> +	I3C_CCC_EXIT_TEST_MODE,
> +	I3C_CCC_VENDOR_TEST_MODE,
> +};
> +
> +/**
> + * struct i3c_ccc_enttm - payload passed to ENTTM CCC
> + *
> + * @mode: one of the &enum i3c_ccc_test_mode modes
> + *
> + * Information passed to the ENTTM CCC to instruct an I3C device to enter a
> + * specific test mode.
> + */
> +struct i3c_ccc_enttm {
> +	u8 mode;
> +} __packed;
> +
> +/**
> + * struct i3c_ccc_setda - payload passed to ENTTM CCC
> + *
> + * @mode: one of the &enum i3c_ccc_test_mode modes
> + *
> + * Information passed to the ENTTM CCC to instruct an I3C device to enter a
> + * specific test mode.
> + */
> +struct i3c_ccc_setda {
> +	u8 addr;
> +} __packed;

 what do you mean with struct? Maybe setdasa? if so, what is the addr?

 > +/**
> + * enum i3c_sdr_max_data_rate - max data rate values for private SDR transfers
> + */
> +enum i3c_sdr_max_data_rate {
> +	I3C_SDR_DR_FSCL_MAX,
> +	I3C_SDR_DR_FSCL_8MHZ,
> +	I3C_SDR_DR_FSCL_6MHZ,
> +	I3C_SDR_DR_FSCL_4MHZ,
> +	I3C_SDR_DR_FSCL_2MHZ,
> +};
Can you change the names to:

I3C_SDR0_FSCL_MAX,
I3C_SDR1_FSCL_8MHZ,
I3C_SDR2_FSCL_6MHZ,
I3C_SDR3_FSCL_4MHZ,
I3C_SDR4_FSCL_2MHZ,

thus the data rate isn't repeated.

> +
> +/**
> + * enum i3c_tsco - clock to data turn-around
> + */
> +enum i3c_tsco {
> +	I3C_TSCO_LT_8NS,
> +	I3C_TSCO_LT_9NS,
> +	I3C_TSCO_LT_10NS,
> +	I3C_TSCO_LT_11NS,
> +	I3C_TSCO_LT_12NS,
> +};
what's the meaning of _LT_ ?
> +
> +#endif /* I3C_CCC_H */
> diff --git a/include/linux/i3c/device.h b/include/linux/i3c/device.h
> new file mode 100644
> index 000000000000..83958d3a02e2
> --- /dev/null
> +++ b/include/linux/i3c/device.h
> @@ -0,0 +1,321 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2017 Cadence Design Systems Inc.
> + *
> + * Author: Boris Brezillon<boris.brezillon@free-electrons.com>
> + */
> +
> +#ifndef I3C_DEV_H
> +#define I3C_DEV_H
> +
> +#include <linux/device.h>
> +#include <linux/i2c.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/module.h>
> +
> +/**
> + * enum i3c_hdr_mode - HDR mode ids
> + * @I3C_HDR_DDR: DDR mode
> + * @I3C_HDR_TSP: TSP mode
> + * @I3C_HDR_TSL: TSL mode
> + */
> +enum i3c_hdr_mode {
> +	I3C_HDR_DDR,
> +	I3C_HDR_TSP,
> +	I3C_HDR_TSL,
> +};
> +
> +/**
> + * struct i3c_hdr_cmd - I3C HDR command
> + * @mode: HDR mode selected for this command
> + * @code: command opcode
> + * @addr: I3C dynamic address
> + * @ndatawords: number of data words (a word is 16bits wide)
> + * @data: input/output buffer
> + */
> +struct i3c_hdr_cmd {
> +	enum i3c_hdr_mode mode;
> +	u8 code;
> +	u8 addr;
> +	int ndatawords;
> +	union {
> +		u16 *in;
> +		const u16 *out;
> +	} data;
> +};
> +
> +/* Private SDR read transfer */
> +#define I3C_PRIV_XFER_READ		BIT(0)
> +/*
> + * Instruct the controller to issue a STOP after a specific transfer instead
> + * of a REPEATED START.
> + */
> +#define I3C_PRIV_XFER_STOP		BIT(1)
> +
> +/**
> + * struct i3c_priv_xfer - I3C SDR private transfer
> + * @addr: I3C dynamic address
> + * @len: transfer length in bytes of the transfer
> + * @flags: combination of I3C_PRIV_XFER_xxx flags
> + * @data: input/output buffer
> + */
> +struct i3c_priv_xfer {
> +	u8 addr;
> +	u16 len;
> +	u32 flags;
> +	struct {
> +		void *in;
> +		const void *out;
> +	} data;
> +};

 Same as above, i3c_sdr_max_data_rate to change the bus scl.

 > +
> +/**
> + * enum i3c_dcr - I3C DCR values
> + * @I3C_DCR_GENERIC_DEVICE: generic I3C device
> + */
> +enum i3c_dcr {
> +	I3C_DCR_GENERIC_DEVICE = 0,
> +};
> +
> +#define I3C_PID_MANUF_ID(pid)		(((pid) & GENMASK_ULL(47, 33)) >> 33)
> +#define I3C_PID_RND_LOWER_32BITS(pid)	(!!((pid) & BIT_ULL(32)))
> +#define I3C_PID_RND_VAL(pid)		((pid) & GENMASK_ULL(31, 0))
> +#define I3C_PID_PART_ID(pid)		(((pid) & GENMASK_ULL(31, 16)) >> 16)
> +#define I3C_PID_INSTANCE_ID(pid)	(((pid) & GENMASK_ULL(15, 12)) >> 12)
> +#define I3C_PID_EXTRA_INFO(pid)		((pid) & GENMASK_ULL(11, 0))
> +
> +#define I3C_BCR_DEVICE_ROLE(bcr)	((bcr) & GENMASK(7, 6))
> +#define I3C_BCR_I3C_SLAVE		(0 << 6)
> +#define I3C_BCR_I3C_MASTER		(1 << 6)
> +#define I3C_BCR_HDR_CAP			BIT(5)
> +#define I3C_BCR_BRIDGE			BIT(4)
> +#define I3C_BCR_OFFLINE_CAP		BIT(3)
> +#define I3C_BCR_IBI_PAYLOAD		BIT(2)
> +#define I3C_BCR_IBI_REQ_CAP		BIT(1)
> +#define I3C_BCR_MAX_DATA_SPEED_LIM	BIT(0)
> +
> +/**
> + * struct i3c_device_info - I3C device information
> + * @pid: Provisional ID
> + * @bcr: Bus Characteristic Register
> + * @dcr: Device Characteristic Register
> + * @static_addr: static/I2C address
> + * @dyn_addr: dynamic address
> + * @hdr_cap: supported HDR modes
> + * @max_read_ds: max read speed information
> + * @max_write_ds: max write speed information
> + * @max_ibi_len: max IBI payload length
> + * @max_read_turnaround: max read turn-around time in micro-seconds
> + * @max_read_len: max private SDR read length in bytes
> + * @max_write_len: max private SDR write length in bytes
> + *
> + * These are all basic information that should be advertised by an I3C device.
> + * Some of them are optional depending on the device type and device
> + * capabilities.
> + * For each I3C slave attached to a master with
> + * i3c_master_add_i3c_dev_locked(), the core will send the relevant CCC command
> + * to retrieve these data.
> + */
> +struct i3c_device_info {
> +	u64 pid;
> +	u8 bcr;
> +	u8 dcr;
> +	u8 static_addr;
> +	u8 dyn_addr;
> +	u8 hdr_cap;
> +	u8 max_read_ds;
> +	u8 max_write_ds;
> +	u8 max_ibi_len;
> +	u32 max_read_turnaround;
> +	u16 max_read_len;
> +	u16 max_write_len;
> +};
> +

 is this information filled with data provided from CCC commands?

 > +
> +#endif /* I3C_DEV_H */
> diff --git a/include/linux/i3c/master.h b/include/linux/i3c/master.h
> new file mode 100644
> index 000000000000..7ec9a4821bac
> --- /dev/null
> +++ b/include/linux/i3c/master.h
> @@ -0,0 +1,564 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2017 Cadence Design Systems Inc.
> + *
> + * Author: Boris Brezillon<boris.brezillon@free-electrons.com>
> + */
> +
> +#ifndef I3C_MASTER_H
> +#define I3C_MASTER_H
> +
> +#include <linux/i2c.h>
> +#include <linux/i3c/ccc.h>
> +#include <linux/i3c/device.h>
> +#include <linux/spinlock.h>
> +
> +#define I3C_HOT_JOIN_ADDR		0x2
> +#define I3C_BROADCAST_ADDR		0x7e
> +#define I3C_MAX_ADDR			GENMASK(6, 0)
> +
> +struct i3c_master_controller;
> +struct i3c_bus;
> +
> +/**
> + * struct i3c_i2c_dev - I3C/I2C common information
> + * @node: node element used to insert the device into the I2C or I3C device
> + *	  list
> + * @bus: I3C bus this device is connected to
> + * @master: I3C master that instantiated this device. Will be used to send
> + *	    I2C/I3C frames on the bus
> + * @master_priv: master private data assigned to the device. Can be used to
> + *		 add master specific information
> + *
> + * This structure is describing common I3C/I2C dev information.
> + */
> +struct i3c_i2c_dev {
> +	struct list_head node;
> +	struct i3c_bus *bus;
> +	struct i3c_master_controller *master;
> +	void *master_priv;
> +};
> +
> +#define I3C_LVR_I2C_INDEX_MASK		GENMASK(7, 5)
> +#define I3C_LVR_I2C_INDEX(x)		((x) << 5)
> +#define I3C_LVR_I2C_FM_MODE		BIT(4)
> +
> +#define I2C_MAX_ADDR			GENMASK(9, 0)

 why 10-bit address?

 > +
> +/**
> + * struct i2c_device - I2C device object
> + * @common: inherit common I3C/I2C description
> + * @info: I2C board info used to instantiate the I2C device. If you are
> + *	  using DT to describe your hardware, this will be filled for you
> + * @client: I2C client object created by the I2C framework. This will only
> + *	    be valid after i3c_master_register() returns
> + * @lvr: Legacy Virtual Register value as described in the I3C specification
> + *
> + * I2C device object. Note that the real I2C device is represented by
> + * i2c_device->client, but we need extra information to handle the device when
> + * it's connected to an I3C bus, hence the &struct i2c_device wrapper.
> + *
> + * The I2C framework is not impacted by this new representation.
> + */
> +struct i2c_device {
> +	struct i3c_i2c_dev common;
> +	struct i2c_board_info info;
> +	struct i2c_client *client;
> +	u8 lvr;
> +};
> +

 It is usefull to know the speed limitations of the device.

 > +
> +/**
> + * enum i3c_addr_slot_status - I3C address slot status
> + * @I3C_ADDR_SLOT_FREE: address is free
> + * @I3C_ADDR_SLOT_RSVD: address is reserved
> + * @I3C_ADDR_SLOT_I2C_DEV: address is assigned to an I2C device
> + * @I3C_ADDR_SLOT_I3C_DEV: address is assigned to an I3C device
> + * @I3C_ADDR_SLOT_STATUS_MASK: address slot mask
> + *
> + * On an I3C bus, addresses are assigned dynamically, and we need to know which
> + * addresses are free to use and which ones are already assigned.
> + *
> + * Addresses marked as reserved are those reserved by the I3C protocol
> + * (broadcast address, ...).
> + */
> +enum i3c_addr_slot_status {
> +	I3C_ADDR_SLOT_FREE,
> +	I3C_ADDR_SLOT_RSVD,
> +	I3C_ADDR_SLOT_I2C_DEV,
> +	I3C_ADDR_SLOT_I3C_DEV,
> +	I3C_ADDR_SLOT_STATUS_MASK = 3,
> +};
> +
> +/**
> + * struct i3c_bus - I3C bus object
> + * @dev: device to be registered to the device-model
> + * @cur_master: I3C master currently driving the bus. Since I3C is multi-master
> + *		this can change over the time. Will be used to let a master
> + *		know whether it needs to request bus ownership before sending
> + *		a frame or not
> + * @id: bus ID. Assigned by the framework when register the bus
> + * @addrslots: a bitmap with 2-bits per-slot to encode the address status and
> + *	       ease the DAA (Dynamic Address Assignment) procedure (see
> + *	       &enum i3c_addr_slot_status)
> + * @mode: bus mode (see &enum i3c_bus_mode)
> + * @scl_rate: SCL signal rate for I3C and I2C mode
> + * @devs: 2 lists containing all I3C/I2C devices connected to the bus
> + * @lock: read/write lock on the bus. This is needed to protect against
> + *	  operations that have an impact on the whole bus and the devices
> + *	  connected to it. For example, when asking slaves to drop their
> + *	  dynamic address (RSTDAA CCC), we need to make sure no one is trying
> + *	  to send I3C frames to these devices.
> + *	  Note that this lock does not protect against concurrency between
> + *	  devices: several drivers can send different I3C/I2C frames through
> + *	  the same master in parallel. This is the responsibility of the
> + *	  master to guarantee that frames are actually sent sequentially and
> + *	  not interlaced
> + *
> + * The I3C bus is represented with its own object and not implicitly described
> + * by the I3C master to cope with the multi-master functionality, where one bus
> + * can be shared amongst several masters, each of them requesting bus ownership
> + * when they need to.
> + */
> +struct i3c_bus {
> +	struct device dev;
> +	struct i3c_device *cur_master;
> +	int id;
> +	unsigned long addrslots[((I2C_MAX_ADDR + 1) * 2) / BITS_PER_LONG];
> +	enum i3c_bus_mode mode;
> +	struct {
> +		unsigned long i3c;
> +		unsigned long i2c;
> +	} scl_rate;
> +	struct {
> +		struct list_head i3c;
> +		struct list_head i2c;
> +	} devs;
> +	struct rw_semaphore lock;
> +};
Can you explain the addrslots[] ?
> +
> +static inline struct i3c_device *dev_to_i3cdev(struct device *dev)
> +{
> +	return container_of(dev, struct i3c_device, dev);
> +}
> +
> +struct i3c_master_controller;
> +
> +/**
> + * struct i3c_master_controller_ops - I3C master methods
> + * @bus_init: hook responsible for the I3C bus initialization. This
> + *	      initialization should follow the steps described in the I3C
> + *	      specification. This hook is called with the bus lock held in
> + *	      write mode, which means all _locked() helpers can safely be
> + *	      called from there
> + * @bus_cleanup: cleanup everything done in
> + *		 &i3c_master_controller_ops->bus_init(). This function is
> + *		 optional and should only be implemented if
> + *		 &i3c_master_controller_ops->bus_init() attached private data
> + *		 to I3C/I2C devices. This hook is called with the bus lock
> + *		 held in write mode, which means all _locked() helpers can
> + *		 safely be called from there
> + * @supports_ccc_cmd: should return true if the CCC command is supported, false
> + *		      otherwise
> + * @send_ccc_cmd: send a CCC command
> + * @send_hdr_cmds: send one or several HDR commands. If there is more than one
> + *		   command, they should ideally be sent in the same HDR
> + *		   transaction
> + * @priv_xfers: do one or several private I3C SDR transfers
> + * @i2c_xfers: do one or several I2C transfers
> + * @request_ibi: attach an IBI handler to an I3C device. This implies defining
> + *		 an IBI handler and the constraints of the IBI (maximum payload
> + *		 length and number of pre-allocated slots).
> + *		 Some controllers support less IBI-capable devices than regular
> + *		 devices, so this method might return -%EBUSY if there's no
> + *		 more space for an extra IBI registration
> + * @free_ibi: free an IBI previously requested with ->request_ibi(). The IBI
> + *	      should have been disabled with ->disable_irq() prior to that
> + * @enable_ibi: enable the IBI. Only valid if ->request_ibi() has been called
> + *		prior to ->enable_ibi(). The controller should first enable
> + *		the IBI on the controller end (for example, unmask the hardware
> + *		IRQ) and then send the ENEC CCC command (with the IBI flag set)
> + *		to the I3C device
> + * @disable_ibi: disable an IBI. First send the DISEC CCC command with the IBI
> + *		 flag set and then deactivate the hardware IRQ on the
> + *		 controller end
> + * @recycle_ibi_slot: recycle an IBI slot. Called every time an IBI has been
> + *		      processed by its handler. The IBI slot should be put back
> + *		      in the IBI slot pool so that the controller can re-use it
> + *		      for a future IBI
> + *
> + * One of the most important hooks in these ops is
> + * &i3c_master_controller_ops->bus_init(). Here is a non-exhaustive list of
> + * things that should be done in &i3c_master_controller_ops->bus_init():
> + *
> + * 1) call i3c_master_set_info() with all information describing the master
> + * 2) ask all slaves to drop their dynamic address by sending the RSTDAA CCC
> + *    with i3c_master_rstdaa_locked()
> + * 3) ask all slaves to disable IBIs using i3c_master_disec_locked()
> + * 4) start a DDA procedure by sending the ENTDAA CCC with
> + *    i3c_master_entdaa_locked(), or using the internal DAA logic provided by
> + *    your controller
You mean SETDASA CCC command?
> + * 5) assign a dynamic address to each I3C device discovered during DAA and
> + *    for each of them, call i3c_master_add_i3c_dev_locked()
> + * 6) propagate device table to secondary masters by calling
> + *    i3c_master_defslvs_locked()
> + *
> + * Note that these steps do not include all controller specific initialization.
> + */
> +struct i3c_master_controller_ops {
> +	int (*bus_init)(struct i3c_master_controller *master);
> +	void (*bus_cleanup)(struct i3c_master_controller *master);
> +	bool (*supports_ccc_cmd)(struct i3c_master_controller *master,
> +				 const struct i3c_ccc_cmd *cmd);
> +	int (*send_ccc_cmd)(struct i3c_master_controller *master,
> +			    struct i3c_ccc_cmd *cmd);
> +	int (*send_hdr_cmds)(struct i3c_master_controller *master,
> +			     const struct i3c_hdr_cmd *cmds,
> +			     int ncmds);
> +	int (*priv_xfers)(struct i3c_master_controller *master,
> +			  const struct i3c_priv_xfer *xfers,
> +			  int nxfers);
> +	int (*i2c_xfers)(struct i3c_master_controller *master,
> +			 const struct i2c_msg *xfers, int nxfers);
> +	int (*request_ibi)(struct i3c_master_controller *master,
> +			   struct i3c_device *dev,
> +			   const struct i3c_ibi_setup *req);
> +	void (*free_ibi)(struct i3c_master_controller *master,
> +			 struct i3c_device *dev);
> +	int (*enable_ibi)(struct i3c_master_controller *master,
> +			  struct i3c_device *dev);
> +	int (*disable_ibi)(struct i3c_master_controller *master,
> +			   struct i3c_device *dev);
> +	void (*recycle_ibi_slot)(struct i3c_master_controller *master,
> +				 struct i3c_device *dev,
> +				 struct i3c_ibi_slot *slot);
> +};
> +
>

Best regards,
Vitor Soares
Boris Brezillon Feb. 23, 2018, 8:30 p.m. UTC | #13 
Hi Vitor,

On Fri, 23 Feb 2018 16:56:14 +0000
Vitor Soares <Vitor.Soares@synopsys.com> wrote:

> Hi Boris,
> 
> Às 3:16 PM de 12/14/2017, Boris Brezillon escreveu:
> > +
> > +enum i3c_addr_slot_status i3c_bus_get_addr_slot_status(struct i3c_bus *bus,
> > +						       u16 addr)
> > +{
> > +	int status, bitpos = addr * 2;
> > +
> > +	if (addr > I2C_MAX_ADDR)
> > +		return I3C_ADDR_SLOT_RSVD;
> > +
> > +	status = bus->addrslots[bitpos / BITS_PER_LONG];
> > +	status >>= bitpos % BITS_PER_LONG;
> > +
> > +	return status & I3C_ADDR_SLOT_STATUS_MASK;
> > +}  
> 
> I don't understand the size of addr. The I3C only allow 7-bit addresses.
> 
> Is the addrslots used to store the addresses and its status?

No, slots are used for both I2C and I3C addresses, and an I2C address
can be 10-bits wide, hence the u16 type.


[...]

> > +/**
> > + * i3c_device_do_priv_xfers() - do I3C SDR private transfers directed to a
> > + *				specific device
> > + *
> > + * @dev: device with which the transfers should be done
> > + * @xfers: array of transfers
> > + * @nxfers: number of transfers
> > + *
> > + * Initiate one or several private SDR transfers with @dev.
> > + *
> > + * This function can sleep and thus cannot be called in atomic context.
> > + *
> > + * Return: 0 in case of success, a negative error core otherwise.
> > + */
> > +int i3c_device_do_priv_xfers(struct i3c_device *dev,
> > +			     struct i3c_priv_xfer *xfers,
> > +			     int nxfers)
> > +{
> > +	struct i3c_master_controller *master;
> > +	int i, ret;
> > +
> > +	master = i3c_device_get_master(dev);
> > +	if (!master)
> > +		return -EINVAL;
> > +
> > +	i3c_bus_normaluse_lock(master->bus);
> > +	for (i = 0; i < nxfers; i++)
> > +		xfers[i].addr = dev->info.dyn_addr;
> > +
> > +	ret = i3c_master_do_priv_xfers_locked(master, xfers, nxfers);
> > +	i3c_bus_normaluse_unlock(master->bus);
> > +
> > +	return ret;
> > +}
> > +EXPORT_SYMBOL_GPL(i3c_device_do_priv_xfers);  
> 
>  The controller should know the speed mode for each xfer. The SDR0 mode 
> is used by default but if any device have read or write speed 
> limitations the controller can use SDRx.

I might be wrong, but that's not my understanding of the spec. A device
can express a speed limitation for SDR priv transfers, but this
limitation applies to all SDR transfers.

The speed R/W speed limitation is encoded in the device object, so, if
the controller has to configure that on a per-transfer basis, one
solution would be to pass the device to the ->priv_xfers().

> 
> This could be also applied to i2c transfers.

Not really. The max SCL frequency is something that applies to the
whole bus, because all I2C devices have to decode the address when
messages are sent on the bus to determine if they should ignore or
process the message.

> > +#endif /* I3C_INTERNAL_H */
> > diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c
> > new file mode 100644
> > index 000000000000..1c85abac08d5
> > --- /dev/null
> > +++ b/drivers/i3c/master.c
> > @@ -0,0 +1,1433 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2017 Cadence Design Systems Inc.
> > + *
> > + * Author: Boris Brezillon<boris.brezillon@free-electrons.com>
> > + */
> > +
> > +#include <linux/slab.h>
> > +
> > +#include "internals.h"
> > +
> > +/**
> > + * i3c_master_entdaa_locked() - start a DAA (Dynamic Address Assignment)
> > + *				procedure
> > + * @master: master used to send frames on the bus
> > + *
> > + * Send a ENTDAA CCC command to start a DAA procedure.
> > + *
> > + * Note that this function only sends the ENTDAA CCC command, all the logic
> > + * behind dynamic address assignment has to be handled in the I3C master
> > + * driver.
> > + *
> > + * This function must be called with the bus lock held in write mode.
> > + *
> > + * Return: 0 in case of success, a negative error code otherwise.
> > + */
> > +int i3c_master_entdaa_locked(struct i3c_master_controller *master)
> > +{
> > +	struct i3c_ccc_cmd_dest dest = { };
> > +	struct i3c_ccc_cmd cmd = { };
> > +	int ret;
> > +
> > +	dest.addr = I3C_BROADCAST_ADDR;
> > +	cmd.dests = &dest;
> > +	cmd.ndests = 1;
> > +	cmd.rnw = false;
> > +	cmd.id = I3C_CCC_ENTDAA;
> > +
> > +	ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
> > +	if (ret)
> > +		return ret;
> > +
> > +	return 0;
> > +}
> > +EXPORT_SYMBOL_GPL(i3c_master_entdaa_locked);  
> 
>  can you explain the process?

Not sure what you mean. The ENTDAA is just a CCC command that is used
to trigger a DAA procedure. What the master controller does when it
sends such a command is likely to be controller dependent, and it might
even be possible that you don't need to call this function in your
controller driver to trigger a DAA. If you want more details about the
bus initialization steps and how the ENTDAA CCC command fits into it I
recommend reading section "5.1.4 Bus Initialization and Dynamic Address
Assignment Mode"

> the command is only execute once, what if 
> there is more devices on the bus?

Again, I'm not sure what you mean. The ENTDAA command is sent every
time a controller wants to discover new devices on the bus, that can be
when initializing the bus, after a Hot Join event or simply triggered
by the user (the last case is not supported yet though).

Now, if you're interested in what happens after an ENTDAA CCC is sent,
the controller will keep sending RepeatedStart until there's no more
devices acking the request. You can have a look at "B.3 Error Types in
Dynamic Address Arbitration" for more details.

> 
>  > +
> > +/**
> > + * i3c_master_defslvs_locked() - send a DEFSLVS CCC command
> > + * @master: master used to send frames on the bus
> > + *
> > + * Send a DEFSLVS CCC command containing all the devices known to the @master.
> > + * This is useful when you have secondary masters on the bus to propagate
> > + * device information.
> > + *
> > + * This should be called after all I3C devices have been discovered (in other
> > + * words, after the DAA procedure has finished) and instantiated in
> > + * i3c_master_controller_ops->bus_init().
> > + * It should also be called if a master ACKed an Hot-Join request and assigned
> > + * a dynamic address to the device joining the bus.
> > + *
> > + * This function must be called with the bus lock held in write mode.
> > + *
> > + * Return: 0 in case of success, a negative error code otherwise.
> > + */
> > +int i3c_master_defslvs_locked(struct i3c_master_controller *master)
> > +{
> > +	struct i3c_ccc_cmd_dest dest = {
> > +		.addr = I3C_BROADCAST_ADDR,
> > +	};
> > +	struct i3c_ccc_cmd cmd = {
> > +		.id = I3C_CCC_DEFSLVS,
> > +		.dests = &dest,
> > +		.ndests = 1,
> > +	};
> > +	struct i3c_ccc_defslvs *defslvs;
> > +	struct i3c_ccc_dev_desc *desc;
> > +	struct i3c_device *i3cdev;
> > +	struct i2c_device *i2cdev;
> > +	struct i3c_bus *bus;
> > +	bool send = false;
> > +	int ndevs = 0, ret;
> > +
> > +	if (!master)
> > +		return -EINVAL;
> > +
> > +	bus = i3c_master_get_bus(master);
> > +	i3c_bus_for_each_i3cdev(bus, i3cdev) {
> > +		ndevs++;
> > +		if (I3C_BCR_DEVICE_ROLE(i3cdev->info.bcr) == I3C_BCR_I3C_MASTER)
> > +			send = true;
> > +	}
> > +
> > +	/* No other master on the bus, skip DEFSLVS. */
> > +	if (!send)
> > +		return 0;
> > +
> > +	i3c_bus_for_each_i2cdev(bus, i2cdev)
> > +		ndevs++;
> > +
> > +	dest.payload.len = sizeof(*defslvs) +
> > +			   ((ndevs - 1) * sizeof(struct i3c_ccc_dev_desc));
> > +	defslvs = kzalloc(dest.payload.len, GFP_KERNEL);
> > +	if (!defslvs)
> > +		return -ENOMEM;
> > +
> > +	dest.payload.data = defslvs;
> > +
> > +	defslvs->count = ndevs;
> > +	defslvs->master.bcr = master->this->info.bcr;
> > +	defslvs->master.dcr = master->this->info.dcr;
> > +	defslvs->master.dyn_addr = master->this->info.dyn_addr;
> > +	defslvs->master.static_addr = I3C_BROADCAST_ADDR;  
> 
>  Why defslvs->master.static_addr = I3C_BROADCAST_ADDR?

I just follow what's document in "5.1.9.3.7 Define List of Slaves
(DEFSLVS)"

> 
>  > +
> > +	desc = defslvs->slaves;
> > +	i3c_bus_for_each_i2cdev(bus, i2cdev) {
> > +		desc->lvr = i2cdev->lvr;
> > +		desc->static_addr = i2cdev->info.addr;
> > +		desc++;
> > +	}
> > +
> > +	i3c_bus_for_each_i3cdev(bus, i3cdev) {
> > +		/* Skip the I3C dev representing this master. */
> > +		if (i3cdev == master->this)
> > +			continue;
> > +
> > +		desc->bcr = i3cdev->info.bcr;
> > +		desc->dcr = i3cdev->info.dcr;
> > +		desc->dyn_addr = i3cdev->info.dyn_addr;
> > +		desc->static_addr = i3cdev->info.static_addr;
> > +		desc++;
> > +	}
> > +
> > +	ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
> > +	kfree(defslvs);
> > +
> > +	return ret;
> > +}
> > +EXPORT_SYMBOL_GPL(i3c_master_defslvs_locked);
> > +
> > +
> > +static int i3c_master_i2c_adapter_xfer(struct i2c_adapter *adap,
> > +				       struct i2c_msg *xfers, int nxfers)
> > +{
> > +	struct i3c_master_controller *master = i2c_adapter_to_i3c_master(adap);
> > +	int i, ret;
> > +
> > +	for (i = 0; i < nxfers; i++) {
> > +		enum i3c_addr_slot_status status;
> > +
> > +		status = i3c_bus_get_addr_slot_status(master->bus,
> > +						      xfers[i].addr);
> > +		if (status != I3C_ADDR_SLOT_I2C_DEV)
> > +			return -EINVAL;
> > +	}
> > +
> > +	ret = i3c_master_do_i2c_xfers(master, xfers, nxfers);
> > +	if (ret)
> > +		return ret;
> > +
> > +	return nxfers;
> > +}
> > +
> > +static u32 i3c_master_i2c_functionalities(struct i2c_adapter *adap)
> > +{
> > +	return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR;
> > +}  
> 
>  Is I2C_FUNC_10BIT_ADDR allowed ?

According to "Table 4 I 2 C Features Allowed in I3C Slaves", yes (at
least that my understanding). And the Cadence controller supports it.

> 
>  > diff --git a/drivers/i3c/master/Kconfig b/drivers/i3c/master/Kconfig
> > new file mode 100644
> > index 000000000000..e69de29bb2d1
> > diff --git a/drivers/i3c/master/Makefile b/drivers/i3c/master/Makefile
> > new file mode 100644
> > index 000000000000..e69de29bb2d1
> > diff --git a/include/linux/i3c/ccc.h b/include/linux/i3c/ccc.h
> > new file mode 100644
> > index 000000000000..ff3e1a3e2c4c
> > --- /dev/null
> > +++ b/include/linux/i3c/ccc.h
> > @@ -0,0 +1,380 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (C) 2017 Cadence Design Systems Inc.
> > + *
> > + * Author: Boris Brezillon<boris.brezillon@free-electrons.com>
> > + */
> > +
> > +
> > +/**
> > + * enum i3c_ccc_test_mode - enum listing all available test modes
> > + *
> > + * @I3C_CCC_EXIT_TEST_MODE: exit test mode
> > + * @I3C_CCC_VENDOR_TEST_MODE: enter vendor test mode
> > + */
> > +enum i3c_ccc_test_mode {
> > +	I3C_CCC_EXIT_TEST_MODE,
> > +	I3C_CCC_VENDOR_TEST_MODE,
> > +};
> > +
> > +/**
> > + * struct i3c_ccc_enttm - payload passed to ENTTM CCC
> > + *
> > + * @mode: one of the &enum i3c_ccc_test_mode modes
> > + *
> > + * Information passed to the ENTTM CCC to instruct an I3C device to enter a
> > + * specific test mode.
> > + */
> > +struct i3c_ccc_enttm {
> > +	u8 mode;
> > +} __packed;
> > +
> > +/**
> > + * struct i3c_ccc_setda - payload passed to ENTTM CCC
> > + *
> > + * @mode: one of the &enum i3c_ccc_test_mode modes
> > + *
> > + * Information passed to the ENTTM CCC to instruct an I3C device to enter a
> > + * specific test mode.
> > + */
> > +struct i3c_ccc_setda {
> > +	u8 addr;
> > +} __packed;  
> 
>  what do you mean with struct? Maybe setdasa? if so, what is the addr?
> 
>  > +/**
> > + * enum i3c_sdr_max_data_rate - max data rate values for private SDR transfers
> > + */
> > +enum i3c_sdr_max_data_rate {
> > +	I3C_SDR_DR_FSCL_MAX,
> > +	I3C_SDR_DR_FSCL_8MHZ,
> > +	I3C_SDR_DR_FSCL_6MHZ,
> > +	I3C_SDR_DR_FSCL_4MHZ,
> > +	I3C_SDR_DR_FSCL_2MHZ,
> > +};  
> Can you change the names to:
> 
> I3C_SDR0_FSCL_MAX,
> I3C_SDR1_FSCL_8MHZ,
> I3C_SDR2_FSCL_6MHZ,
> I3C_SDR3_FSCL_4MHZ,
> I3C_SDR4_FSCL_2MHZ,
> 
> thus the data rate isn't repeated.

What's the problem with the name I use? Moreover, I see no mention to
the SDR0,1,2,3,4 modes in the public spec.

> 
> > +
> > +/**
> > + * enum i3c_tsco - clock to data turn-around
> > + */
> > +enum i3c_tsco {
> > +	I3C_TSCO_LT_8NS,
> > +	I3C_TSCO_LT_9NS,
> > +	I3C_TSCO_LT_10NS,
> > +	I3C_TSCO_LT_11NS,
> > +	I3C_TSCO_LT_12NS,
> > +};  
> what's the meaning of _LT_ ?

This I don't remember. I'll drop it in the next version.

> > +
> > +#endif /* I3C_CCC_H */
> > diff --git a/include/linux/i3c/device.h b/include/linux/i3c/device.h
> > new file mode 100644
> > index 000000000000..83958d3a02e2
> > --- /dev/null
> > +++ b/include/linux/i3c/device.h
> > @@ -0,0 +1,321 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (C) 2017 Cadence Design Systems Inc.
> > + *
> > + * Author: Boris Brezillon<boris.brezillon@free-electrons.com>
> > + */
> > +
> > +#ifndef I3C_DEV_H
> > +#define I3C_DEV_H
> > +
> > +#include <linux/device.h>
> > +#include <linux/i2c.h>
> > +#include <linux/mod_devicetable.h>
> > +#include <linux/module.h>
> > +
> > +/**
> > + * enum i3c_hdr_mode - HDR mode ids
> > + * @I3C_HDR_DDR: DDR mode
> > + * @I3C_HDR_TSP: TSP mode
> > + * @I3C_HDR_TSL: TSL mode
> > + */
> > +enum i3c_hdr_mode {
> > +	I3C_HDR_DDR,
> > +	I3C_HDR_TSP,
> > +	I3C_HDR_TSL,
> > +};
> > +
> > +/**
> > + * struct i3c_hdr_cmd - I3C HDR command
> > + * @mode: HDR mode selected for this command
> > + * @code: command opcode
> > + * @addr: I3C dynamic address
> > + * @ndatawords: number of data words (a word is 16bits wide)
> > + * @data: input/output buffer
> > + */
> > +struct i3c_hdr_cmd {
> > +	enum i3c_hdr_mode mode;
> > +	u8 code;
> > +	u8 addr;
> > +	int ndatawords;
> > +	union {
> > +		u16 *in;
> > +		const u16 *out;
> > +	} data;
> > +};
> > +
> > +/* Private SDR read transfer */
> > +#define I3C_PRIV_XFER_READ		BIT(0)
> > +/*
> > + * Instruct the controller to issue a STOP after a specific transfer instead
> > + * of a REPEATED START.
> > + */
> > +#define I3C_PRIV_XFER_STOP		BIT(1)
> > +
> > +/**
> > + * struct i3c_priv_xfer - I3C SDR private transfer
> > + * @addr: I3C dynamic address
> > + * @len: transfer length in bytes of the transfer
> > + * @flags: combination of I3C_PRIV_XFER_xxx flags
> > + * @data: input/output buffer
> > + */
> > +struct i3c_priv_xfer {
> > +	u8 addr;
> > +	u16 len;
> > +	u32 flags;
> > +	struct {
> > +		void *in;
> > +		const void *out;
> > +	} data;
> > +};  
> 
>  Same as above, i3c_sdr_max_data_rate to change the bus scl.

If I'm understanding the spec correctly, that's not something you want
to change on a per-transfer basis. The constraint is on the device
itself and should IMO not be part of the i3c_priv_xfer struct.

> 
>  > +
> > +/**
> > + * enum i3c_dcr - I3C DCR values
> > + * @I3C_DCR_GENERIC_DEVICE: generic I3C device
> > + */
> > +enum i3c_dcr {
> > +	I3C_DCR_GENERIC_DEVICE = 0,
> > +};
> > +
> > +#define I3C_PID_MANUF_ID(pid)		(((pid) & GENMASK_ULL(47, 33)) >> 33)
> > +#define I3C_PID_RND_LOWER_32BITS(pid)	(!!((pid) & BIT_ULL(32)))
> > +#define I3C_PID_RND_VAL(pid)		((pid) & GENMASK_ULL(31, 0))
> > +#define I3C_PID_PART_ID(pid)		(((pid) & GENMASK_ULL(31, 16)) >> 16)
> > +#define I3C_PID_INSTANCE_ID(pid)	(((pid) & GENMASK_ULL(15, 12)) >> 12)
> > +#define I3C_PID_EXTRA_INFO(pid)		((pid) & GENMASK_ULL(11, 0))
> > +
> > +#define I3C_BCR_DEVICE_ROLE(bcr)	((bcr) & GENMASK(7, 6))
> > +#define I3C_BCR_I3C_SLAVE		(0 << 6)
> > +#define I3C_BCR_I3C_MASTER		(1 << 6)
> > +#define I3C_BCR_HDR_CAP			BIT(5)
> > +#define I3C_BCR_BRIDGE			BIT(4)
> > +#define I3C_BCR_OFFLINE_CAP		BIT(3)
> > +#define I3C_BCR_IBI_PAYLOAD		BIT(2)
> > +#define I3C_BCR_IBI_REQ_CAP		BIT(1)
> > +#define I3C_BCR_MAX_DATA_SPEED_LIM	BIT(0)
> > +
> > +/**
> > + * struct i3c_device_info - I3C device information
> > + * @pid: Provisional ID
> > + * @bcr: Bus Characteristic Register
> > + * @dcr: Device Characteristic Register
> > + * @static_addr: static/I2C address
> > + * @dyn_addr: dynamic address
> > + * @hdr_cap: supported HDR modes
> > + * @max_read_ds: max read speed information
> > + * @max_write_ds: max write speed information
> > + * @max_ibi_len: max IBI payload length
> > + * @max_read_turnaround: max read turn-around time in micro-seconds
> > + * @max_read_len: max private SDR read length in bytes
> > + * @max_write_len: max private SDR write length in bytes
> > + *
> > + * These are all basic information that should be advertised by an I3C device.
> > + * Some of them are optional depending on the device type and device
> > + * capabilities.
> > + * For each I3C slave attached to a master with
> > + * i3c_master_add_i3c_dev_locked(), the core will send the relevant CCC command
> > + * to retrieve these data.
> > + */
> > +struct i3c_device_info {
> > +	u64 pid;
> > +	u8 bcr;
> > +	u8 dcr;
> > +	u8 static_addr;
> > +	u8 dyn_addr;
> > +	u8 hdr_cap;
> > +	u8 max_read_ds;
> > +	u8 max_write_ds;
> > +	u8 max_ibi_len;
> > +	u32 max_read_turnaround;
> > +	u16 max_read_len;
> > +	u16 max_write_len;
> > +};
> > +  
> 
>  is this information filled with data provided from CCC commands?

Yes, they are.

> 
>  > +
> > +#endif /* I3C_DEV_H */
> > diff --git a/include/linux/i3c/master.h b/include/linux/i3c/master.h
> > new file mode 100644
> > index 000000000000..7ec9a4821bac
> > --- /dev/null
> > +++ b/include/linux/i3c/master.h
> > @@ -0,0 +1,564 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (C) 2017 Cadence Design Systems Inc.
> > + *
> > + * Author: Boris Brezillon<boris.brezillon@free-electrons.com>
> > + */
> > +
> > +#ifndef I3C_MASTER_H
> > +#define I3C_MASTER_H
> > +
> > +#include <linux/i2c.h>
> > +#include <linux/i3c/ccc.h>
> > +#include <linux/i3c/device.h>
> > +#include <linux/spinlock.h>
> > +
> > +#define I3C_HOT_JOIN_ADDR		0x2
> > +#define I3C_BROADCAST_ADDR		0x7e
> > +#define I3C_MAX_ADDR			GENMASK(6, 0)
> > +
> > +struct i3c_master_controller;
> > +struct i3c_bus;
> > +
> > +/**
> > + * struct i3c_i2c_dev - I3C/I2C common information
> > + * @node: node element used to insert the device into the I2C or I3C device
> > + *	  list
> > + * @bus: I3C bus this device is connected to
> > + * @master: I3C master that instantiated this device. Will be used to send
> > + *	    I2C/I3C frames on the bus
> > + * @master_priv: master private data assigned to the device. Can be used to
> > + *		 add master specific information
> > + *
> > + * This structure is describing common I3C/I2C dev information.
> > + */
> > +struct i3c_i2c_dev {
> > +	struct list_head node;
> > +	struct i3c_bus *bus;
> > +	struct i3c_master_controller *master;
> > +	void *master_priv;
> > +};
> > +
> > +#define I3C_LVR_I2C_INDEX_MASK		GENMASK(7, 5)
> > +#define I3C_LVR_I2C_INDEX(x)		((x) << 5)
> > +#define I3C_LVR_I2C_FM_MODE		BIT(4)
> > +
> > +#define I2C_MAX_ADDR			GENMASK(9, 0)  
> 
>  why 10-bit address?
> 

Because some I2C devices have 10-bit addresses.

>  > +
> > +/**
> > + * struct i2c_device - I2C device object
> > + * @common: inherit common I3C/I2C description
> > + * @info: I2C board info used to instantiate the I2C device. If you are
> > + *	  using DT to describe your hardware, this will be filled for you
> > + * @client: I2C client object created by the I2C framework. This will only
> > + *	    be valid after i3c_master_register() returns
> > + * @lvr: Legacy Virtual Register value as described in the I3C specification
> > + *
> > + * I2C device object. Note that the real I2C device is represented by
> > + * i2c_device->client, but we need extra information to handle the device when
> > + * it's connected to an I3C bus, hence the &struct i2c_device wrapper.
> > + *
> > + * The I2C framework is not impacted by this new representation.
> > + */
> > +struct i2c_device {
> > +	struct i3c_i2c_dev common;
> > +	struct i2c_board_info info;
> > +	struct i2c_client *client;
> > +	u8 lvr;
> > +};
> > +  
> 
>  It is usefull to know the speed limitations of the device.

See my previous explanation about I2C and the max frequency. BTW, the
FM vs FM+ information is already encoded in the ->lvr field.

> 
>  > +
> > +/**
> > + * enum i3c_addr_slot_status - I3C address slot status
> > + * @I3C_ADDR_SLOT_FREE: address is free
> > + * @I3C_ADDR_SLOT_RSVD: address is reserved
> > + * @I3C_ADDR_SLOT_I2C_DEV: address is assigned to an I2C device
> > + * @I3C_ADDR_SLOT_I3C_DEV: address is assigned to an I3C device
> > + * @I3C_ADDR_SLOT_STATUS_MASK: address slot mask
> > + *
> > + * On an I3C bus, addresses are assigned dynamically, and we need to know which
> > + * addresses are free to use and which ones are already assigned.
> > + *
> > + * Addresses marked as reserved are those reserved by the I3C protocol
> > + * (broadcast address, ...).
> > + */
> > +enum i3c_addr_slot_status {
> > +	I3C_ADDR_SLOT_FREE,
> > +	I3C_ADDR_SLOT_RSVD,
> > +	I3C_ADDR_SLOT_I2C_DEV,
> > +	I3C_ADDR_SLOT_I3C_DEV,
> > +	I3C_ADDR_SLOT_STATUS_MASK = 3,
> > +};
> > +
> > +/**
> > + * struct i3c_bus - I3C bus object
> > + * @dev: device to be registered to the device-model
> > + * @cur_master: I3C master currently driving the bus. Since I3C is multi-master
> > + *		this can change over the time. Will be used to let a master
> > + *		know whether it needs to request bus ownership before sending
> > + *		a frame or not
> > + * @id: bus ID. Assigned by the framework when register the bus
> > + * @addrslots: a bitmap with 2-bits per-slot to encode the address status and
> > + *	       ease the DAA (Dynamic Address Assignment) procedure (see
> > + *	       &enum i3c_addr_slot_status)
> > + * @mode: bus mode (see &enum i3c_bus_mode)
> > + * @scl_rate: SCL signal rate for I3C and I2C mode
> > + * @devs: 2 lists containing all I3C/I2C devices connected to the bus
> > + * @lock: read/write lock on the bus. This is needed to protect against
> > + *	  operations that have an impact on the whole bus and the devices
> > + *	  connected to it. For example, when asking slaves to drop their
> > + *	  dynamic address (RSTDAA CCC), we need to make sure no one is trying
> > + *	  to send I3C frames to these devices.
> > + *	  Note that this lock does not protect against concurrency between
> > + *	  devices: several drivers can send different I3C/I2C frames through
> > + *	  the same master in parallel. This is the responsibility of the
> > + *	  master to guarantee that frames are actually sent sequentially and
> > + *	  not interlaced
> > + *
> > + * The I3C bus is represented with its own object and not implicitly described
> > + * by the I3C master to cope with the multi-master functionality, where one bus
> > + * can be shared amongst several masters, each of them requesting bus ownership
> > + * when they need to.
> > + */
> > +struct i3c_bus {
> > +	struct device dev;
> > +	struct i3c_device *cur_master;
> > +	int id;
> > +	unsigned long addrslots[((I2C_MAX_ADDR + 1) * 2) / BITS_PER_LONG];
> > +	enum i3c_bus_mode mode;
> > +	struct {
> > +		unsigned long i3c;
> > +		unsigned long i2c;
> > +	} scl_rate;
> > +	struct {
> > +		struct list_head i3c;
> > +		struct list_head i2c;
> > +	} devs;
> > +	struct rw_semaphore lock;
> > +};  
> Can you explain the addrslots[] ?

It's a bitmap encoding the status of I3C/I2C addresses: are they
assigned, reserved of free, and if they are assigned is it an I3C or
I2C device. That's particularly useful to master controller drivers
to know which addresses they can assign during DAA.

I'll try to clarify it in the kernel-doc header.  

> > +
> > +static inline struct i3c_device *dev_to_i3cdev(struct device *dev)
> > +{
> > +	return container_of(dev, struct i3c_device, dev);
> > +}
> > +
> > +struct i3c_master_controller;
> > +
> > +/**
> > + * struct i3c_master_controller_ops - I3C master methods
> > + * @bus_init: hook responsible for the I3C bus initialization. This
> > + *	      initialization should follow the steps described in the I3C
> > + *	      specification. This hook is called with the bus lock held in
> > + *	      write mode, which means all _locked() helpers can safely be
> > + *	      called from there
> > + * @bus_cleanup: cleanup everything done in
> > + *		 &i3c_master_controller_ops->bus_init(). This function is
> > + *		 optional and should only be implemented if
> > + *		 &i3c_master_controller_ops->bus_init() attached private data
> > + *		 to I3C/I2C devices. This hook is called with the bus lock
> > + *		 held in write mode, which means all _locked() helpers can
> > + *		 safely be called from there
> > + * @supports_ccc_cmd: should return true if the CCC command is supported, false
> > + *		      otherwise
> > + * @send_ccc_cmd: send a CCC command
> > + * @send_hdr_cmds: send one or several HDR commands. If there is more than one
> > + *		   command, they should ideally be sent in the same HDR
> > + *		   transaction
> > + * @priv_xfers: do one or several private I3C SDR transfers
> > + * @i2c_xfers: do one or several I2C transfers
> > + * @request_ibi: attach an IBI handler to an I3C device. This implies defining
> > + *		 an IBI handler and the constraints of the IBI (maximum payload
> > + *		 length and number of pre-allocated slots).
> > + *		 Some controllers support less IBI-capable devices than regular
> > + *		 devices, so this method might return -%EBUSY if there's no
> > + *		 more space for an extra IBI registration
> > + * @free_ibi: free an IBI previously requested with ->request_ibi(). The IBI
> > + *	      should have been disabled with ->disable_irq() prior to that
> > + * @enable_ibi: enable the IBI. Only valid if ->request_ibi() has been called
> > + *		prior to ->enable_ibi(). The controller should first enable
> > + *		the IBI on the controller end (for example, unmask the hardware
> > + *		IRQ) and then send the ENEC CCC command (with the IBI flag set)
> > + *		to the I3C device
> > + * @disable_ibi: disable an IBI. First send the DISEC CCC command with the IBI
> > + *		 flag set and then deactivate the hardware IRQ on the
> > + *		 controller end
> > + * @recycle_ibi_slot: recycle an IBI slot. Called every time an IBI has been
> > + *		      processed by its handler. The IBI slot should be put back
> > + *		      in the IBI slot pool so that the controller can re-use it
> > + *		      for a future IBI
> > + *
> > + * One of the most important hooks in these ops is
> > + * &i3c_master_controller_ops->bus_init(). Here is a non-exhaustive list of
> > + * things that should be done in &i3c_master_controller_ops->bus_init():
> > + *
> > + * 1) call i3c_master_set_info() with all information describing the master
> > + * 2) ask all slaves to drop their dynamic address by sending the RSTDAA CCC
> > + *    with i3c_master_rstdaa_locked()
> > + * 3) ask all slaves to disable IBIs using i3c_master_disec_locked()
> > + * 4) start a DDA procedure by sending the ENTDAA CCC with
> > + *    i3c_master_entdaa_locked(), or using the internal DAA logic provided by
> > + *    your controller  
> You mean SETDASA CCC command?

No, I really mean ENTDAA and DAA. By internal DAA logic I mean that
some controllers are probably automating the whole DAA procedure, while
others may let the SW control every step.

Thanks for your review.

Boris
Boris Brezillon Feb. 23, 2018, 10:45 p.m. UTC | #14 
On Fri, 23 Feb 2018 16:56:14 +0000
Vitor Soares <Vitor.Soares@synopsys.com> wrote:


> > +
> > +/**
> > + * struct i3c_ccc_setda - payload passed to ENTTM CCC
> > + *
> > + * @mode: one of the &enum i3c_ccc_test_mode modes
> > + *
> > + * Information passed to the ENTTM CCC to instruct an I3C device to enter a
> > + * specific test mode.

Oops, copy&paste error. I'll fix the kernel-doc header.

> > + */
> > +struct i3c_ccc_setda {
> > +	u8 addr;
> > +} __packed;  
> 
>  what do you mean with struct? Maybe setdasa? if so, what is the addr?

It's the payload passed to SETDASA and SETNEWDA, hence the generic
_setda suffix. addr is the new dynamic address assigned to the
device.
Vitor Soares Feb. 26, 2018, 6:58 p.m. UTC | #15 
Hi Boris


Às 8:30 PM de 2/23/2018, Boris Brezillon escreveu:
> Hi Vitor,
>
> On Fri, 23 Feb 2018 16:56:14 +0000
> Vitor Soares <Vitor.Soares@synopsys.com> wrote:
>
>> Hi Boris,
>>
>> Às 3:16 PM de 12/14/2017, Boris Brezillon escreveu:
>>> +
>>> +enum i3c_addr_slot_status i3c_bus_get_addr_slot_status(struct i3c_bus *bus,
>>> +						       u16 addr)
>>> +{
>>> +	int status, bitpos = addr * 2;
>>> +
>>> +	if (addr > I2C_MAX_ADDR)
>>> +		return I3C_ADDR_SLOT_RSVD;
>>> +
>>> +	status = bus->addrslots[bitpos / BITS_PER_LONG];
>>> +	status >>= bitpos % BITS_PER_LONG;
>>> +
>>> +	return status & I3C_ADDR_SLOT_STATUS_MASK;
>>> +}  
>> I don't understand the size of addr. The I3C only allow 7-bit addresses.
>>
>> Is the addrslots used to store the addresses and its status?
> No, slots are used for both I2C and I3C addresses, and an I2C address
> can be 10-bits wide, hence the u16 type.
>
>
> [...]
>
>>> +/**
>>> + * i3c_device_do_priv_xfers() - do I3C SDR private transfers directed to a
>>> + *				specific device
>>> + *
>>> + * @dev: device with which the transfers should be done
>>> + * @xfers: array of transfers
>>> + * @nxfers: number of transfers
>>> + *
>>> + * Initiate one or several private SDR transfers with @dev.
>>> + *
>>> + * This function can sleep and thus cannot be called in atomic context.
>>> + *
>>> + * Return: 0 in case of success, a negative error core otherwise.
>>> + */
>>> +int i3c_device_do_priv_xfers(struct i3c_device *dev,
>>> +			     struct i3c_priv_xfer *xfers,
>>> +			     int nxfers)
>>> +{
>>> +	struct i3c_master_controller *master;
>>> +	int i, ret;
>>> +
>>> +	master = i3c_device_get_master(dev);
>>> +	if (!master)
>>> +		return -EINVAL;
>>> +
>>> +	i3c_bus_normaluse_lock(master->bus);
>>> +	for (i = 0; i < nxfers; i++)
>>> +		xfers[i].addr = dev->info.dyn_addr;
>>> +
>>> +	ret = i3c_master_do_priv_xfers_locked(master, xfers, nxfers);
>>> +	i3c_bus_normaluse_unlock(master->bus);
>>> +
>>> +	return ret;
>>> +}
>>> +EXPORT_SYMBOL_GPL(i3c_device_do_priv_xfers);  
>>  The controller should know the speed mode for each xfer. The SDR0 mode 
>> is used by default but if any device have read or write speed 
>> limitations the controller can use SDRx.
> I might be wrong, but that's not my understanding of the spec. A device
> can express a speed limitation for SDR priv transfers, but this
> limitation applies to all SDR transfers.
>
> The speed R/W speed limitation is encoded in the device object, so, if
> the controller has to configure that on a per-transfer basis, one
> solution would be to pass the device to the ->priv_xfers().
The speed R/W limitation is only for private transfers. Also the device can have
a limitation to write and not for read data.
This information is obtained with the command GETMXDS which returns the Maximum
Sustained Data Rate for non-CCC messages.
>
>> This could be also applied to i2c transfers.
> Not really. The max SCL frequency is something that applies to the
> whole bus, because all I2C devices have to decode the address when
> messages are sent on the bus to determine if they should ignore or
> process the message.
>
>>> +#endif /* I3C_INTERNAL_H */
>>> diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c
>>> new file mode 100644
>>> index 000000000000..1c85abac08d5
>>> --- /dev/null
>>> +++ b/drivers/i3c/master.c
>>> @@ -0,0 +1,1433 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +/*
>>> + * Copyright (C) 2017 Cadence Design Systems Inc.
>>> + *
>>> + * Author: Boris Brezillon<boris.brezillon@free-electrons.com>
>>> + */
>>> +
>>> +#include <linux/slab.h>
>>> +
>>> +#include "internals.h"
>>> +
>>> +/**
>>> + * i3c_master_entdaa_locked() - start a DAA (Dynamic Address Assignment)
>>> + *				procedure
>>> + * @master: master used to send frames on the bus
>>> + *
>>> + * Send a ENTDAA CCC command to start a DAA procedure.
>>> + *
>>> + * Note that this function only sends the ENTDAA CCC command, all the logic
>>> + * behind dynamic address assignment has to be handled in the I3C master
>>> + * driver.
>>> + *
>>> + * This function must be called with the bus lock held in write mode.
>>> + *
>>> + * Return: 0 in case of success, a negative error code otherwise.
>>> + */
>>> +int i3c_master_entdaa_locked(struct i3c_master_controller *master)
>>> +{
>>> +	struct i3c_ccc_cmd_dest dest = { };
>>> +	struct i3c_ccc_cmd cmd = { };
>>> +	int ret;
>>> +
>>> +	dest.addr = I3C_BROADCAST_ADDR;
>>> +	cmd.dests = &dest;
>>> +	cmd.ndests = 1;
>>> +	cmd.rnw = false;
>>> +	cmd.id = I3C_CCC_ENTDAA;
>>> +
>>> +	ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
>>> +	if (ret)
>>> +		return ret;
>>> +
>>> +	return 0;
>>> +}
>>> +EXPORT_SYMBOL_GPL(i3c_master_entdaa_locked);  
>>  can you explain the process?
> Not sure what you mean. The ENTDAA is just a CCC command that is used
> to trigger a DAA procedure. What the master controller does when it
> sends such a command is likely to be controller dependent, and it might
> even be possible that you don't need to call this function in your
> controller driver to trigger a DAA. If you want more details about the
> bus initialization steps and how the ENTDAA CCC command fits into it I
> recommend reading section "5.1.4 Bus Initialization and Dynamic Address
> Assignment Mode"
>
>> the command is only execute once, what if 
>> there is more devices on the bus?
> Again, I'm not sure what you mean. The ENTDAA command is sent every
> time a controller wants to discover new devices on the bus, that can be
> when initializing the bus, after a Hot Join event or simply triggered
> by the user (the last case is not supported yet though).
>
> Now, if you're interested in what happens after an ENTDAA CCC is sent,
> the controller will keep sending RepeatedStart until there's no more
> devices acking the request. You can have a look at "B.3 Error Types in
> Dynamic Address Arbitration" for more details.
My understanding is this command shall be executed once, this mean that only one
slave will assign the dynamic address (cmd.ndests = 1) and not trigger the whole
process of DAA.
Either important is the SETDASA for declared I3C devices. So the DAA process
should start by send an SETDASA and them ENTDAA CCC command.
>>  > +
>>> +/**
>>> + * i3c_master_defslvs_locked() - send a DEFSLVS CCC command
>>> + * @master: master used to send frames on the bus
>>> + *
>>> + * Send a DEFSLVS CCC command containing all the devices known to the @master.
>>> + * This is useful when you have secondary masters on the bus to propagate
>>> + * device information.
>>> + *
>>> + * This should be called after all I3C devices have been discovered (in other
>>> + * words, after the DAA procedure has finished) and instantiated in
>>> + * i3c_master_controller_ops->bus_init().
>>> + * It should also be called if a master ACKed an Hot-Join request and assigned
>>> + * a dynamic address to the device joining the bus.
>>> + *
>>> + * This function must be called with the bus lock held in write mode.
>>> + *
>>> + * Return: 0 in case of success, a negative error code otherwise.
>>> + */
>>> +int i3c_master_defslvs_locked(struct i3c_master_controller *master)
>>> +{
>>> +	struct i3c_ccc_cmd_dest dest = {
>>> +		.addr = I3C_BROADCAST_ADDR,
>>> +	};
>>> +	struct i3c_ccc_cmd cmd = {
>>> +		.id = I3C_CCC_DEFSLVS,
>>> +		.dests = &dest,
>>> +		.ndests = 1,
>>> +	};
>>> +	struct i3c_ccc_defslvs *defslvs;
>>> +	struct i3c_ccc_dev_desc *desc;
>>> +	struct i3c_device *i3cdev;
>>> +	struct i2c_device *i2cdev;
>>> +	struct i3c_bus *bus;
>>> +	bool send = false;
>>> +	int ndevs = 0, ret;
>>> +
>>> +	if (!master)
>>> +		return -EINVAL;
>>> +
>>> +	bus = i3c_master_get_bus(master);
>>> +	i3c_bus_for_each_i3cdev(bus, i3cdev) {
>>> +		ndevs++;
>>> +		if (I3C_BCR_DEVICE_ROLE(i3cdev->info.bcr) == I3C_BCR_I3C_MASTER)
>>> +			send = true;
>>> +	}
>>> +
>>> +	/* No other master on the bus, skip DEFSLVS. */
>>> +	if (!send)
>>> +		return 0;
>>> +
>>> +	i3c_bus_for_each_i2cdev(bus, i2cdev)
>>> +		ndevs++;
>>> +
>>> +	dest.payload.len = sizeof(*defslvs) +
>>> +			   ((ndevs - 1) * sizeof(struct i3c_ccc_dev_desc));
>>> +	defslvs = kzalloc(dest.payload.len, GFP_KERNEL);
>>> +	if (!defslvs)
>>> +		return -ENOMEM;
>>> +
>>> +	dest.payload.data = defslvs;
>>> +
>>> +	defslvs->count = ndevs;
>>> +	defslvs->master.bcr = master->this->info.bcr;
>>> +	defslvs->master.dcr = master->this->info.dcr;
>>> +	defslvs->master.dyn_addr = master->this->info.dyn_addr;
>>> +	defslvs->master.static_addr = I3C_BROADCAST_ADDR;  
>>  Why defslvs->master.static_addr = I3C_BROADCAST_ADDR?
> I just follow what's document in "5.1.9.3.7 Define List of Slaves
> (DEFSLVS)"
yes, that's right.
>>  > +
>>> +	desc = defslvs->slaves;
>>> +	i3c_bus_for_each_i2cdev(bus, i2cdev) {
>>> +		desc->lvr = i2cdev->lvr;
>>> +		desc->static_addr = i2cdev->info.addr;
>>> +		desc++;
>>> +	}
>>> +
>>> +	i3c_bus_for_each_i3cdev(bus, i3cdev) {
>>> +		/* Skip the I3C dev representing this master. */
>>> +		if (i3cdev == master->this)
>>> +			continue;
>>> +
>>> +		desc->bcr = i3cdev->info.bcr;
>>> +		desc->dcr = i3cdev->info.dcr;
>>> +		desc->dyn_addr = i3cdev->info.dyn_addr;
>>> +		desc->static_addr = i3cdev->info.static_addr;
>>> +		desc++;
>>> +	}
>>> +
>>> +	ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
>>> +	kfree(defslvs);
>>> +
>>> +	return ret;
>>> +}
>>> +EXPORT_SYMBOL_GPL(i3c_master_defslvs_locked);
>>> +
>>> +
>>> +static int i3c_master_i2c_adapter_xfer(struct i2c_adapter *adap,
>>> +				       struct i2c_msg *xfers, int nxfers)
>>> +{
>>> +	struct i3c_master_controller *master = i2c_adapter_to_i3c_master(adap);
>>> +	int i, ret;
>>> +
>>> +	for (i = 0; i < nxfers; i++) {
>>> +		enum i3c_addr_slot_status status;
>>> +
>>> +		status = i3c_bus_get_addr_slot_status(master->bus,
>>> +						      xfers[i].addr);
>>> +		if (status != I3C_ADDR_SLOT_I2C_DEV)
>>> +			return -EINVAL;
>>> +	}
>>> +
>>> +	ret = i3c_master_do_i2c_xfers(master, xfers, nxfers);
>>> +	if (ret)
>>> +		return ret;
>>> +
>>> +	return nxfers;
>>> +}
>>> +
>>> +static u32 i3c_master_i2c_functionalities(struct i2c_adapter *adap)
>>> +{
>>> +	return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR;
>>> +}  
>>  Is I2C_FUNC_10BIT_ADDR allowed ?
> According to "Table 4 I 2 C Features Allowed in I3C Slaves", yes (at
> least that my understanding). And the Cadence controller supports it.
The table say the oposite. The I2C extended address feature is not used on I3C
bus, thus this feature shall be disable.
BTW it is optional on I2C devices.

>
>>  > diff --git a/drivers/i3c/master/Kconfig b/drivers/i3c/master/Kconfig
>>> new file mode 100644
>>> index 000000000000..e69de29bb2d1
>>> diff --git a/drivers/i3c/master/Makefile b/drivers/i3c/master/Makefile
>>> new file mode 100644
>>> index 000000000000..e69de29bb2d1
>>> diff --git a/include/linux/i3c/ccc.h b/include/linux/i3c/ccc.h
>>> new file mode 100644
>>> index 000000000000..ff3e1a3e2c4c
>>> --- /dev/null
>>> +++ b/include/linux/i3c/ccc.h
>>> @@ -0,0 +1,380 @@
>>> +/* SPDX-License-Identifier: GPL-2.0 */
>>> +/*
>>> + * Copyright (C) 2017 Cadence Design Systems Inc.
>>> + *
>>> + * Author: Boris Brezillon<boris.brezillon@free-electrons.com>
>>> + */
>>> +
>>> +
>>> +/**
>>> + * enum i3c_ccc_test_mode - enum listing all available test modes
>>> + *
>>> + * @I3C_CCC_EXIT_TEST_MODE: exit test mode
>>> + * @I3C_CCC_VENDOR_TEST_MODE: enter vendor test mode
>>> + */
>>> +enum i3c_ccc_test_mode {
>>> +	I3C_CCC_EXIT_TEST_MODE,
>>> +	I3C_CCC_VENDOR_TEST_MODE,
>>> +};
>>> +
>>> +/**
>>> + * struct i3c_ccc_enttm - payload passed to ENTTM CCC
>>> + *
>>> + * @mode: one of the &enum i3c_ccc_test_mode modes
>>> + *
>>> + * Information passed to the ENTTM CCC to instruct an I3C device to enter a
>>> + * specific test mode.
>>> + */
>>> +struct i3c_ccc_enttm {
>>> +	u8 mode;
>>> +} __packed;
>>> +
>>> +/**
>>> + * struct i3c_ccc_setda - payload passed to ENTTM CCC
>>> + *
>>> + * @mode: one of the &enum i3c_ccc_test_mode modes
>>> + *
>>> + * Information passed to the ENTTM CCC to instruct an I3C device to enter a
>>> + * specific test mode.
>>> + */
>>> +struct i3c_ccc_setda {
>>> +	u8 addr;
>>> +} __packed;  
>>  what do you mean with struct? Maybe setdasa? if so, what is the addr?
Do you have the function to use this structure? Because one command use the
static address and the other use the dynamic address.

>>
>>  > +/**
>>> + * enum i3c_sdr_max_data_rate - max data rate values for private SDR transfers
>>> + */
>>> +enum i3c_sdr_max_data_rate {
>>> +	I3C_SDR_DR_FSCL_MAX,
>>> +	I3C_SDR_DR_FSCL_8MHZ,
>>> +	I3C_SDR_DR_FSCL_6MHZ,
>>> +	I3C_SDR_DR_FSCL_4MHZ,
>>> +	I3C_SDR_DR_FSCL_2MHZ,
>>> +};  
>> Can you change the names to:
>>
>> I3C_SDR0_FSCL_MAX,
>> I3C_SDR1_FSCL_8MHZ,
>> I3C_SDR2_FSCL_6MHZ,
>> I3C_SDR3_FSCL_4MHZ,
>> I3C_SDR4_FSCL_2MHZ,
>>
>> thus the data rate isn't repeated.
> What's the problem with the name I use? Moreover, I see no mention to
> the SDR0,1,2,3,4 modes in the public spec.
When you get the GETMXDS information, the maxWr and maxRd came from 0 to 4, so
in my opinion I think in this way is easier to have a relationship.
>
>>> +
>>> +/**
>>> + * enum i3c_tsco - clock to data turn-around
>>> + */
>>> +enum i3c_tsco {
>>> +	I3C_TSCO_LT_8NS,
>>> +	I3C_TSCO_LT_9NS,
>>> +	I3C_TSCO_LT_10NS,
>>> +	I3C_TSCO_LT_11NS,
>>> +	I3C_TSCO_LT_12NS,
>>> +};  
>> what's the meaning of _LT_ ?
> This I don't remember. I'll drop it in the next version.
>
>>> +
>>> +#endif /* I3C_CCC_H */
>>> diff --git a/include/linux/i3c/device.h b/include/linux/i3c/device.h
>>> new file mode 100644
>>> index 000000000000..83958d3a02e2
>>> --- /dev/null
>>> +++ b/include/linux/i3c/device.h
>>> @@ -0,0 +1,321 @@
>>> +/* SPDX-License-Identifier: GPL-2.0 */
>>> +/*
>>> + * Copyright (C) 2017 Cadence Design Systems Inc.
>>> + *
>>> + * Author: Boris Brezillon<boris.brezillon@free-electrons.com>
>>> + */
>>> +
>>> +#ifndef I3C_DEV_H
>>> +#define I3C_DEV_H
>>> +
>>> +#include <linux/device.h>
>>> +#include <linux/i2c.h>
>>> +#include <linux/mod_devicetable.h>
>>> +#include <linux/module.h>
>>> +
>>> +/**
>>> + * enum i3c_hdr_mode - HDR mode ids
>>> + * @I3C_HDR_DDR: DDR mode
>>> + * @I3C_HDR_TSP: TSP mode
>>> + * @I3C_HDR_TSL: TSL mode
>>> + */
>>> +enum i3c_hdr_mode {
>>> +	I3C_HDR_DDR,
>>> +	I3C_HDR_TSP,
>>> +	I3C_HDR_TSL,
>>> +};
>>> +
>>> +/**
>>> + * struct i3c_hdr_cmd - I3C HDR command
>>> + * @mode: HDR mode selected for this command
>>> + * @code: command opcode
>>> + * @addr: I3C dynamic address
>>> + * @ndatawords: number of data words (a word is 16bits wide)
>>> + * @data: input/output buffer
>>> + */
>>> +struct i3c_hdr_cmd {
>>> +	enum i3c_hdr_mode mode;
>>> +	u8 code;
>>> +	u8 addr;
>>> +	int ndatawords;
>>> +	union {
>>> +		u16 *in;
>>> +		const u16 *out;
>>> +	} data;
>>> +};
Please mention that the @code is what will define if the transfer is read or write.
>>> +
>>> +/* Private SDR read transfer */
>>> +#define I3C_PRIV_XFER_READ		BIT(0)
>>> +/*
>>> + * Instruct the controller to issue a STOP after a specific transfer instead
>>> + * of a REPEATED START.
>>> + */
>>> +#define I3C_PRIV_XFER_STOP		BIT(1)
>>> +
>>> +/**
>>> + * struct i3c_priv_xfer - I3C SDR private transfer
>>> + * @addr: I3C dynamic address
>>> + * @len: transfer length in bytes of the transfer
>>> + * @flags: combination of I3C_PRIV_XFER_xxx flags
>>> + * @data: input/output buffer
>>> + */
>>> +struct i3c_priv_xfer {
>>> +	u8 addr;
>>> +	u16 len;
>>> +	u32 flags;
>>> +	struct {
>>> +		void *in;
>>> +		const void *out;
>>> +	} data;
>>> +};  
>>  Same as above, i3c_sdr_max_data_rate to change the bus scl.
> If I'm understanding the spec correctly, that's not something you want
> to change on a per-transfer basis. The constraint is on the device
> itself and should IMO not be part of the i3c_priv_xfer struct.
As mention before this is important.
You can do the same as for struct i3c_hdr_cmd and add a enum i3c_sdr_max_data_rate.

The @flag only have 2 bits of load, is the rest opened?
>
>>  > +
>>> +/**
>>> + * enum i3c_dcr - I3C DCR values
>>> + * @I3C_DCR_GENERIC_DEVICE: generic I3C device
>>> + */
>>> +enum i3c_dcr {
>>> +	I3C_DCR_GENERIC_DEVICE = 0,
>>> +};
>>> +
>>> +#define I3C_PID_MANUF_ID(pid)		(((pid) & GENMASK_ULL(47, 33)) >> 33)
>>> +#define I3C_PID_RND_LOWER_32BITS(pid)	(!!((pid) & BIT_ULL(32)))
>>> +#define I3C_PID_RND_VAL(pid)		((pid) & GENMASK_ULL(31, 0))
>>> +#define I3C_PID_PART_ID(pid)		(((pid) & GENMASK_ULL(31, 16)) >> 16)
>>> +#define I3C_PID_INSTANCE_ID(pid)	(((pid) & GENMASK_ULL(15, 12)) >> 12)
>>> +#define I3C_PID_EXTRA_INFO(pid)		((pid) & GENMASK_ULL(11, 0))
>>> +
>>> +#define I3C_BCR_DEVICE_ROLE(bcr)	((bcr) & GENMASK(7, 6))
>>> +#define I3C_BCR_I3C_SLAVE		(0 << 6)
>>> +#define I3C_BCR_I3C_MASTER		(1 << 6)
>>> +#define I3C_BCR_HDR_CAP			BIT(5)
>>> +#define I3C_BCR_BRIDGE			BIT(4)
>>> +#define I3C_BCR_OFFLINE_CAP		BIT(3)
>>> +#define I3C_BCR_IBI_PAYLOAD		BIT(2)
>>> +#define I3C_BCR_IBI_REQ_CAP		BIT(1)
>>> +#define I3C_BCR_MAX_DATA_SPEED_LIM	BIT(0)
>>> +
>>> +/**
>>> + * struct i3c_device_info - I3C device information
>>> + * @pid: Provisional ID
>>> + * @bcr: Bus Characteristic Register
>>> + * @dcr: Device Characteristic Register
>>> + * @static_addr: static/I2C address
>>> + * @dyn_addr: dynamic address
>>> + * @hdr_cap: supported HDR modes
>>> + * @max_read_ds: max read speed information
>>> + * @max_write_ds: max write speed information
>>> + * @max_ibi_len: max IBI payload length
>>> + * @max_read_turnaround: max read turn-around time in micro-seconds
>>> + * @max_read_len: max private SDR read length in bytes
>>> + * @max_write_len: max private SDR write length in bytes
>>> + *
>>> + * These are all basic information that should be advertised by an I3C device.
>>> + * Some of them are optional depending on the device type and device
>>> + * capabilities.
>>> + * For each I3C slave attached to a master with
>>> + * i3c_master_add_i3c_dev_locked(), the core will send the relevant CCC command
>>> + * to retrieve these data.
>>> + */
>>> +struct i3c_device_info {
>>> +	u64 pid;
>>> +	u8 bcr;
>>> +	u8 dcr;
>>> +	u8 static_addr;
>>> +	u8 dyn_addr;
>>> +	u8 hdr_cap;
>>> +	u8 max_read_ds;
>>> +	u8 max_write_ds;
>>> +	u8 max_ibi_len;
>>> +	u32 max_read_turnaround;
>>> +	u16 max_read_len;
>>> +	u16 max_write_len;
>>> +};
>>> +  
>>  is this information filled with data provided from CCC commands?
> Yes, they are.
Ok, them the intention is to do this on bus_init(), right?
>
>>  > +
>>> +#endif /* I3C_DEV_H */
>>> diff --git a/include/linux/i3c/master.h b/include/linux/i3c/master.h
>>> new file mode 100644
>>> index 000000000000..7ec9a4821bac
>>> --- /dev/null
>>> +++ b/include/linux/i3c/master.h
>>> @@ -0,0 +1,564 @@
>>> +/* SPDX-License-Identifier: GPL-2.0 */
>>> +/*
>>> + * Copyright (C) 2017 Cadence Design Systems Inc.
>>> + *
>>> + * Author: Boris Brezillon<boris.brezillon@free-electrons.com>
>>> + */
>>> +
>>> +#ifndef I3C_MASTER_H
>>> +#define I3C_MASTER_H
>>> +
>>> +#include <linux/i2c.h>
>>> +#include <linux/i3c/ccc.h>
>>> +#include <linux/i3c/device.h>
>>> +#include <linux/spinlock.h>
>>> +
>>> +#define I3C_HOT_JOIN_ADDR		0x2
>>> +#define I3C_BROADCAST_ADDR		0x7e
>>> +#define I3C_MAX_ADDR			GENMASK(6, 0)
>>> +
>>> +struct i3c_master_controller;
>>> +struct i3c_bus;
>>> +
>>> +/**
>>> + * struct i3c_i2c_dev - I3C/I2C common information
>>> + * @node: node element used to insert the device into the I2C or I3C device
>>> + *	  list
>>> + * @bus: I3C bus this device is connected to
>>> + * @master: I3C master that instantiated this device. Will be used to send
>>> + *	    I2C/I3C frames on the bus
>>> + * @master_priv: master private data assigned to the device. Can be used to
>>> + *		 add master specific information
>>> + *
>>> + * This structure is describing common I3C/I2C dev information.
>>> + */
>>> +struct i3c_i2c_dev {
>>> +	struct list_head node;
>>> +	struct i3c_bus *bus;
>>> +	struct i3c_master_controller *master;
>>> +	void *master_priv;
>>> +};
>>> +
>>> +#define I3C_LVR_I2C_INDEX_MASK		GENMASK(7, 5)
>>> +#define I3C_LVR_I2C_INDEX(x)		((x) << 5)
>>> +#define I3C_LVR_I2C_FM_MODE		BIT(4)
>>> +
>>> +#define I2C_MAX_ADDR			GENMASK(9, 0)  
>>  why 10-bit address?
>>
> Because some I2C devices have 10-bit addresses.
>
>>  > +
>>> +/**
>>> + * struct i2c_device - I2C device object
>>> + * @common: inherit common I3C/I2C description
>>> + * @info: I2C board info used to instantiate the I2C device. If you are
>>> + *	  using DT to describe your hardware, this will be filled for you
>>> + * @client: I2C client object created by the I2C framework. This will only
>>> + *	    be valid after i3c_master_register() returns
>>> + * @lvr: Legacy Virtual Register value as described in the I3C specification
>>> + *
>>> + * I2C device object. Note that the real I2C device is represented by
>>> + * i2c_device->client, but we need extra information to handle the device when
>>> + * it's connected to an I3C bus, hence the &struct i2c_device wrapper.
>>> + *
>>> + * The I2C framework is not impacted by this new representation.
>>> + */
>>> +struct i2c_device {
>>> +	struct i3c_i2c_dev common;
>>> +	struct i2c_board_info info;
>>> +	struct i2c_client *client;
>>> +	u8 lvr;
>>> +};
>>> +  
>>  It is usefull to know the speed limitations of the device.
> See my previous explanation about I2C and the max frequency. BTW, the
> FM vs FM+ information is already encoded in the ->lvr field.
you are right.
>>  > +
>>> +/**
>>> + * enum i3c_addr_slot_status - I3C address slot status
>>> + * @I3C_ADDR_SLOT_FREE: address is free
>>> + * @I3C_ADDR_SLOT_RSVD: address is reserved
>>> + * @I3C_ADDR_SLOT_I2C_DEV: address is assigned to an I2C device
>>> + * @I3C_ADDR_SLOT_I3C_DEV: address is assigned to an I3C device
>>> + * @I3C_ADDR_SLOT_STATUS_MASK: address slot mask
>>> + *
>>> + * On an I3C bus, addresses are assigned dynamically, and we need to know which
>>> + * addresses are free to use and which ones are already assigned.
>>> + *
>>> + * Addresses marked as reserved are those reserved by the I3C protocol
>>> + * (broadcast address, ...).
>>> + */
>>> +enum i3c_addr_slot_status {
>>> +	I3C_ADDR_SLOT_FREE,
>>> +	I3C_ADDR_SLOT_RSVD,
>>> +	I3C_ADDR_SLOT_I2C_DEV,
>>> +	I3C_ADDR_SLOT_I3C_DEV,
>>> +	I3C_ADDR_SLOT_STATUS_MASK = 3,
>>> +};
>>> +
>>> +/**
>>> + * struct i3c_bus - I3C bus object
>>> + * @dev: device to be registered to the device-model
>>> + * @cur_master: I3C master currently driving the bus. Since I3C is multi-master
>>> + *		this can change over the time. Will be used to let a master
>>> + *		know whether it needs to request bus ownership before sending
>>> + *		a frame or not
>>> + * @id: bus ID. Assigned by the framework when register the bus
>>> + * @addrslots: a bitmap with 2-bits per-slot to encode the address status and
>>> + *	       ease the DAA (Dynamic Address Assignment) procedure (see
>>> + *	       &enum i3c_addr_slot_status)
>>> + * @mode: bus mode (see &enum i3c_bus_mode)
>>> + * @scl_rate: SCL signal rate for I3C and I2C mode
>>> + * @devs: 2 lists containing all I3C/I2C devices connected to the bus
>>> + * @lock: read/write lock on the bus. This is needed to protect against
>>> + *	  operations that have an impact on the whole bus and the devices
>>> + *	  connected to it. For example, when asking slaves to drop their
>>> + *	  dynamic address (RSTDAA CCC), we need to make sure no one is trying
>>> + *	  to send I3C frames to these devices.
>>> + *	  Note that this lock does not protect against concurrency between
>>> + *	  devices: several drivers can send different I3C/I2C frames through
>>> + *	  the same master in parallel. This is the responsibility of the
>>> + *	  master to guarantee that frames are actually sent sequentially and
>>> + *	  not interlaced
>>> + *
>>> + * The I3C bus is represented with its own object and not implicitly described
>>> + * by the I3C master to cope with the multi-master functionality, where one bus
>>> + * can be shared amongst several masters, each of them requesting bus ownership
>>> + * when they need to.
>>> + */
>>> +struct i3c_bus {
>>> +	struct device dev;
>>> +	struct i3c_device *cur_master;
>>> +	int id;
>>> +	unsigned long addrslots[((I2C_MAX_ADDR + 1) * 2) / BITS_PER_LONG];
>>> +	enum i3c_bus_mode mode;
>>> +	struct {
>>> +		unsigned long i3c;
>>> +		unsigned long i2c;
>>> +	} scl_rate;
>>> +	struct {
>>> +		struct list_head i3c;
>>> +		struct list_head i2c;
>>> +	} devs;
>>> +	struct rw_semaphore lock;
>>> +};  
>> Can you explain the addrslots[] ?
> It's a bitmap encoding the status of I3C/I2C addresses: are they
> assigned, reserved of free, and if they are assigned is it an I3C or
> I2C device. That's particularly useful to master controller drivers
> to know which addresses they can assign during DAA.
>
> I'll try to clarify it in the kernel-doc header.
yes please.
>
>>> +
>>> +static inline struct i3c_device *dev_to_i3cdev(struct device *dev)
>>> +{
>>> +	return container_of(dev, struct i3c_device, dev);
>>> +}
>>> +
>>> +struct i3c_master_controller;
>>> +
>>> +/**
>>> + * struct i3c_master_controller_ops - I3C master methods
>>> + * @bus_init: hook responsible for the I3C bus initialization. This
>>> + *	      initialization should follow the steps described in the I3C
>>> + *	      specification. This hook is called with the bus lock held in
>>> + *	      write mode, which means all _locked() helpers can safely be
>>> + *	      called from there
>>> + * @bus_cleanup: cleanup everything done in
>>> + *		 &i3c_master_controller_ops->bus_init(). This function is
>>> + *		 optional and should only be implemented if
>>> + *		 &i3c_master_controller_ops->bus_init() attached private data
>>> + *		 to I3C/I2C devices. This hook is called with the bus lock
>>> + *		 held in write mode, which means all _locked() helpers can
>>> + *		 safely be called from there
>>> + * @supports_ccc_cmd: should return true if the CCC command is supported, false
>>> + *		      otherwise
>>> + * @send_ccc_cmd: send a CCC command
>>> + * @send_hdr_cmds: send one or several HDR commands. If there is more than one
>>> + *		   command, they should ideally be sent in the same HDR
>>> + *		   transaction
>>> + * @priv_xfers: do one or several private I3C SDR transfers
>>> + * @i2c_xfers: do one or several I2C transfers
>>> + * @request_ibi: attach an IBI handler to an I3C device. This implies defining
>>> + *		 an IBI handler and the constraints of the IBI (maximum payload
>>> + *		 length and number of pre-allocated slots).
>>> + *		 Some controllers support less IBI-capable devices than regular
>>> + *		 devices, so this method might return -%EBUSY if there's no
>>> + *		 more space for an extra IBI registration
>>> + * @free_ibi: free an IBI previously requested with ->request_ibi(). The IBI
>>> + *	      should have been disabled with ->disable_irq() prior to that
>>> + * @enable_ibi: enable the IBI. Only valid if ->request_ibi() has been called
>>> + *		prior to ->enable_ibi(). The controller should first enable
>>> + *		the IBI on the controller end (for example, unmask the hardware
>>> + *		IRQ) and then send the ENEC CCC command (with the IBI flag set)
>>> + *		to the I3C device
>>> + * @disable_ibi: disable an IBI. First send the DISEC CCC command with the IBI
>>> + *		 flag set and then deactivate the hardware IRQ on the
>>> + *		 controller end
>>> + * @recycle_ibi_slot: recycle an IBI slot. Called every time an IBI has been
>>> + *		      processed by its handler. The IBI slot should be put back
>>> + *		      in the IBI slot pool so that the controller can re-use it
>>> + *		      for a future IBI
>>> + *
>>> + * One of the most important hooks in these ops is
>>> + * &i3c_master_controller_ops->bus_init(). Here is a non-exhaustive list of
>>> + * things that should be done in &i3c_master_controller_ops->bus_init():
>>> + *
>>> + * 1) call i3c_master_set_info() with all information describing the master
>>> + * 2) ask all slaves to drop their dynamic address by sending the RSTDAA CCC
>>> + *    with i3c_master_rstdaa_locked()
>>> + * 3) ask all slaves to disable IBIs using i3c_master_disec_locked()
>>> + * 4) start a DDA procedure by sending the ENTDAA CCC with
>>> + *    i3c_master_entdaa_locked(), or using the internal DAA logic provided by
>>> + *    your controller  
>> You mean SETDASA CCC command?
> No, I really mean ENTDAA and DAA. By internal DAA logic I mean that
> some controllers are probably automating the whole DAA procedure, while
> others may let the SW control every step.
My understanding is that i3c_master_entdaa_locked() will trigger the DAA process
and DAA can be done by SETDASA, ENTDAA and later after the bus initialization
with SETNEWDA.

I think the DAA process should be more generic, right now is only made through
the ENTDAA command with (cmd.ndests = 1).
I mean, shouldn't this be made by the core? First doing DAA for the devices
declared and them try do discover the rest of devices on the bus. 
>
> Thanks for your review.
>
> Boris
>

Thank you,
Vitor Soares
Boris Brezillon Feb. 26, 2018, 8:36 p.m. UTC | #16 
Hi Vitor,

On Mon, 26 Feb 2018 18:58:15 +0000
Vitor Soares <Vitor.Soares@synopsys.com> wrote:

> >>> +/**
> >>> + * i3c_device_do_priv_xfers() - do I3C SDR private transfers directed to a
> >>> + *				specific device
> >>> + *
> >>> + * @dev: device with which the transfers should be done
> >>> + * @xfers: array of transfers
> >>> + * @nxfers: number of transfers
> >>> + *
> >>> + * Initiate one or several private SDR transfers with @dev.
> >>> + *
> >>> + * This function can sleep and thus cannot be called in atomic context.
> >>> + *
> >>> + * Return: 0 in case of success, a negative error core otherwise.
> >>> + */
> >>> +int i3c_device_do_priv_xfers(struct i3c_device *dev,
> >>> +			     struct i3c_priv_xfer *xfers,
> >>> +			     int nxfers)
> >>> +{
> >>> +	struct i3c_master_controller *master;
> >>> +	int i, ret;
> >>> +
> >>> +	master = i3c_device_get_master(dev);
> >>> +	if (!master)
> >>> +		return -EINVAL;
> >>> +
> >>> +	i3c_bus_normaluse_lock(master->bus);
> >>> +	for (i = 0; i < nxfers; i++)
> >>> +		xfers[i].addr = dev->info.dyn_addr;
> >>> +
> >>> +	ret = i3c_master_do_priv_xfers_locked(master, xfers, nxfers);
> >>> +	i3c_bus_normaluse_unlock(master->bus);
> >>> +
> >>> +	return ret;
> >>> +}
> >>> +EXPORT_SYMBOL_GPL(i3c_device_do_priv_xfers);    
> >>  The controller should know the speed mode for each xfer. The SDR0 mode 
> >> is used by default but if any device have read or write speed 
> >> limitations the controller can use SDRx.  
> > I might be wrong, but that's not my understanding of the spec. A device
> > can express a speed limitation for SDR priv transfers, but this
> > limitation applies to all SDR transfers.
> >
> > The speed R/W speed limitation is encoded in the device object, so, if
> > the controller has to configure that on a per-transfer basis, one
> > solution would be to pass the device to the ->priv_xfers().  
> The speed R/W limitation is only for private transfers. Also the device can have
> a limitation to write and not for read data.
> This information is obtained with the command GETMXDS which returns the Maximum
> Sustained Data Rate for non-CCC messages.

And that's exactly what I expose in i3c_device_info, which is embedded
in i3c_device, so you should have all the information you need to
determine the speed in the controller driver if ->priv_xfer() is passed
the device attached to those transfers. Would that be okay if we pass an
i3c_device object to ->priv_xfers()?

> >  
> >> This could be also applied to i2c transfers.  
> > Not really. The max SCL frequency is something that applies to the
> > whole bus, because all I2C devices have to decode the address when
> > messages are sent on the bus to determine if they should ignore or
> > process the message.
> >  
> >>> +#endif /* I3C_INTERNAL_H */
> >>> diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c
> >>> new file mode 100644
> >>> index 000000000000..1c85abac08d5
> >>> --- /dev/null
> >>> +++ b/drivers/i3c/master.c
> >>> @@ -0,0 +1,1433 @@
> >>> +// SPDX-License-Identifier: GPL-2.0
> >>> +/*
> >>> + * Copyright (C) 2017 Cadence Design Systems Inc.
> >>> + *
> >>> + * Author: Boris Brezillon<boris.brezillon@free-electrons.com>
> >>> + */
> >>> +
> >>> +#include <linux/slab.h>
> >>> +
> >>> +#include "internals.h"
> >>> +
> >>> +/**
> >>> + * i3c_master_entdaa_locked() - start a DAA (Dynamic Address Assignment)
> >>> + *				procedure
> >>> + * @master: master used to send frames on the bus
> >>> + *
> >>> + * Send a ENTDAA CCC command to start a DAA procedure.
> >>> + *
> >>> + * Note that this function only sends the ENTDAA CCC command, all the logic
> >>> + * behind dynamic address assignment has to be handled in the I3C master
> >>> + * driver.
> >>> + *
> >>> + * This function must be called with the bus lock held in write mode.
> >>> + *
> >>> + * Return: 0 in case of success, a negative error code otherwise.
> >>> + */
> >>> +int i3c_master_entdaa_locked(struct i3c_master_controller *master)
> >>> +{
> >>> +	struct i3c_ccc_cmd_dest dest = { };
> >>> +	struct i3c_ccc_cmd cmd = { };
> >>> +	int ret;
> >>> +
> >>> +	dest.addr = I3C_BROADCAST_ADDR;
> >>> +	cmd.dests = &dest;
> >>> +	cmd.ndests = 1;
> >>> +	cmd.rnw = false;
> >>> +	cmd.id = I3C_CCC_ENTDAA;
> >>> +
> >>> +	ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
> >>> +	if (ret)
> >>> +		return ret;
> >>> +
> >>> +	return 0;
> >>> +}
> >>> +EXPORT_SYMBOL_GPL(i3c_master_entdaa_locked);    
> >>  can you explain the process?  
> > Not sure what you mean. The ENTDAA is just a CCC command that is used
> > to trigger a DAA procedure. What the master controller does when it
> > sends such a command is likely to be controller dependent, and it might
> > even be possible that you don't need to call this function in your
> > controller driver to trigger a DAA. If you want more details about the
> > bus initialization steps and how the ENTDAA CCC command fits into it I
> > recommend reading section "5.1.4 Bus Initialization and Dynamic Address
> > Assignment Mode"
> >  
> >> the command is only execute once, what if 
> >> there is more devices on the bus?  
> > Again, I'm not sure what you mean. The ENTDAA command is sent every
> > time a controller wants to discover new devices on the bus, that can be
> > when initializing the bus, after a Hot Join event or simply triggered
> > by the user (the last case is not supported yet though).
> >
> > Now, if you're interested in what happens after an ENTDAA CCC is sent,
> > the controller will keep sending RepeatedStart until there's no more
> > devices acking the request. You can have a look at "B.3 Error Types in
> > Dynamic Address Arbitration" for more details.  
> My understanding is this command shall be executed once, this mean that only one
> slave will assign the dynamic address (cmd.ndests = 1) and not trigger the whole
> process of DAA.

No, that's not what happens. The master controller is supposed to
continue until no one replies with an Ack on the bus, and by continue I
don't mean resend an ENTDAA, but issue a RepeatedStart followed by the
broadcast address (0x7e).

> Either important is the SETDASA for declared I3C devices. So the DAA process
> should start by send an SETDASA and them ENTDAA CCC command.

My understanding was that SETDASA was not mandatory, and was only useful
when one wants to assign a specific dynamic address to a slave that has
a static address (which is again not mandatory).
I've tested it, and even devices with a static address participate to
the DAA procedure if they've not been assigned a dynamic address yet,
so I don't see the need for this SETDASA step if you don't need to
assign a particular dynamic address to the device.

Could you tell me why you think SETDASA is required?

> >>> +static u32 i3c_master_i2c_functionalities(struct i2c_adapter *adap)
> >>> +{
> >>> +	return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR;
> >>> +}    
> >>  Is I2C_FUNC_10BIT_ADDR allowed ?  
> > According to "Table 4 I 2 C Features Allowed in I3C Slaves", yes (at
> > least that my understanding). And the Cadence controller supports it.  
> The table say the oposite. The I2C extended address feature is not used on I3C
> bus, thus this feature shall be disable.

Actually, I was wrong when initially mentioning this table: it's about
I2C features supported on I3C slaves, so not really what we're looking
for. Here, we're wondering if I2C-only devices can have 10-bit
addresses. The Cadence controller supports that, so there's probably
nothing preventing use of 10-bit addresses for I2C transfers, but maybe
not all I3C master controllers support that, so we should probably
let the I3C master driver implement this method.

> BTW it is optional on I2C devices.

You mean I2C controllers? When an I2C device has a 10bit address, the
controller has to support this mode to communicate with the device, at
least that's my understanding. But we're digressing a bit. The
question is not whether I2C devices can optionally use a 10 bit
address, but whether I3C master controller can support this mode for
I2C transfers to I2C-only devices.

> 
> >  
> >>  > diff --git a/drivers/i3c/master/Kconfig b/drivers/i3c/master/Kconfig
> >>> new file mode 100644
> >>> index 000000000000..e69de29bb2d1
> >>> diff --git a/drivers/i3c/master/Makefile b/drivers/i3c/master/Makefile
> >>> new file mode 100644
> >>> index 000000000000..e69de29bb2d1
> >>> diff --git a/include/linux/i3c/ccc.h b/include/linux/i3c/ccc.h
> >>> new file mode 100644
> >>> index 000000000000..ff3e1a3e2c4c
> >>> --- /dev/null
> >>> +++ b/include/linux/i3c/ccc.h
> >>> @@ -0,0 +1,380 @@
> >>> +/* SPDX-License-Identifier: GPL-2.0 */
> >>> +/*
> >>> + * Copyright (C) 2017 Cadence Design Systems Inc.
> >>> + *
> >>> + * Author: Boris Brezillon<boris.brezillon@free-electrons.com>
> >>> + */
> >>> +
> >>> +
> >>> +/**
> >>> + * enum i3c_ccc_test_mode - enum listing all available test modes
> >>> + *
> >>> + * @I3C_CCC_EXIT_TEST_MODE: exit test mode
> >>> + * @I3C_CCC_VENDOR_TEST_MODE: enter vendor test mode
> >>> + */
> >>> +enum i3c_ccc_test_mode {
> >>> +	I3C_CCC_EXIT_TEST_MODE,
> >>> +	I3C_CCC_VENDOR_TEST_MODE,
> >>> +};
> >>> +
> >>> +/**
> >>> + * struct i3c_ccc_enttm - payload passed to ENTTM CCC
> >>> + *
> >>> + * @mode: one of the &enum i3c_ccc_test_mode modes
> >>> + *
> >>> + * Information passed to the ENTTM CCC to instruct an I3C device to enter a
> >>> + * specific test mode.
> >>> + */
> >>> +struct i3c_ccc_enttm {
> >>> +	u8 mode;
> >>> +} __packed;
> >>> +
> >>> +/**
> >>> + * struct i3c_ccc_setda - payload passed to ENTTM CCC
> >>> + *
> >>> + * @mode: one of the &enum i3c_ccc_test_mode modes
> >>> + *
> >>> + * Information passed to the ENTTM CCC to instruct an I3C device to enter a
> >>> + * specific test mode.
> >>> + */
> >>> +struct i3c_ccc_setda {
> >>> +	u8 addr;
> >>> +} __packed;    
> >>  what do you mean with struct? Maybe setdasa? if so, what is the addr?  
> Do you have the function to use this structure? Because one command use the
> static address and the other use the dynamic address.
> 
> >>  
> >>  > +/**
> >>> + * enum i3c_sdr_max_data_rate - max data rate values for private SDR transfers
> >>> + */
> >>> +enum i3c_sdr_max_data_rate {
> >>> +	I3C_SDR_DR_FSCL_MAX,
> >>> +	I3C_SDR_DR_FSCL_8MHZ,
> >>> +	I3C_SDR_DR_FSCL_6MHZ,
> >>> +	I3C_SDR_DR_FSCL_4MHZ,
> >>> +	I3C_SDR_DR_FSCL_2MHZ,
> >>> +};    
> >> Can you change the names to:
> >>
> >> I3C_SDR0_FSCL_MAX,
> >> I3C_SDR1_FSCL_8MHZ,
> >> I3C_SDR2_FSCL_6MHZ,
> >> I3C_SDR3_FSCL_4MHZ,
> >> I3C_SDR4_FSCL_2MHZ,
> >>
> >> thus the data rate isn't repeated.  
> > What's the problem with the name I use? Moreover, I see no mention to
> > the SDR0,1,2,3,4 modes in the public spec.  
> When you get the GETMXDS information, the maxWr and maxRd came from 0 to 4, so
> in my opinion I think in this way is easier to have a relationship.

It's an emum, and there's no mention of the SDRX modes you're using
here in the I3C spec. I guess it's named this way in your I3C
controller datasheet. I personally don't see a good reason to add SDRX
in the name, but if you insist...

> >>> +
> >>> +#endif /* I3C_CCC_H */
> >>> diff --git a/include/linux/i3c/device.h b/include/linux/i3c/device.h
> >>> new file mode 100644
> >>> index 000000000000..83958d3a02e2
> >>> --- /dev/null
> >>> +++ b/include/linux/i3c/device.h
> >>> @@ -0,0 +1,321 @@
> >>> +/* SPDX-License-Identifier: GPL-2.0 */
> >>> +/*
> >>> + * Copyright (C) 2017 Cadence Design Systems Inc.
> >>> + *
> >>> + * Author: Boris Brezillon<boris.brezillon@free-electrons.com>
> >>> + */
> >>> +
> >>> +#ifndef I3C_DEV_H
> >>> +#define I3C_DEV_H
> >>> +
> >>> +#include <linux/device.h>
> >>> +#include <linux/i2c.h>
> >>> +#include <linux/mod_devicetable.h>
> >>> +#include <linux/module.h>
> >>> +
> >>> +/**
> >>> + * enum i3c_hdr_mode - HDR mode ids
> >>> + * @I3C_HDR_DDR: DDR mode
> >>> + * @I3C_HDR_TSP: TSP mode
> >>> + * @I3C_HDR_TSL: TSL mode
> >>> + */
> >>> +enum i3c_hdr_mode {
> >>> +	I3C_HDR_DDR,
> >>> +	I3C_HDR_TSP,
> >>> +	I3C_HDR_TSL,
> >>> +};
> >>> +
> >>> +/**
> >>> + * struct i3c_hdr_cmd - I3C HDR command
> >>> + * @mode: HDR mode selected for this command
> >>> + * @code: command opcode
> >>> + * @addr: I3C dynamic address
> >>> + * @ndatawords: number of data words (a word is 16bits wide)
> >>> + * @data: input/output buffer
> >>> + */
> >>> +struct i3c_hdr_cmd {
> >>> +	enum i3c_hdr_mode mode;
> >>> +	u8 code;
> >>> +	u8 addr;
> >>> +	int ndatawords;
> >>> +	union {
> >>> +		u16 *in;
> >>> +		const u16 *out;
> >>> +	} data;
> >>> +};  
> Please mention that the @code is what will define if the transfer is read or write.

Well, I think it's pretty clear in the definition you'll find in the
ccc.h file, but I can add a comment here too if you like.

> >>> +
> >>> +/* Private SDR read transfer */
> >>> +#define I3C_PRIV_XFER_READ		BIT(0)
> >>> +/*
> >>> + * Instruct the controller to issue a STOP after a specific transfer instead
> >>> + * of a REPEATED START.
> >>> + */
> >>> +#define I3C_PRIV_XFER_STOP		BIT(1)
> >>> +
> >>> +/**
> >>> + * struct i3c_priv_xfer - I3C SDR private transfer
> >>> + * @addr: I3C dynamic address
> >>> + * @len: transfer length in bytes of the transfer
> >>> + * @flags: combination of I3C_PRIV_XFER_xxx flags
> >>> + * @data: input/output buffer
> >>> + */
> >>> +struct i3c_priv_xfer {
> >>> +	u8 addr;
> >>> +	u16 len;
> >>> +	u32 flags;
> >>> +	struct {
> >>> +		void *in;
> >>> +		const void *out;
> >>> +	} data;
> >>> +};    
> >>  Same as above, i3c_sdr_max_data_rate to change the bus scl.  
> > If I'm understanding the spec correctly, that's not something you want
> > to change on a per-transfer basis. The constraint is on the device
> > itself and should IMO not be part of the i3c_priv_xfer struct.  
> As mention before this is important.
> You can do the same as for struct i3c_hdr_cmd and add a enum i3c_sdr_max_data_rate.
> 
> The @flag only have 2 bits of load, is the rest opened?

If by open you mean that we can add more flags if we need to, then yes.

> >  
> >>  > +
> >>> +/**
> >>> + * enum i3c_dcr - I3C DCR values
> >>> + * @I3C_DCR_GENERIC_DEVICE: generic I3C device
> >>> + */
> >>> +enum i3c_dcr {
> >>> +	I3C_DCR_GENERIC_DEVICE = 0,
> >>> +};
> >>> +
> >>> +#define I3C_PID_MANUF_ID(pid)		(((pid) & GENMASK_ULL(47, 33)) >> 33)
> >>> +#define I3C_PID_RND_LOWER_32BITS(pid)	(!!((pid) & BIT_ULL(32)))
> >>> +#define I3C_PID_RND_VAL(pid)		((pid) & GENMASK_ULL(31, 0))
> >>> +#define I3C_PID_PART_ID(pid)		(((pid) & GENMASK_ULL(31, 16)) >> 16)
> >>> +#define I3C_PID_INSTANCE_ID(pid)	(((pid) & GENMASK_ULL(15, 12)) >> 12)
> >>> +#define I3C_PID_EXTRA_INFO(pid)		((pid) & GENMASK_ULL(11, 0))
> >>> +
> >>> +#define I3C_BCR_DEVICE_ROLE(bcr)	((bcr) & GENMASK(7, 6))
> >>> +#define I3C_BCR_I3C_SLAVE		(0 << 6)
> >>> +#define I3C_BCR_I3C_MASTER		(1 << 6)
> >>> +#define I3C_BCR_HDR_CAP			BIT(5)
> >>> +#define I3C_BCR_BRIDGE			BIT(4)
> >>> +#define I3C_BCR_OFFLINE_CAP		BIT(3)
> >>> +#define I3C_BCR_IBI_PAYLOAD		BIT(2)
> >>> +#define I3C_BCR_IBI_REQ_CAP		BIT(1)
> >>> +#define I3C_BCR_MAX_DATA_SPEED_LIM	BIT(0)
> >>> +
> >>> +/**
> >>> + * struct i3c_device_info - I3C device information
> >>> + * @pid: Provisional ID
> >>> + * @bcr: Bus Characteristic Register
> >>> + * @dcr: Device Characteristic Register
> >>> + * @static_addr: static/I2C address
> >>> + * @dyn_addr: dynamic address
> >>> + * @hdr_cap: supported HDR modes
> >>> + * @max_read_ds: max read speed information
> >>> + * @max_write_ds: max write speed information
> >>> + * @max_ibi_len: max IBI payload length
> >>> + * @max_read_turnaround: max read turn-around time in micro-seconds
> >>> + * @max_read_len: max private SDR read length in bytes
> >>> + * @max_write_len: max private SDR write length in bytes
> >>> + *
> >>> + * These are all basic information that should be advertised by an I3C device.
> >>> + * Some of them are optional depending on the device type and device
> >>> + * capabilities.
> >>> + * For each I3C slave attached to a master with
> >>> + * i3c_master_add_i3c_dev_locked(), the core will send the relevant CCC command
> >>> + * to retrieve these data.
> >>> + */
> >>> +struct i3c_device_info {
> >>> +	u64 pid;
> >>> +	u8 bcr;
> >>> +	u8 dcr;
> >>> +	u8 static_addr;
> >>> +	u8 dyn_addr;
> >>> +	u8 hdr_cap;
> >>> +	u8 max_read_ds;
> >>> +	u8 max_write_ds;
> >>> +	u8 max_ibi_len;
> >>> +	u32 max_read_turnaround;
> >>> +	u16 max_read_len;
> >>> +	u16 max_write_len;
> >>> +};
> >>> +    
> >>  is this information filled with data provided from CCC commands?  
> > Yes, they are.  
> Ok, them the intention is to do this on bus_init(), right?

Not only, it can be after a Hot-Join, or after the user has triggered a
new DAA. Anyway, these information are retrieved anytime you add a
device with i3c_master_add_i3c_dev_locked(), and the core uses CCC
commands to do that.

> >>> +
> >>> +/**
> >>> + * struct i3c_master_controller_ops - I3C master methods
> >>> + * @bus_init: hook responsible for the I3C bus initialization. This
> >>> + *	      initialization should follow the steps described in the I3C
> >>> + *	      specification. This hook is called with the bus lock held in
> >>> + *	      write mode, which means all _locked() helpers can safely be
> >>> + *	      called from there
> >>> + * @bus_cleanup: cleanup everything done in
> >>> + *		 &i3c_master_controller_ops->bus_init(). This function is
> >>> + *		 optional and should only be implemented if
> >>> + *		 &i3c_master_controller_ops->bus_init() attached private data
> >>> + *		 to I3C/I2C devices. This hook is called with the bus lock
> >>> + *		 held in write mode, which means all _locked() helpers can
> >>> + *		 safely be called from there
> >>> + * @supports_ccc_cmd: should return true if the CCC command is supported, false
> >>> + *		      otherwise
> >>> + * @send_ccc_cmd: send a CCC command
> >>> + * @send_hdr_cmds: send one or several HDR commands. If there is more than one
> >>> + *		   command, they should ideally be sent in the same HDR
> >>> + *		   transaction
> >>> + * @priv_xfers: do one or several private I3C SDR transfers
> >>> + * @i2c_xfers: do one or several I2C transfers
> >>> + * @request_ibi: attach an IBI handler to an I3C device. This implies defining
> >>> + *		 an IBI handler and the constraints of the IBI (maximum payload
> >>> + *		 length and number of pre-allocated slots).
> >>> + *		 Some controllers support less IBI-capable devices than regular
> >>> + *		 devices, so this method might return -%EBUSY if there's no
> >>> + *		 more space for an extra IBI registration
> >>> + * @free_ibi: free an IBI previously requested with ->request_ibi(). The IBI
> >>> + *	      should have been disabled with ->disable_irq() prior to that
> >>> + * @enable_ibi: enable the IBI. Only valid if ->request_ibi() has been called
> >>> + *		prior to ->enable_ibi(). The controller should first enable
> >>> + *		the IBI on the controller end (for example, unmask the hardware
> >>> + *		IRQ) and then send the ENEC CCC command (with the IBI flag set)
> >>> + *		to the I3C device
> >>> + * @disable_ibi: disable an IBI. First send the DISEC CCC command with the IBI
> >>> + *		 flag set and then deactivate the hardware IRQ on the
> >>> + *		 controller end
> >>> + * @recycle_ibi_slot: recycle an IBI slot. Called every time an IBI has been
> >>> + *		      processed by its handler. The IBI slot should be put back
> >>> + *		      in the IBI slot pool so that the controller can re-use it
> >>> + *		      for a future IBI
> >>> + *
> >>> + * One of the most important hooks in these ops is
> >>> + * &i3c_master_controller_ops->bus_init(). Here is a non-exhaustive list of
> >>> + * things that should be done in &i3c_master_controller_ops->bus_init():
> >>> + *
> >>> + * 1) call i3c_master_set_info() with all information describing the master
> >>> + * 2) ask all slaves to drop their dynamic address by sending the RSTDAA CCC
> >>> + *    with i3c_master_rstdaa_locked()
> >>> + * 3) ask all slaves to disable IBIs using i3c_master_disec_locked()
> >>> + * 4) start a DDA procedure by sending the ENTDAA CCC with
> >>> + *    i3c_master_entdaa_locked(), or using the internal DAA logic provided by
> >>> + *    your controller    
> >> You mean SETDASA CCC command?  
> > No, I really mean ENTDAA and DAA. By internal DAA logic I mean that
> > some controllers are probably automating the whole DAA procedure, while
> > others may let the SW control every step.  
> My understanding is that i3c_master_entdaa_locked() will trigger the DAA process
> and DAA can be done by SETDASA, ENTDAA and later after the bus initialization
> with SETNEWDA.

No. Only ENTDAA can trigger a DAA procedure. SETDASA is here to assign
a single dynamic address to a device that already has a static address
but no dynamic address yet, and SETNEWDA is here to modify the dynamic
address of a device that already has one.

> 
> I think the DAA process should be more generic, right now is only made through
> the ENTDAA command with (cmd.ndests = 1).
> I mean, shouldn't this be made by the core? First doing DAA for the devices
> declared and them try do discover the rest of devices on the bus.

Can you detail a bit more? If the only part you're complaining about is
pre-assignment of dynamic addresses with SETDASA when a device is
declared in the DT with a reg and dynamic-address property, then yes, I
think I can provide an helper for that. But this helper would still have
to be called from the master controller driver (from ->bus_init() or
after a Hot-Join).

Now, if the question is, is there a way we can automate things even more
and completely implement DAA from the core? I doubt it, because the way
the core will trigger DAA, expose discovered devices or allow you to
declare manually assigned addresses is likely to be
controller-dependent.
When I designed the framework I took the decision to base my work on the
spec rather than focusing on the I3C master controller I had to support
(Cadence). This is the reason I decided to keep the interface as simple
as possible at the risk of encouraging code-duplication (at first)
rather than coming up with an interface that is designed with a single
controller in mind and having to break things every time a new
controller comes out.

Thank you for you comments, but I'd like to know if some of my design
choices are blocking you to support your controller. What I've seen so
far is a collection of things that might be relevant to fix (though
most of them are subject to interpretation and/or a matter of taste),
but nothing that should really block you.

Can you clarify that, and maybe come back with a list of things that you
think are preventing you from properly supporting the Synopsys
controller?

Thanks,

Boris
Boris Brezillon Feb. 26, 2018, 8:40 p.m. UTC | #17 
On Mon, 26 Feb 2018 21:36:07 +0100
Boris Brezillon <boris.brezillon@bootlin.com> wrote:

> > >>> +
> > >>> +/**
> > >>> + * struct i3c_master_controller_ops - I3C master methods
> > >>> + * @bus_init: hook responsible for the I3C bus initialization. This
> > >>> + *	      initialization should follow the steps described in the I3C
> > >>> + *	      specification. This hook is called with the bus lock held in
> > >>> + *	      write mode, which means all _locked() helpers can safely be
> > >>> + *	      called from there
> > >>> + * @bus_cleanup: cleanup everything done in
> > >>> + *		 &i3c_master_controller_ops->bus_init(). This function is
> > >>> + *		 optional and should only be implemented if
> > >>> + *		 &i3c_master_controller_ops->bus_init() attached private data
> > >>> + *		 to I3C/I2C devices. This hook is called with the bus lock
> > >>> + *		 held in write mode, which means all _locked() helpers can
> > >>> + *		 safely be called from there
> > >>> + * @supports_ccc_cmd: should return true if the CCC command is supported, false
> > >>> + *		      otherwise
> > >>> + * @send_ccc_cmd: send a CCC command
> > >>> + * @send_hdr_cmds: send one or several HDR commands. If there is more than one
> > >>> + *		   command, they should ideally be sent in the same HDR
> > >>> + *		   transaction
> > >>> + * @priv_xfers: do one or several private I3C SDR transfers
> > >>> + * @i2c_xfers: do one or several I2C transfers
> > >>> + * @request_ibi: attach an IBI handler to an I3C device. This implies defining
> > >>> + *		 an IBI handler and the constraints of the IBI (maximum payload
> > >>> + *		 length and number of pre-allocated slots).
> > >>> + *		 Some controllers support less IBI-capable devices than regular
> > >>> + *		 devices, so this method might return -%EBUSY if there's no
> > >>> + *		 more space for an extra IBI registration
> > >>> + * @free_ibi: free an IBI previously requested with ->request_ibi(). The IBI
> > >>> + *	      should have been disabled with ->disable_irq() prior to that
> > >>> + * @enable_ibi: enable the IBI. Only valid if ->request_ibi() has been called
> > >>> + *		prior to ->enable_ibi(). The controller should first enable
> > >>> + *		the IBI on the controller end (for example, unmask the hardware
> > >>> + *		IRQ) and then send the ENEC CCC command (with the IBI flag set)
> > >>> + *		to the I3C device
> > >>> + * @disable_ibi: disable an IBI. First send the DISEC CCC command with the IBI
> > >>> + *		 flag set and then deactivate the hardware IRQ on the
> > >>> + *		 controller end
> > >>> + * @recycle_ibi_slot: recycle an IBI slot. Called every time an IBI has been
> > >>> + *		      processed by its handler. The IBI slot should be put back
> > >>> + *		      in the IBI slot pool so that the controller can re-use it
> > >>> + *		      for a future IBI
> > >>> + *
> > >>> + * One of the most important hooks in these ops is
> > >>> + * &i3c_master_controller_ops->bus_init(). Here is a non-exhaustive list of
> > >>> + * things that should be done in &i3c_master_controller_ops->bus_init():
> > >>> + *
> > >>> + * 1) call i3c_master_set_info() with all information describing the master
> > >>> + * 2) ask all slaves to drop their dynamic address by sending the RSTDAA CCC
> > >>> + *    with i3c_master_rstdaa_locked()
> > >>> + * 3) ask all slaves to disable IBIs using i3c_master_disec_locked()
> > >>> + * 4) start a DDA procedure by sending the ENTDAA CCC with
> > >>> + *    i3c_master_entdaa_locked(), or using the internal DAA logic provided by
> > >>> + *    your controller      
> > >> You mean SETDASA CCC command?    
> > > No, I really mean ENTDAA and DAA. By internal DAA logic I mean that
> > > some controllers are probably automating the whole DAA procedure, while
> > > others may let the SW control every step.    
> > My understanding is that i3c_master_entdaa_locked() will trigger the DAA process
> > and DAA can be done by SETDASA, ENTDAA and later after the bus initialization
> > with SETNEWDA.  
> 
> No. Only ENTDAA can trigger a DAA procedure. SETDASA is here to assign
> a single dynamic address to a device that already has a static address
> but no dynamic address yet, and SETNEWDA is here to modify the dynamic
> address of a device that already has one.
> 
> > 
> > I think the DAA process should be more generic, right now is only made through
> > the ENTDAA command with (cmd.ndests = 1).
> > I mean, shouldn't this be made by the core? First doing DAA for the devices
> > declared and them try do discover the rest of devices on the bus.  
> 
> Can you detail a bit more? If the only part you're complaining about is
> pre-assignment of dynamic addresses with SETDASA when a device is
> declared in the DT with a reg and dynamic-address property, then yes, I
> think I can provide an helper for that. But this helper would still have
> to be called from the master controller driver (from ->bus_init() or
> after a Hot-Join).
> 
> Now, if the question is, is there a way we can automate things even more
> and completely implement DAA from the core? I doubt it, because the way
> the core will trigger DAA, expose discovered devices or allow you to
> declare manually assigned addresses is likely to be
> controller-dependent.
> When I designed the framework I took the decision to base my work on the
> spec rather than focusing on the I3C master controller I had to support
> (Cadence). This is the reason I decided to keep the interface as simple
> as possible at the risk of encouraging code-duplication (at first)
> rather than coming up with an interface that is designed with a single
> controller in mind and having to break things every time a new
> controller comes out.
> 
> Thank you for you comments, but I'd like to know if some of my design
> choices are blocking you to support your controller. What I've seen so
> far is a collection of things that might be relevant to fix (though
> most of them are subject to interpretation and/or a matter of taste),
> but nothing that should really block you.

Well, that's not entirely true: I agree that something is missing in
->priv_xfers() to let the controller know about the device limitations,
and this could be a blocking aspect.
Boris Brezillon Feb. 26, 2018, 9:38 p.m. UTC | #18 
On Mon, 26 Feb 2018 21:40:32 +0100
Boris Brezillon <boris.brezillon@bootlin.com> wrote:

> On Mon, 26 Feb 2018 21:36:07 +0100
> Boris Brezillon <boris.brezillon@bootlin.com> wrote:
> 
> > > >>> +
> > > >>> +/**
> > > >>> + * struct i3c_master_controller_ops - I3C master methods
> > > >>> + * @bus_init: hook responsible for the I3C bus initialization. This
> > > >>> + *	      initialization should follow the steps described in the I3C
> > > >>> + *	      specification. This hook is called with the bus lock held in
> > > >>> + *	      write mode, which means all _locked() helpers can safely be
> > > >>> + *	      called from there
> > > >>> + * @bus_cleanup: cleanup everything done in
> > > >>> + *		 &i3c_master_controller_ops->bus_init(). This function is
> > > >>> + *		 optional and should only be implemented if
> > > >>> + *		 &i3c_master_controller_ops->bus_init() attached private data
> > > >>> + *		 to I3C/I2C devices. This hook is called with the bus lock
> > > >>> + *		 held in write mode, which means all _locked() helpers can
> > > >>> + *		 safely be called from there
> > > >>> + * @supports_ccc_cmd: should return true if the CCC command is supported, false
> > > >>> + *		      otherwise
> > > >>> + * @send_ccc_cmd: send a CCC command
> > > >>> + * @send_hdr_cmds: send one or several HDR commands. If there is more than one
> > > >>> + *		   command, they should ideally be sent in the same HDR
> > > >>> + *		   transaction
> > > >>> + * @priv_xfers: do one or several private I3C SDR transfers
> > > >>> + * @i2c_xfers: do one or several I2C transfers
> > > >>> + * @request_ibi: attach an IBI handler to an I3C device. This implies defining
> > > >>> + *		 an IBI handler and the constraints of the IBI (maximum payload
> > > >>> + *		 length and number of pre-allocated slots).
> > > >>> + *		 Some controllers support less IBI-capable devices than regular
> > > >>> + *		 devices, so this method might return -%EBUSY if there's no
> > > >>> + *		 more space for an extra IBI registration
> > > >>> + * @free_ibi: free an IBI previously requested with ->request_ibi(). The IBI
> > > >>> + *	      should have been disabled with ->disable_irq() prior to that
> > > >>> + * @enable_ibi: enable the IBI. Only valid if ->request_ibi() has been called
> > > >>> + *		prior to ->enable_ibi(). The controller should first enable
> > > >>> + *		the IBI on the controller end (for example, unmask the hardware
> > > >>> + *		IRQ) and then send the ENEC CCC command (with the IBI flag set)
> > > >>> + *		to the I3C device
> > > >>> + * @disable_ibi: disable an IBI. First send the DISEC CCC command with the IBI
> > > >>> + *		 flag set and then deactivate the hardware IRQ on the
> > > >>> + *		 controller end
> > > >>> + * @recycle_ibi_slot: recycle an IBI slot. Called every time an IBI has been
> > > >>> + *		      processed by its handler. The IBI slot should be put back
> > > >>> + *		      in the IBI slot pool so that the controller can re-use it
> > > >>> + *		      for a future IBI
> > > >>> + *
> > > >>> + * One of the most important hooks in these ops is
> > > >>> + * &i3c_master_controller_ops->bus_init(). Here is a non-exhaustive list of
> > > >>> + * things that should be done in &i3c_master_controller_ops->bus_init():
> > > >>> + *
> > > >>> + * 1) call i3c_master_set_info() with all information describing the master
> > > >>> + * 2) ask all slaves to drop their dynamic address by sending the RSTDAA CCC
> > > >>> + *    with i3c_master_rstdaa_locked()
> > > >>> + * 3) ask all slaves to disable IBIs using i3c_master_disec_locked()
> > > >>> + * 4) start a DDA procedure by sending the ENTDAA CCC with
> > > >>> + *    i3c_master_entdaa_locked(), or using the internal DAA logic provided by
> > > >>> + *    your controller        
> > > >> You mean SETDASA CCC command?      
> > > > No, I really mean ENTDAA and DAA. By internal DAA logic I mean that
> > > > some controllers are probably automating the whole DAA procedure, while
> > > > others may let the SW control every step.      
> > > My understanding is that i3c_master_entdaa_locked() will trigger the DAA process
> > > and DAA can be done by SETDASA, ENTDAA and later after the bus initialization
> > > with SETNEWDA.    
> > 
> > No. Only ENTDAA can trigger a DAA procedure. SETDASA is here to assign
> > a single dynamic address to a device that already has a static address
> > but no dynamic address yet, and SETNEWDA is here to modify the dynamic
> > address of a device that already has one.
> >   
> > > 
> > > I think the DAA process should be more generic, right now is only made through
> > > the ENTDAA command with (cmd.ndests = 1).
> > > I mean, shouldn't this be made by the core? First doing DAA for the devices
> > > declared and them try do discover the rest of devices on the bus.    
> > 
> > Can you detail a bit more? If the only part you're complaining about is
> > pre-assignment of dynamic addresses with SETDASA when a device is
> > declared in the DT with a reg and dynamic-address property, then yes, I
> > think I can provide an helper for that. But this helper would still have
> > to be called from the master controller driver (from ->bus_init() or
> > after a Hot-Join).
> > 
> > Now, if the question is, is there a way we can automate things even more
> > and completely implement DAA from the core? I doubt it, because the way
> > the core will trigger DAA, expose discovered devices or allow you to
> > declare manually assigned addresses is likely to be
> > controller-dependent.
> > When I designed the framework I took the decision to base my work on the
> > spec rather than focusing on the I3C master controller I had to support
> > (Cadence). This is the reason I decided to keep the interface as simple
> > as possible at the risk of encouraging code-duplication (at first)
> > rather than coming up with an interface that is designed with a single
> > controller in mind and having to break things every time a new
> > controller comes out.
> > 
> > Thank you for you comments, but I'd like to know if some of my design
> > choices are blocking you to support your controller. What I've seen so
> > far is a collection of things that might be relevant to fix (though
> > most of them are subject to interpretation and/or a matter of taste),
> > but nothing that should really block you.  
> 
> Well, that's not entirely true: I agree that something is missing in
> ->priv_xfers() to let the controller know about the device limitations,  
> and this could be a blocking aspect.
> 

And I2C functionalities might differ between I3C master controllers, so
that's also something we should transfer to the I3C master driver
instead of imposing it in the core.
Vitor Soares Feb. 27, 2018, 4:03 p.m. UTC | #19 
Hi Boris


Às 8:36 PM de 2/26/2018, Boris Brezillon escreveu:
> Hi Vitor,
>
> On Mon, 26 Feb 2018 18:58:15 +0000
> Vitor Soares <Vitor.Soares@synopsys.com> wrote:
>
>>>>> +/**
>>>>> + * i3c_device_do_priv_xfers() - do I3C SDR private transfers directed to a
>>>>> + *				specific device
>>>>> + *
>>>>> + * @dev: device with which the transfers should be done
>>>>> + * @xfers: array of transfers
>>>>> + * @nxfers: number of transfers
>>>>> + *
>>>>> + * Initiate one or several private SDR transfers with @dev.
>>>>> + *
>>>>> + * This function can sleep and thus cannot be called in atomic context.
>>>>> + *
>>>>> + * Return: 0 in case of success, a negative error core otherwise.
>>>>> + */
>>>>> +int i3c_device_do_priv_xfers(struct i3c_device *dev,
>>>>> +			     struct i3c_priv_xfer *xfers,
>>>>> +			     int nxfers)
>>>>> +{
>>>>> +	struct i3c_master_controller *master;
>>>>> +	int i, ret;
>>>>> +
>>>>> +	master = i3c_device_get_master(dev);
>>>>> +	if (!master)
>>>>> +		return -EINVAL;
>>>>> +
>>>>> +	i3c_bus_normaluse_lock(master->bus);
>>>>> +	for (i = 0; i < nxfers; i++)
>>>>> +		xfers[i].addr = dev->info.dyn_addr;
>>>>> +
>>>>> +	ret = i3c_master_do_priv_xfers_locked(master, xfers, nxfers);
>>>>> +	i3c_bus_normaluse_unlock(master->bus);
>>>>> +
>>>>> +	return ret;
>>>>> +}
>>>>> +EXPORT_SYMBOL_GPL(i3c_device_do_priv_xfers);    
>>>>  The controller should know the speed mode for each xfer. The SDR0 mode 
>>>> is used by default but if any device have read or write speed 
>>>> limitations the controller can use SDRx.  
>>> I might be wrong, but that's not my understanding of the spec. A device
>>> can express a speed limitation for SDR priv transfers, but this
>>> limitation applies to all SDR transfers.
>>>
>>> The speed R/W speed limitation is encoded in the device object, so, if
>>> the controller has to configure that on a per-transfer basis, one
>>> solution would be to pass the device to the ->priv_xfers().  
>> The speed R/W limitation is only for private transfers. Also the device can have
>> a limitation to write and not for read data.
>> This information is obtained with the command GETMXDS which returns the Maximum
>> Sustained Data Rate for non-CCC messages.
> And that's exactly what I expose in i3c_device_info, which is embedded
> in i3c_device, so you should have all the information you need to
> determine the speed in the controller driver if ->priv_xfer() is passed
> the device attached to those transfers. Would that be okay if we pass an
> i3c_device object to ->priv_xfers()?

If you pass the i3c_device to ->priv_xfer(), then you won't need the address too.

Maybe someone else can give other point of view.

>>>  
>>>> This could be also applied to i2c transfers.  
>>> Not really. The max SCL frequency is something that applies to the
>>> whole bus, because all I2C devices have to decode the address when
>>> messages are sent on the bus to determine if they should ignore or
>>> process the message.
>>>  
>>>>> +#endif /* I3C_INTERNAL_H */
>>>>> diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c
>>>>> new file mode 100644
>>>>> index 000000000000..1c85abac08d5
>>>>> --- /dev/null
>>>>> +++ b/drivers/i3c/master.c
>>>>> @@ -0,0 +1,1433 @@
>>>>> +// SPDX-License-Identifier: GPL-2.0
>>>>> +/*
>>>>> + * Copyright (C) 2017 Cadence Design Systems Inc.
>>>>> + *
>>>>> + * Author: Boris Brezillon<boris.brezillon@free-electrons.com>
>>>>> + */
>>>>> +
>>>>> +#include <linux/slab.h>
>>>>> +
>>>>> +#include "internals.h"
>>>>> +
>>>>> +/**
>>>>> + * i3c_master_entdaa_locked() - start a DAA (Dynamic Address Assignment)
>>>>> + *				procedure
>>>>> + * @master: master used to send frames on the bus
>>>>> + *
>>>>> + * Send a ENTDAA CCC command to start a DAA procedure.
>>>>> + *
>>>>> + * Note that this function only sends the ENTDAA CCC command, all the logic
>>>>> + * behind dynamic address assignment has to be handled in the I3C master
>>>>> + * driver.
>>>>> + *
>>>>> + * This function must be called with the bus lock held in write mode.
>>>>> + *
>>>>> + * Return: 0 in case of success, a negative error code otherwise.
>>>>> + */
>>>>> +int i3c_master_entdaa_locked(struct i3c_master_controller *master)
>>>>> +{
>>>>> +	struct i3c_ccc_cmd_dest dest = { };
>>>>> +	struct i3c_ccc_cmd cmd = { };
>>>>> +	int ret;
>>>>> +
>>>>> +	dest.addr = I3C_BROADCAST_ADDR;
>>>>> +	cmd.dests = &dest;
>>>>> +	cmd.ndests = 1;
>>>>> +	cmd.rnw = false;
>>>>> +	cmd.id = I3C_CCC_ENTDAA;
>>>>> +
>>>>> +	ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
>>>>> +	if (ret)
>>>>> +		return ret;
>>>>> +
>>>>> +	return 0;
>>>>> +}
>>>>> +EXPORT_SYMBOL_GPL(i3c_master_entdaa_locked);    
>>>>  can you explain the process?  
>>> Not sure what you mean. The ENTDAA is just a CCC command that is used
>>> to trigger a DAA procedure. What the master controller does when it
>>> sends such a command is likely to be controller dependent, and it might
>>> even be possible that you don't need to call this function in your
>>> controller driver to trigger a DAA. If you want more details about the
>>> bus initialization steps and how the ENTDAA CCC command fits into it I
>>> recommend reading section "5.1.4 Bus Initialization and Dynamic Address
>>> Assignment Mode"
>>>  
>>>> the command is only execute once, what if 
>>>> there is more devices on the bus?  
>>> Again, I'm not sure what you mean. The ENTDAA command is sent every
>>> time a controller wants to discover new devices on the bus, that can be
>>> when initializing the bus, after a Hot Join event or simply triggered
>>> by the user (the last case is not supported yet though).
>>>
>>> Now, if you're interested in what happens after an ENTDAA CCC is sent,
>>> the controller will keep sending RepeatedStart until there's no more
>>> devices acking the request. You can have a look at "B.3 Error Types in
>>> Dynamic Address Arbitration" for more details.  
>> My understanding is this command shall be executed once, this mean that only one
>> slave will assign the dynamic address (cmd.ndests = 1) and not trigger the whole
>> process of DAA.
> No, that's not what happens. The master controller is supposed to
> continue until no one replies with an Ack on the bus, and by continue I
> don't mean resend an ENTDAA, but issue a RepeatedStart followed by the
> broadcast address (0x7e).

I am sorry, you have point here. I misunderstood that the cmd.ndests = 1 is for
broadcast commands.

>> Either important is the SETDASA for declared I3C devices. So the DAA process
>> should start by send an SETDASA and them ENTDAA CCC command.
> My understanding was that SETDASA was not mandatory, and was only useful
> when one wants to assign a specific dynamic address to a slave that has
> a static address (which is again not mandatory).
> I've tested it, and even devices with a static address participate to
> the DAA procedure if they've not been assigned a dynamic address yet,
> so I don't see the need for this SETDASA step if you don't need to
> assign a particular dynamic address to the device.
>
> Could you tell me why you think SETDASA is required?

Yes, you are right... But in my opinion it is required as it does part of DAA
process.

>>>>> +static u32 i3c_master_i2c_functionalities(struct i2c_adapter *adap)
>>>>> +{
>>>>> +	return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR;
>>>>> +}    
>>>>  Is I2C_FUNC_10BIT_ADDR allowed ?  
>>> According to "Table 4 I 2 C Features Allowed in I3C Slaves", yes (at
>>> least that my understanding). And the Cadence controller supports it.  
>> The table say the oposite. The I2C extended address feature is not used on I3C
>> bus, thus this feature shall be disable.
> Actually, I was wrong when initially mentioning this table: it's about
> I2C features supported on I3C slaves, so not really what we're looking
> for. Here, we're wondering if I2C-only devices can have 10-bit
> addresses. The Cadence controller supports that, so there's probably
> nothing preventing use of 10-bit addresses for I2C transfers, but maybe
> not all I3C master controllers support that, so we should probably
> let the I3C master driver implement this method.

The spec says that is "not used" so it will not interface with I3C bus.

>> BTW it is optional on I2C devices.
> You mean I2C controllers? When an I2C device has a 10bit address, the
> controller has to support this mode to communicate with the device, at
> least that's my understanding. But we're digressing a bit. The
> question is not whether I2C devices can optionally use a 10 bit
> address, but whether I3C master controller can support this mode for
> I2C transfers to I2C-only devices.

By the i2c spec the 10-bit address is optional, however the 7-bit address is
mandatory.

>>>  
>>>>  > diff --git a/drivers/i3c/master/Kconfig b/drivers/i3c/master/Kconfig
>>>>> new file mode 100644
>>>>> index 000000000000..e69de29bb2d1
>>>>> diff --git a/drivers/i3c/master/Makefile b/drivers/i3c/master/Makefile
>>>>> new file mode 100644
>>>>> index 000000000000..e69de29bb2d1
>>>>> diff --git a/include/linux/i3c/ccc.h b/include/linux/i3c/ccc.h
>>>>> new file mode 100644
>>>>> index 000000000000..ff3e1a3e2c4c
>>>>> --- /dev/null
>>>>> +++ b/include/linux/i3c/ccc.h
>>>>> @@ -0,0 +1,380 @@
>>>>> +/* SPDX-License-Identifier: GPL-2.0 */
>>>>> +/*
>>>>> + * Copyright (C) 2017 Cadence Design Systems Inc.
>>>>> + *
>>>>> + * Author: Boris Brezillon<boris.brezillon@free-electrons.com>
>>>>> + */
>>>>> +
>>>>> +
>>>>> +/**
>>>>> + * enum i3c_ccc_test_mode - enum listing all available test modes
>>>>> + *
>>>>> + * @I3C_CCC_EXIT_TEST_MODE: exit test mode
>>>>> + * @I3C_CCC_VENDOR_TEST_MODE: enter vendor test mode
>>>>> + */
>>>>> +enum i3c_ccc_test_mode {
>>>>> +	I3C_CCC_EXIT_TEST_MODE,
>>>>> +	I3C_CCC_VENDOR_TEST_MODE,
>>>>> +};
>>>>> +
>>>>> +/**
>>>>> + * struct i3c_ccc_enttm - payload passed to ENTTM CCC
>>>>> + *
>>>>> + * @mode: one of the &enum i3c_ccc_test_mode modes
>>>>> + *
>>>>> + * Information passed to the ENTTM CCC to instruct an I3C device to enter a
>>>>> + * specific test mode.
>>>>> + */
>>>>> +struct i3c_ccc_enttm {
>>>>> +	u8 mode;
>>>>> +} __packed;
>>>>> +
>>>>> +/**
>>>>> + * struct i3c_ccc_setda - payload passed to ENTTM CCC
>>>>> + *
>>>>> + * @mode: one of the &enum i3c_ccc_test_mode modes
>>>>> + *
>>>>> + * Information passed to the ENTTM CCC to instruct an I3C device to enter a
>>>>> + * specific test mode.
>>>>> + */
>>>>> +struct i3c_ccc_setda {
>>>>> +	u8 addr;
>>>>> +} __packed;    
>>>>  what do you mean with struct? Maybe setdasa? if so, what is the addr?  
>> Do you have the function to use this structure? Because one command use the
>> static address and the other use the dynamic address.
>>
>>>>  
>>>>  > +/**
>>>>> + * enum i3c_sdr_max_data_rate - max data rate values for private SDR transfers
>>>>> + */
>>>>> +enum i3c_sdr_max_data_rate {
>>>>> +	I3C_SDR_DR_FSCL_MAX,
>>>>> +	I3C_SDR_DR_FSCL_8MHZ,
>>>>> +	I3C_SDR_DR_FSCL_6MHZ,
>>>>> +	I3C_SDR_DR_FSCL_4MHZ,
>>>>> +	I3C_SDR_DR_FSCL_2MHZ,
>>>>> +};    
>>>> Can you change the names to:
>>>>
>>>> I3C_SDR0_FSCL_MAX,
>>>> I3C_SDR1_FSCL_8MHZ,
>>>> I3C_SDR2_FSCL_6MHZ,
>>>> I3C_SDR3_FSCL_4MHZ,
>>>> I3C_SDR4_FSCL_2MHZ,
>>>>
>>>> thus the data rate isn't repeated.  
>>> What's the problem with the name I use? Moreover, I see no mention to
>>> the SDR0,1,2,3,4 modes in the public spec.  
>> When you get the GETMXDS information, the maxWr and maxRd came from 0 to 4, so
>> in my opinion I think in this way is easier to have a relationship.
> It's an emum, and there's no mention of the SDRX modes you're using
> here in the I3C spec. I guess it's named this way in your I3C
> controller datasheet. I personally don't see a good reason to add SDRX
> in the name, but if you insist...

The idea is to say that it is SDR mode and the value that GETMXDS command
return. It is what makes sense to me.

>>>>> +
>>>>> +#endif /* I3C_CCC_H */
>>>>> diff --git a/include/linux/i3c/device.h b/include/linux/i3c/device.h
>>>>> new file mode 100644
>>>>> index 000000000000..83958d3a02e2
>>>>> --- /dev/null
>>>>> +++ b/include/linux/i3c/device.h
>>>>> @@ -0,0 +1,321 @@
>>>>> +/* SPDX-License-Identifier: GPL-2.0 */
>>>>> +/*
>>>>> + * Copyright (C) 2017 Cadence Design Systems Inc.
>>>>> + *
>>>>> + * Author: Boris Brezillon<boris.brezillon@free-electrons.com>
>>>>> + */
>>>>> +
>>>>> +#ifndef I3C_DEV_H
>>>>> +#define I3C_DEV_H
>>>>> +
>>>>> +#include <linux/device.h>
>>>>> +#include <linux/i2c.h>
>>>>> +#include <linux/mod_devicetable.h>
>>>>> +#include <linux/module.h>
>>>>> +
>>>>> +/**
>>>>> + * enum i3c_hdr_mode - HDR mode ids
>>>>> + * @I3C_HDR_DDR: DDR mode
>>>>> + * @I3C_HDR_TSP: TSP mode
>>>>> + * @I3C_HDR_TSL: TSL mode
>>>>> + */
>>>>> +enum i3c_hdr_mode {
>>>>> +	I3C_HDR_DDR,
>>>>> +	I3C_HDR_TSP,
>>>>> +	I3C_HDR_TSL,
>>>>> +};
>>>>> +
>>>>> +/**
>>>>> + * struct i3c_hdr_cmd - I3C HDR command
>>>>> + * @mode: HDR mode selected for this command
>>>>> + * @code: command opcode
>>>>> + * @addr: I3C dynamic address
>>>>> + * @ndatawords: number of data words (a word is 16bits wide)
>>>>> + * @data: input/output buffer
>>>>> + */
>>>>> +struct i3c_hdr_cmd {
>>>>> +	enum i3c_hdr_mode mode;
>>>>> +	u8 code;
>>>>> +	u8 addr;
>>>>> +	int ndatawords;
>>>>> +	union {
>>>>> +		u16 *in;
>>>>> +		const u16 *out;
>>>>> +	} data;
>>>>> +};  
>> Please mention that the @code is what will define if the transfer is read or write.
> Well, I think it's pretty clear in the definition you'll find in the
> ccc.h file, but I can add a comment here too if you like.

I don't find it in ccc.h file. Anyway is not good to put this definition there
because is not related.

>>>>> +
>>>>> +/* Private SDR read transfer */
>>>>> +#define I3C_PRIV_XFER_READ		BIT(0)
>>>>> +/*
>>>>> + * Instruct the controller to issue a STOP after a specific transfer instead
>>>>> + * of a REPEATED START.
>>>>> + */
>>>>> +#define I3C_PRIV_XFER_STOP		BIT(1)
>>>>> +
>>>>> +/**
>>>>> + * struct i3c_priv_xfer - I3C SDR private transfer
>>>>> + * @addr: I3C dynamic address
>>>>> + * @len: transfer length in bytes of the transfer
>>>>> + * @flags: combination of I3C_PRIV_XFER_xxx flags
>>>>> + * @data: input/output buffer
>>>>> + */
>>>>> +struct i3c_priv_xfer {
>>>>> +	u8 addr;
>>>>> +	u16 len;
>>>>> +	u32 flags;
>>>>> +	struct {
>>>>> +		void *in;
>>>>> +		const void *out;
>>>>> +	} data;
>>>>> +};    
>>>>  Same as above, i3c_sdr_max_data_rate to change the bus scl.  
>>> If I'm understanding the spec correctly, that's not something you want
>>> to change on a per-transfer basis. The constraint is on the device
>>> itself and should IMO not be part of the i3c_priv_xfer struct.  
>> As mention before this is important.
>> You can do the same as for struct i3c_hdr_cmd and add a enum i3c_sdr_max_data_rate.
>>
>> The @flag only have 2 bits of load, is the rest opened?
> If by open you mean that we can add more flags if we need to, then yes.
>
>>>  
>>>>  > +
>>>>> +/**
>>>>> + * enum i3c_dcr - I3C DCR values
>>>>> + * @I3C_DCR_GENERIC_DEVICE: generic I3C device
>>>>> + */
>>>>> +enum i3c_dcr {
>>>>> +	I3C_DCR_GENERIC_DEVICE = 0,
>>>>> +};
>>>>> +
>>>>> +#define I3C_PID_MANUF_ID(pid)		(((pid) & GENMASK_ULL(47, 33)) >> 33)
>>>>> +#define I3C_PID_RND_LOWER_32BITS(pid)	(!!((pid) & BIT_ULL(32)))
>>>>> +#define I3C_PID_RND_VAL(pid)		((pid) & GENMASK_ULL(31, 0))
>>>>> +#define I3C_PID_PART_ID(pid)		(((pid) & GENMASK_ULL(31, 16)) >> 16)
>>>>> +#define I3C_PID_INSTANCE_ID(pid)	(((pid) & GENMASK_ULL(15, 12)) >> 12)
>>>>> +#define I3C_PID_EXTRA_INFO(pid)		((pid) & GENMASK_ULL(11, 0))
>>>>> +
>>>>> +#define I3C_BCR_DEVICE_ROLE(bcr)	((bcr) & GENMASK(7, 6))
>>>>> +#define I3C_BCR_I3C_SLAVE		(0 << 6)
>>>>> +#define I3C_BCR_I3C_MASTER		(1 << 6)
>>>>> +#define I3C_BCR_HDR_CAP			BIT(5)
>>>>> +#define I3C_BCR_BRIDGE			BIT(4)
>>>>> +#define I3C_BCR_OFFLINE_CAP		BIT(3)
>>>>> +#define I3C_BCR_IBI_PAYLOAD		BIT(2)
>>>>> +#define I3C_BCR_IBI_REQ_CAP		BIT(1)
>>>>> +#define I3C_BCR_MAX_DATA_SPEED_LIM	BIT(0)
>>>>> +
>>>>> +/**
>>>>> + * struct i3c_device_info - I3C device information
>>>>> + * @pid: Provisional ID
>>>>> + * @bcr: Bus Characteristic Register
>>>>> + * @dcr: Device Characteristic Register
>>>>> + * @static_addr: static/I2C address
>>>>> + * @dyn_addr: dynamic address
>>>>> + * @hdr_cap: supported HDR modes
>>>>> + * @max_read_ds: max read speed information
>>>>> + * @max_write_ds: max write speed information
>>>>> + * @max_ibi_len: max IBI payload length
>>>>> + * @max_read_turnaround: max read turn-around time in micro-seconds
>>>>> + * @max_read_len: max private SDR read length in bytes
>>>>> + * @max_write_len: max private SDR write length in bytes
>>>>> + *
>>>>> + * These are all basic information that should be advertised by an I3C device.
>>>>> + * Some of them are optional depending on the device type and device
>>>>> + * capabilities.
>>>>> + * For each I3C slave attached to a master with
>>>>> + * i3c_master_add_i3c_dev_locked(), the core will send the relevant CCC command
>>>>> + * to retrieve these data.
>>>>> + */
>>>>> +struct i3c_device_info {
>>>>> +	u64 pid;
>>>>> +	u8 bcr;
>>>>> +	u8 dcr;
>>>>> +	u8 static_addr;
>>>>> +	u8 dyn_addr;
>>>>> +	u8 hdr_cap;
>>>>> +	u8 max_read_ds;
>>>>> +	u8 max_write_ds;
>>>>> +	u8 max_ibi_len;
>>>>> +	u32 max_read_turnaround;
>>>>> +	u16 max_read_len;
>>>>> +	u16 max_write_len;
>>>>> +};
>>>>> +    
>>>>  is this information filled with data provided from CCC commands?  
>>> Yes, they are.  
>> Ok, them the intention is to do this on bus_init(), right?
> Not only, it can be after a Hot-Join, or after the user has triggered a
> new DAA. Anyway, these information are retrieved anytime you add a
> device with i3c_master_add_i3c_dev_locked(), and the core uses CCC
> commands to do that.
>
>>>>> +
>>>>> +/**
>>>>> + * struct i3c_master_controller_ops - I3C master methods
>>>>> + * @bus_init: hook responsible for the I3C bus initialization. This
>>>>> + *	      initialization should follow the steps described in the I3C
>>>>> + *	      specification. This hook is called with the bus lock held in
>>>>> + *	      write mode, which means all _locked() helpers can safely be
>>>>> + *	      called from there
>>>>> + * @bus_cleanup: cleanup everything done in
>>>>> + *		 &i3c_master_controller_ops->bus_init(). This function is
>>>>> + *		 optional and should only be implemented if
>>>>> + *		 &i3c_master_controller_ops->bus_init() attached private data
>>>>> + *		 to I3C/I2C devices. This hook is called with the bus lock
>>>>> + *		 held in write mode, which means all _locked() helpers can
>>>>> + *		 safely be called from there
>>>>> + * @supports_ccc_cmd: should return true if the CCC command is supported, false
>>>>> + *		      otherwise
>>>>> + * @send_ccc_cmd: send a CCC command
>>>>> + * @send_hdr_cmds: send one or several HDR commands. If there is more than one
>>>>> + *		   command, they should ideally be sent in the same HDR
>>>>> + *		   transaction
>>>>> + * @priv_xfers: do one or several private I3C SDR transfers
>>>>> + * @i2c_xfers: do one or several I2C transfers
>>>>> + * @request_ibi: attach an IBI handler to an I3C device. This implies defining
>>>>> + *		 an IBI handler and the constraints of the IBI (maximum payload
>>>>> + *		 length and number of pre-allocated slots).
>>>>> + *		 Some controllers support less IBI-capable devices than regular
>>>>> + *		 devices, so this method might return -%EBUSY if there's no
>>>>> + *		 more space for an extra IBI registration
>>>>> + * @free_ibi: free an IBI previously requested with ->request_ibi(). The IBI
>>>>> + *	      should have been disabled with ->disable_irq() prior to that
>>>>> + * @enable_ibi: enable the IBI. Only valid if ->request_ibi() has been called
>>>>> + *		prior to ->enable_ibi(). The controller should first enable
>>>>> + *		the IBI on the controller end (for example, unmask the hardware
>>>>> + *		IRQ) and then send the ENEC CCC command (with the IBI flag set)
>>>>> + *		to the I3C device
>>>>> + * @disable_ibi: disable an IBI. First send the DISEC CCC command with the IBI
>>>>> + *		 flag set and then deactivate the hardware IRQ on the
>>>>> + *		 controller end
>>>>> + * @recycle_ibi_slot: recycle an IBI slot. Called every time an IBI has been
>>>>> + *		      processed by its handler. The IBI slot should be put back
>>>>> + *		      in the IBI slot pool so that the controller can re-use it
>>>>> + *		      for a future IBI
>>>>> + *
>>>>> + * One of the most important hooks in these ops is
>>>>> + * &i3c_master_controller_ops->bus_init(). Here is a non-exhaustive list of
>>>>> + * things that should be done in &i3c_master_controller_ops->bus_init():
>>>>> + *
>>>>> + * 1) call i3c_master_set_info() with all information describing the master
>>>>> + * 2) ask all slaves to drop their dynamic address by sending the RSTDAA CCC
>>>>> + *    with i3c_master_rstdaa_locked()
>>>>> + * 3) ask all slaves to disable IBIs using i3c_master_disec_locked()
>>>>> + * 4) start a DDA procedure by sending the ENTDAA CCC with
>>>>> + *    i3c_master_entdaa_locked(), or using the internal DAA logic provided by
>>>>> + *    your controller    
>>>> You mean SETDASA CCC command?  
>>> No, I really mean ENTDAA and DAA. By internal DAA logic I mean that
>>> some controllers are probably automating the whole DAA procedure, while
>>> others may let the SW control every step.  
>> My understanding is that i3c_master_entdaa_locked() will trigger the DAA process
>> and DAA can be done by SETDASA, ENTDAA and later after the bus initialization
>> with SETNEWDA.
> No. Only ENTDAA can trigger a DAA procedure. SETDASA is here to assign
> a single dynamic address to a device that already has a static address
> but no dynamic address yet, and SETNEWDA is here to modify the dynamic
> address of a device that already has one.

>> I think the DAA process should be more generic, right now is only made through
>> the ENTDAA command with (cmd.ndests = 1).
>> I mean, shouldn't this be made by the core? First doing DAA for the devices
>> declared and them try do discover the rest of devices on the bus.
> Can you detail a bit more? If the only part you're complaining about is
> pre-assignment of dynamic addresses with SETDASA when a device is
> declared in the DT with a reg and dynamic-address property, then yes, I
> think I can provide an helper for that. But this helper would still have
> to be called from the master controller driver (from ->bus_init() or
> after a Hot-Join).
>
> Now, if the question is, is there a way we can automate things even more
> and completely implement DAA from the core? I doubt it, because the way
> the core will trigger DAA, expose discovered devices or allow you to
> declare manually assigned addresses is likely to be
> controller-dependent.

Please refer to figure 90 of public specification. As you can see the DAA
process should start with SETDASA command.

With the current flow of this patch the DAA process is limited to ENTDAA command
only.

> When I designed the framework I took the decision to base my work on the
> spec rather than focusing on the I3C master controller I had to support
> (Cadence). This is the reason I decided to keep the interface as simple
> as possible at the risk of encouraging code-duplication (at first)
> rather than coming up with an interface that is designed with a single
> controller in mind and having to break things every time a new
> controller comes out.
>
> Thank you for you comments, but I'd like to know if some of my design
> choices are blocking you to support your controller. What I've seen so
> far is a collection of things that might be relevant to fix (though
> most of them are subject to interpretation and/or a matter of taste),
> but nothing that should really block you.
>
> Can you clarify that, and maybe come back with a list of things that you
> think are preventing you from properly supporting the Synopsys
> controller?
>
> Thanks,
>
> Boris 

As you can check from my  comments my concerns are about the i3c specification
without the controller in mind.

Best regards,
Vitor Soares
Przemyslaw Sroka Feb. 27, 2018, 4:43 p.m. UTC | #20 
Hi Boris and Vitor

Find below my comment on DAA procedure.

> -----Original Message-----

> From: Vitor Soares [mailto:Vitor.Soares@synopsys.com]

> Sent: Tuesday, February 27, 2018 5:04 PM

> To: Boris Brezillon <boris.brezillon@bootlin.com>; Vitor Soares

> <Vitor.Soares@synopsys.com>

> Cc: Boris Brezillon <boris.brezillon@free-electrons.com>; Wolfram Sang

> <wsa@the-dreams.de>; linux-i2c@vger.kernel.org; Jonathan Corbet

> <corbet@lwn.net>; linux-doc@vger.kernel.org; Greg Kroah-Hartman

> <gregkh@linuxfoundation.org>; Arnd Bergmann <arnd@arndb.de>;

> Przemyslaw Sroka <psroka@cadence.com>; Arkadiusz Golec

> <agolec@cadence.com>; Alan Douglas <adouglas@cadence.com>; Bartosz

> Folta <bfolta@cadence.com>; Damian Kos <dkos@cadence.com>; Alicja

> Jurasik-Urbaniak <alicja@cadence.com>; Cyprian Wronka

> <cwronka@cadence.com>; Suresh Punnoose <sureshp@cadence.com>;

> Thomas Petazzoni <thomas.petazzoni@free-electrons.com>; Nishanth

> Menon <nm@ti.com>; Rob Herring <robh+dt@kernel.org>; Pawel Moll

> <pawel.moll@arm.com>; Mark Rutland <mark.rutland@arm.com>; Ian

> Campbell <ijc+devicetree@hellion.org.uk>; Kumar Gala

> <galak@codeaurora.org>; devicetree@vger.kernel.org; linux-

> kernel@vger.kernel.org; Geert Uytterhoeven <geert@linux-m68k.org>; Linus

> Walleij <linus.walleij@linaro.org>

> Subject: Re: [PATCH v2 2/7] i3c: Add core I3C infrastructure

> 

> EXTERNAL MAIL

> 

> 

> Hi Boris

> 

> 

> Às 8:36 PM de 2/26/2018, Boris Brezillon escreveu:

> > Hi Vitor,

> >

> > On Mon, 26 Feb 2018 18:58:15 +0000

> > Vitor Soares <Vitor.Soares@synopsys.com> wrote:

> >

> >>>>> +/**

> >>>>> + * i3c_device_do_priv_xfers() - do I3C SDR private transfers directed

> to a

> >>>>> + *				specific device

> >>>>> + *

> >>>>> + * @dev: device with which the transfers should be done

> >>>>> + * @xfers: array of transfers

> >>>>> + * @nxfers: number of transfers

> >>>>> + *

> >>>>> + * Initiate one or several private SDR transfers with @dev.

> >>>>> + *

> >>>>> + * This function can sleep and thus cannot be called in atomic

> context.

> >>>>> + *

> >>>>> + * Return: 0 in case of success, a negative error core otherwise.

> >>>>> + */

> >>>>> +int i3c_device_do_priv_xfers(struct i3c_device *dev,

> >>>>> +			     struct i3c_priv_xfer *xfers,

> >>>>> +			     int nxfers)

> >>>>> +{

> >>>>> +	struct i3c_master_controller *master;

> >>>>> +	int i, ret;

> >>>>> +

> >>>>> +	master = i3c_device_get_master(dev);

> >>>>> +	if (!master)

> >>>>> +		return -EINVAL;

> >>>>> +

> >>>>> +	i3c_bus_normaluse_lock(master->bus);

> >>>>> +	for (i = 0; i < nxfers; i++)

> >>>>> +		xfers[i].addr = dev->info.dyn_addr;

> >>>>> +

> >>>>> +	ret = i3c_master_do_priv_xfers_locked(master, xfers,

> nxfers);

> >>>>> +	i3c_bus_normaluse_unlock(master->bus);

> >>>>> +

> >>>>> +	return ret;

> >>>>> +}

> >>>>> +EXPORT_SYMBOL_GPL(i3c_device_do_priv_xfers);

> >>>>  The controller should know the speed mode for each xfer. The SDR0

> >>>> mode is used by default but if any device have read or write speed

> >>>> limitations the controller can use SDRx.

> >>> I might be wrong, but that's not my understanding of the spec. A

> >>> device can express a speed limitation for SDR priv transfers, but

> >>> this limitation applies to all SDR transfers.

> >>>

> >>> The speed R/W speed limitation is encoded in the device object, so,

> >>> if the controller has to configure that on a per-transfer basis, one

> >>> solution would be to pass the device to the ->priv_xfers().

> >> The speed R/W limitation is only for private transfers. Also the

> >> device can have a limitation to write and not for read data.

> >> This information is obtained with the command GETMXDS which returns

> >> the Maximum Sustained Data Rate for non-CCC messages.

> > And that's exactly what I expose in i3c_device_info, which is embedded

> > in i3c_device, so you should have all the information you need to

> > determine the speed in the controller driver if ->priv_xfer() is

> > passed the device attached to those transfers. Would that be okay if

> > we pass an i3c_device object to ->priv_xfers()?

> 

> If you pass the i3c_device to ->priv_xfer(), then you won't need the address

> too.

> 

> Maybe someone else can give other point of view.

> 

> >>>

> >>>> This could be also applied to i2c transfers.

> >>> Not really. The max SCL frequency is something that applies to the

> >>> whole bus, because all I2C devices have to decode the address when

> >>> messages are sent on the bus to determine if they should ignore or

> >>> process the message.

> >>>

> >>>>> +#endif /* I3C_INTERNAL_H */

> >>>>> diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c new file

> >>>>> mode 100644 index 000000000000..1c85abac08d5

> >>>>> --- /dev/null

> >>>>> +++ b/drivers/i3c/master.c

> >>>>> @@ -0,0 +1,1433 @@

> >>>>> +// SPDX-License-Identifier: GPL-2.0

> >>>>> +/*

> >>>>> + * Copyright (C) 2017 Cadence Design Systems Inc.

> >>>>> + *

> >>>>> + * Author: Boris Brezillon<boris.brezillon@free-electrons.com>

> >>>>> + */

> >>>>> +

> >>>>> +#include <linux/slab.h>

> >>>>> +

> >>>>> +#include "internals.h"

> >>>>> +

> >>>>> +/**

> >>>>> + * i3c_master_entdaa_locked() - start a DAA (Dynamic Address

> Assignment)

> >>>>> + *				procedure

> >>>>> + * @master: master used to send frames on the bus

> >>>>> + *

> >>>>> + * Send a ENTDAA CCC command to start a DAA procedure.

> >>>>> + *

> >>>>> + * Note that this function only sends the ENTDAA CCC command, all

> >>>>> +the logic

> >>>>> + * behind dynamic address assignment has to be handled in the I3C

> >>>>> +master

> >>>>> + * driver.

> >>>>> + *

> >>>>> + * This function must be called with the bus lock held in write

> mode.

> >>>>> + *

> >>>>> + * Return: 0 in case of success, a negative error code otherwise.

> >>>>> + */

> >>>>> +int i3c_master_entdaa_locked(struct i3c_master_controller

> >>>>> +*master) {

> >>>>> +	struct i3c_ccc_cmd_dest dest = { };

> >>>>> +	struct i3c_ccc_cmd cmd = { };

> >>>>> +	int ret;

> >>>>> +

> >>>>> +	dest.addr = I3C_BROADCAST_ADDR;

> >>>>> +	cmd.dests = &dest;

> >>>>> +	cmd.ndests = 1;

> >>>>> +	cmd.rnw = false;

> >>>>> +	cmd.id = I3C_CCC_ENTDAA;

> >>>>> +

> >>>>> +	ret = i3c_master_send_ccc_cmd_locked(master, &cmd);

> >>>>> +	if (ret)

> >>>>> +		return ret;

> >>>>> +

> >>>>> +	return 0;

> >>>>> +}

> >>>>> +EXPORT_SYMBOL_GPL(i3c_master_entdaa_locked);

> >>>>  can you explain the process?

> >>> Not sure what you mean. The ENTDAA is just a CCC command that is

> >>> used to trigger a DAA procedure. What the master controller does

> >>> when it sends such a command is likely to be controller dependent,

> >>> and it might even be possible that you don't need to call this

> >>> function in your controller driver to trigger a DAA. If you want

> >>> more details about the bus initialization steps and how the ENTDAA

> >>> CCC command fits into it I recommend reading section "5.1.4 Bus

> >>> Initialization and Dynamic Address Assignment Mode"

> >>>

> >>>> the command is only execute once, what if there is more devices on

> >>>> the bus?

> >>> Again, I'm not sure what you mean. The ENTDAA command is sent

> every

> >>> time a controller wants to discover new devices on the bus, that can

> >>> be when initializing the bus, after a Hot Join event or simply

> >>> triggered by the user (the last case is not supported yet though).

> >>>

> >>> Now, if you're interested in what happens after an ENTDAA CCC is

> >>> sent, the controller will keep sending RepeatedStart until there's

> >>> no more devices acking the request. You can have a look at "B.3

> >>> Error Types in Dynamic Address Arbitration" for more details.

> >> My understanding is this command shall be executed once, this mean

> >> that only one slave will assign the dynamic address (cmd.ndests = 1)

> >> and not trigger the whole process of DAA.

> > No, that's not what happens. The master controller is supposed to

> > continue until no one replies with an Ack on the bus, and by continue

> > I don't mean resend an ENTDAA, but issue a RepeatedStart followed by

> > the broadcast address (0x7e).

> 

> I am sorry, you have point here. I misunderstood that the cmd.ndests = 1 is

> for broadcast commands.

> 

> >> Either important is the SETDASA for declared I3C devices. So the DAA

> >> process should start by send an SETDASA and them ENTDAA CCC

> command.

> > My understanding was that SETDASA was not mandatory, and was only

> > useful when one wants to assign a specific dynamic address to a slave

> > that has a static address (which is again not mandatory).

> > I've tested it, and even devices with a static address participate to

> > the DAA procedure if they've not been assigned a dynamic address yet,

> > so I don't see the need for this SETDASA step if you don't need to

> > assign a particular dynamic address to the device.

> >

> > Could you tell me why you think SETDASA is required?

> 

> Yes, you are right... But in my opinion it is required as it does part of DAA

> process.


SETDASA is simply faster than ENTDAA, but only if there is no need to
collect BCR/DCR/PID of such devices. I think most applications would
like to have them as an status information so  after all ENTDAA can 
be regarded as an generic approach (unless I'm mistaken).

> 

> >>>>> +static u32 i3c_master_i2c_functionalities(struct i2c_adapter

> >>>>> +*adap) {

> >>>>> +	return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_I2C |

> I2C_FUNC_10BIT_ADDR;

> >>>>> +}

> >>>>  Is I2C_FUNC_10BIT_ADDR allowed ?

> >>> According to "Table 4 I 2 C Features Allowed in I3C Slaves", yes (at

> >>> least that my understanding). And the Cadence controller supports it.

> >> The table say the oposite. The I2C extended address feature is not

> >> used on I3C bus, thus this feature shall be disable.

> > Actually, I was wrong when initially mentioning this table: it's about

> > I2C features supported on I3C slaves, so not really what we're looking

> > for. Here, we're wondering if I2C-only devices can have 10-bit

> > addresses. The Cadence controller supports that, so there's probably

> > nothing preventing use of 10-bit addresses for I2C transfers, but

> > maybe not all I3C master controllers support that, so we should

> > probably let the I3C master driver implement this method.

> 

> The spec says that is "not used" so it will not interface with I3C bus.

> 

> >> BTW it is optional on I2C devices.

> > You mean I2C controllers? When an I2C device has a 10bit address, the

> > controller has to support this mode to communicate with the device, at

> > least that's my understanding. But we're digressing a bit. The

> > question is not whether I2C devices can optionally use a 10 bit

> > address, but whether I3C master controller can support this mode for

> > I2C transfers to I2C-only devices.

> 

> By the i2c spec the 10-bit address is optional, however the 7-bit address is

> mandatory.

> 

> >>>

> >>>>  > diff --git a/drivers/i3c/master/Kconfig

> >>>> b/drivers/i3c/master/Kconfig

> >>>>> new file mode 100644

> >>>>> index 000000000000..e69de29bb2d1

> >>>>> diff --git a/drivers/i3c/master/Makefile

> >>>>> b/drivers/i3c/master/Makefile new file mode 100644 index

> >>>>> 000000000000..e69de29bb2d1 diff --git a/include/linux/i3c/ccc.h

> >>>>> b/include/linux/i3c/ccc.h new file mode 100644 index

> >>>>> 000000000000..ff3e1a3e2c4c

> >>>>> --- /dev/null

> >>>>> +++ b/include/linux/i3c/ccc.h

> >>>>> @@ -0,0 +1,380 @@

> >>>>> +/* SPDX-License-Identifier: GPL-2.0 */

> >>>>> +/*

> >>>>> + * Copyright (C) 2017 Cadence Design Systems Inc.

> >>>>> + *

> >>>>> + * Author: Boris Brezillon<boris.brezillon@free-electrons.com>

> >>>>> + */

> >>>>> +

> >>>>> +

> >>>>> +/**

> >>>>> + * enum i3c_ccc_test_mode - enum listing all available test modes

> >>>>> + *

> >>>>> + * @I3C_CCC_EXIT_TEST_MODE: exit test mode

> >>>>> + * @I3C_CCC_VENDOR_TEST_MODE: enter vendor test mode  */

> enum

> >>>>> +i3c_ccc_test_mode {

> >>>>> +	I3C_CCC_EXIT_TEST_MODE,

> >>>>> +	I3C_CCC_VENDOR_TEST_MODE,

> >>>>> +};

> >>>>> +

> >>>>> +/**

> >>>>> + * struct i3c_ccc_enttm - payload passed to ENTTM CCC

> >>>>> + *

> >>>>> + * @mode: one of the &enum i3c_ccc_test_mode modes

> >>>>> + *

> >>>>> + * Information passed to the ENTTM CCC to instruct an I3C device

> >>>>> +to enter a

> >>>>> + * specific test mode.

> >>>>> + */

> >>>>> +struct i3c_ccc_enttm {

> >>>>> +	u8 mode;

> >>>>> +} __packed;

> >>>>> +

> >>>>> +/**

> >>>>> + * struct i3c_ccc_setda - payload passed to ENTTM CCC

> >>>>> + *

> >>>>> + * @mode: one of the &enum i3c_ccc_test_mode modes

> >>>>> + *

> >>>>> + * Information passed to the ENTTM CCC to instruct an I3C device

> >>>>> +to enter a

> >>>>> + * specific test mode.

> >>>>> + */

> >>>>> +struct i3c_ccc_setda {

> >>>>> +	u8 addr;

> >>>>> +} __packed;

> >>>>  what do you mean with struct? Maybe setdasa? if so, what is the

> addr?

> >> Do you have the function to use this structure? Because one command

> >> use the static address and the other use the dynamic address.

> >>

> >>>>

> >>>>  > +/**

> >>>>> + * enum i3c_sdr_max_data_rate - max data rate values for private

> >>>>> +SDR transfers  */ enum i3c_sdr_max_data_rate {

> >>>>> +	I3C_SDR_DR_FSCL_MAX,

> >>>>> +	I3C_SDR_DR_FSCL_8MHZ,

> >>>>> +	I3C_SDR_DR_FSCL_6MHZ,

> >>>>> +	I3C_SDR_DR_FSCL_4MHZ,

> >>>>> +	I3C_SDR_DR_FSCL_2MHZ,

> >>>>> +};

> >>>> Can you change the names to:

> >>>>

> >>>> I3C_SDR0_FSCL_MAX,

> >>>> I3C_SDR1_FSCL_8MHZ,

> >>>> I3C_SDR2_FSCL_6MHZ,

> >>>> I3C_SDR3_FSCL_4MHZ,

> >>>> I3C_SDR4_FSCL_2MHZ,

> >>>>

> >>>> thus the data rate isn't repeated.

> >>> What's the problem with the name I use? Moreover, I see no mention

> >>> to the SDR0,1,2,3,4 modes in the public spec.

> >> When you get the GETMXDS information, the maxWr and maxRd came

> from 0

> >> to 4, so in my opinion I think in this way is easier to have a relationship.

> > It's an emum, and there's no mention of the SDRX modes you're using

> > here in the I3C spec. I guess it's named this way in your I3C

> > controller datasheet. I personally don't see a good reason to add SDRX

> > in the name, but if you insist...

> 

> The idea is to say that it is SDR mode and the value that GETMXDS

> command return. It is what makes sense to me.

> 

> >>>>> +

> >>>>> +#endif /* I3C_CCC_H */

> >>>>> diff --git a/include/linux/i3c/device.h

> >>>>> b/include/linux/i3c/device.h new file mode 100644 index

> >>>>> 000000000000..83958d3a02e2

> >>>>> --- /dev/null

> >>>>> +++ b/include/linux/i3c/device.h

> >>>>> @@ -0,0 +1,321 @@

> >>>>> +/* SPDX-License-Identifier: GPL-2.0 */

> >>>>> +/*

> >>>>> + * Copyright (C) 2017 Cadence Design Systems Inc.

> >>>>> + *

> >>>>> + * Author: Boris Brezillon<boris.brezillon@free-electrons.com>

> >>>>> + */

> >>>>> +

> >>>>> +#ifndef I3C_DEV_H

> >>>>> +#define I3C_DEV_H

> >>>>> +

> >>>>> +#include <linux/device.h>

> >>>>> +#include <linux/i2c.h>

> >>>>> +#include <linux/mod_devicetable.h> #include <linux/module.h>

> >>>>> +

> >>>>> +/**

> >>>>> + * enum i3c_hdr_mode - HDR mode ids

> >>>>> + * @I3C_HDR_DDR: DDR mode

> >>>>> + * @I3C_HDR_TSP: TSP mode

> >>>>> + * @I3C_HDR_TSL: TSL mode

> >>>>> + */

> >>>>> +enum i3c_hdr_mode {

> >>>>> +	I3C_HDR_DDR,

> >>>>> +	I3C_HDR_TSP,

> >>>>> +	I3C_HDR_TSL,

> >>>>> +};

> >>>>> +

> >>>>> +/**

> >>>>> + * struct i3c_hdr_cmd - I3C HDR command

> >>>>> + * @mode: HDR mode selected for this command

> >>>>> + * @code: command opcode

> >>>>> + * @addr: I3C dynamic address

> >>>>> + * @ndatawords: number of data words (a word is 16bits wide)

> >>>>> + * @data: input/output buffer

> >>>>> + */

> >>>>> +struct i3c_hdr_cmd {

> >>>>> +	enum i3c_hdr_mode mode;

> >>>>> +	u8 code;

> >>>>> +	u8 addr;

> >>>>> +	int ndatawords;

> >>>>> +	union {

> >>>>> +		u16 *in;

> >>>>> +		const u16 *out;

> >>>>> +	} data;

> >>>>> +};

> >> Please mention that the @code is what will define if the transfer is read

> or write.

> > Well, I think it's pretty clear in the definition you'll find in the

> > ccc.h file, but I can add a comment here too if you like.

> 

> I don't find it in ccc.h file. Anyway is not good to put this definition there

> because is not related.

> 

> >>>>> +

> >>>>> +/* Private SDR read transfer */

> >>>>> +#define I3C_PRIV_XFER_READ		BIT(0)

> >>>>> +/*

> >>>>> + * Instruct the controller to issue a STOP after a specific

> >>>>> +transfer instead

> >>>>> + * of a REPEATED START.

> >>>>> + */

> >>>>> +#define I3C_PRIV_XFER_STOP		BIT(1)

> >>>>> +

> >>>>> +/**

> >>>>> + * struct i3c_priv_xfer - I3C SDR private transfer

> >>>>> + * @addr: I3C dynamic address

> >>>>> + * @len: transfer length in bytes of the transfer

> >>>>> + * @flags: combination of I3C_PRIV_XFER_xxx flags

> >>>>> + * @data: input/output buffer

> >>>>> + */

> >>>>> +struct i3c_priv_xfer {

> >>>>> +	u8 addr;

> >>>>> +	u16 len;

> >>>>> +	u32 flags;

> >>>>> +	struct {

> >>>>> +		void *in;

> >>>>> +		const void *out;

> >>>>> +	} data;

> >>>>> +};

> >>>>  Same as above, i3c_sdr_max_data_rate to change the bus scl.

> >>> If I'm understanding the spec correctly, that's not something you

> >>> want to change on a per-transfer basis. The constraint is on the

> >>> device itself and should IMO not be part of the i3c_priv_xfer struct.

> >> As mention before this is important.

> >> You can do the same as for struct i3c_hdr_cmd and add a enum

> i3c_sdr_max_data_rate.

> >>

> >> The @flag only have 2 bits of load, is the rest opened?

> > If by open you mean that we can add more flags if we need to, then yes.

> >

> >>>

> >>>>  > +

> >>>>> +/**

> >>>>> + * enum i3c_dcr - I3C DCR values

> >>>>> + * @I3C_DCR_GENERIC_DEVICE: generic I3C device  */ enum i3c_dcr

> {

> >>>>> +	I3C_DCR_GENERIC_DEVICE = 0,

> >>>>> +};

> >>>>> +

> >>>>> +#define I3C_PID_MANUF_ID(pid)		(((pid) &

> GENMASK_ULL(47, 33)) >> 33)

> >>>>> +#define I3C_PID_RND_LOWER_32BITS(pid)	(!!((pid) &

> BIT_ULL(32)))

> >>>>> +#define I3C_PID_RND_VAL(pid)		((pid) & GENMASK_ULL(31,

> 0))

> >>>>> +#define I3C_PID_PART_ID(pid)		(((pid) & GENMASK_ULL(31,

> 16)) >> 16)

> >>>>> +#define I3C_PID_INSTANCE_ID(pid)	(((pid) & GENMASK_ULL(15,

> 12)) >> 12)

> >>>>> +#define I3C_PID_EXTRA_INFO(pid)		((pid) &

> GENMASK_ULL(11, 0))

> >>>>> +

> >>>>> +#define I3C_BCR_DEVICE_ROLE(bcr)	((bcr) & GENMASK(7, 6))

> >>>>> +#define I3C_BCR_I3C_SLAVE		(0 << 6)

> >>>>> +#define I3C_BCR_I3C_MASTER		(1 << 6)

> >>>>> +#define I3C_BCR_HDR_CAP			BIT(5)

> >>>>> +#define I3C_BCR_BRIDGE			BIT(4)

> >>>>> +#define I3C_BCR_OFFLINE_CAP		BIT(3)

> >>>>> +#define I3C_BCR_IBI_PAYLOAD		BIT(2)

> >>>>> +#define I3C_BCR_IBI_REQ_CAP		BIT(1)

> >>>>> +#define I3C_BCR_MAX_DATA_SPEED_LIM	BIT(0)

> >>>>> +

> >>>>> +/**

> >>>>> + * struct i3c_device_info - I3C device information

> >>>>> + * @pid: Provisional ID

> >>>>> + * @bcr: Bus Characteristic Register

> >>>>> + * @dcr: Device Characteristic Register

> >>>>> + * @static_addr: static/I2C address

> >>>>> + * @dyn_addr: dynamic address

> >>>>> + * @hdr_cap: supported HDR modes

> >>>>> + * @max_read_ds: max read speed information

> >>>>> + * @max_write_ds: max write speed information

> >>>>> + * @max_ibi_len: max IBI payload length

> >>>>> + * @max_read_turnaround: max read turn-around time in

> >>>>> +micro-seconds

> >>>>> + * @max_read_len: max private SDR read length in bytes

> >>>>> + * @max_write_len: max private SDR write length in bytes

> >>>>> + *

> >>>>> + * These are all basic information that should be advertised by an

> I3C device.

> >>>>> + * Some of them are optional depending on the device type and

> >>>>> +device

> >>>>> + * capabilities.

> >>>>> + * For each I3C slave attached to a master with

> >>>>> + * i3c_master_add_i3c_dev_locked(), the core will send the

> >>>>> +relevant CCC command

> >>>>> + * to retrieve these data.

> >>>>> + */

> >>>>> +struct i3c_device_info {

> >>>>> +	u64 pid;

> >>>>> +	u8 bcr;

> >>>>> +	u8 dcr;

> >>>>> +	u8 static_addr;

> >>>>> +	u8 dyn_addr;

> >>>>> +	u8 hdr_cap;

> >>>>> +	u8 max_read_ds;

> >>>>> +	u8 max_write_ds;

> >>>>> +	u8 max_ibi_len;

> >>>>> +	u32 max_read_turnaround;

> >>>>> +	u16 max_read_len;

> >>>>> +	u16 max_write_len;

> >>>>> +};

> >>>>> +

> >>>>  is this information filled with data provided from CCC commands?

> >>> Yes, they are.

> >> Ok, them the intention is to do this on bus_init(), right?

> > Not only, it can be after a Hot-Join, or after the user has triggered

> > a new DAA. Anyway, these information are retrieved anytime you add a

> > device with i3c_master_add_i3c_dev_locked(), and the core uses CCC

> > commands to do that.

> >

> >>>>> +

> >>>>> +/**

> >>>>> + * struct i3c_master_controller_ops - I3C master methods

> >>>>> + * @bus_init: hook responsible for the I3C bus initialization. This

> >>>>> + *	      initialization should follow the steps described in the I3C

> >>>>> + *	      specification. This hook is called with the bus lock held

> in

> >>>>> + *	      write mode, which means all _locked() helpers can safely

> be

> >>>>> + *	      called from there

> >>>>> + * @bus_cleanup: cleanup everything done in

> >>>>> + *		 &i3c_master_controller_ops->bus_init(). This

> function is

> >>>>> + *		 optional and should only be implemented if

> >>>>> + *		 &i3c_master_controller_ops->bus_init() attached

> private data

> >>>>> + *		 to I3C/I2C devices. This hook is called with the bus

> lock

> >>>>> + *		 held in write mode, which means all _locked()

> helpers can

> >>>>> + *		 safely be called from there

> >>>>> + * @supports_ccc_cmd: should return true if the CCC command is

> supported, false

> >>>>> + *		      otherwise

> >>>>> + * @send_ccc_cmd: send a CCC command

> >>>>> + * @send_hdr_cmds: send one or several HDR commands. If there is

> more than one

> >>>>> + *		   command, they should ideally be sent in the same

> HDR

> >>>>> + *		   transaction

> >>>>> + * @priv_xfers: do one or several private I3C SDR transfers

> >>>>> + * @i2c_xfers: do one or several I2C transfers

> >>>>> + * @request_ibi: attach an IBI handler to an I3C device. This implies

> defining

> >>>>> + *		 an IBI handler and the constraints of the IBI

> (maximum payload

> >>>>> + *		 length and number of pre-allocated slots).

> >>>>> + *		 Some controllers support less IBI-capable devices

> than regular

> >>>>> + *		 devices, so this method might return -%EBUSY if

> there's no

> >>>>> + *		 more space for an extra IBI registration

> >>>>> + * @free_ibi: free an IBI previously requested with ->request_ibi().

> The IBI

> >>>>> + *	      should have been disabled with ->disable_irq() prior to

> that

> >>>>> + * @enable_ibi: enable the IBI. Only valid if ->request_ibi() has been

> called

> >>>>> + *		prior to ->enable_ibi(). The controller should first

> enable

> >>>>> + *		the IBI on the controller end (for example, unmask

> the hardware

> >>>>> + *		IRQ) and then send the ENEC CCC command (with

> the IBI flag set)

> >>>>> + *		to the I3C device

> >>>>> + * @disable_ibi: disable an IBI. First send the DISEC CCC command

> with the IBI

> >>>>> + *		 flag set and then deactivate the hardware IRQ on

> the

> >>>>> + *		 controller end

> >>>>> + * @recycle_ibi_slot: recycle an IBI slot. Called every time an IBI has

> been

> >>>>> + *		      processed by its handler. The IBI slot should be

> put back

> >>>>> + *		      in the IBI slot pool so that the controller can re-

> use it

> >>>>> + *		      for a future IBI

> >>>>> + *

> >>>>> + * One of the most important hooks in these ops is

> >>>>> + * &i3c_master_controller_ops->bus_init(). Here is a

> >>>>> +non-exhaustive list of

> >>>>> + * things that should be done in &i3c_master_controller_ops-

> >bus_init():

> >>>>> + *

> >>>>> + * 1) call i3c_master_set_info() with all information describing

> >>>>> +the master

> >>>>> + * 2) ask all slaves to drop their dynamic address by sending the

> RSTDAA CCC

> >>>>> + *    with i3c_master_rstdaa_locked()

> >>>>> + * 3) ask all slaves to disable IBIs using

> >>>>> +i3c_master_disec_locked()

> >>>>> + * 4) start a DDA procedure by sending the ENTDAA CCC with

> >>>>> + *    i3c_master_entdaa_locked(), or using the internal DAA logic

> provided by

> >>>>> + *    your controller

> >>>> You mean SETDASA CCC command?

> >>> No, I really mean ENTDAA and DAA. By internal DAA logic I mean that

> >>> some controllers are probably automating the whole DAA procedure,

> >>> while others may let the SW control every step.

> >> My understanding is that i3c_master_entdaa_locked() will trigger the

> >> DAA process and DAA can be done by SETDASA, ENTDAA and later after

> >> the bus initialization with SETNEWDA.

> > No. Only ENTDAA can trigger a DAA procedure. SETDASA is here to assign

> > a single dynamic address to a device that already has a static address

> > but no dynamic address yet, and SETNEWDA is here to modify the

> dynamic

> > address of a device that already has one.

> 

> >> I think the DAA process should be more generic, right now is only

> >> made through the ENTDAA command with (cmd.ndests = 1).

> >> I mean, shouldn't this be made by the core? First doing DAA for the

> >> devices declared and them try do discover the rest of devices on the bus.

> > Can you detail a bit more? If the only part you're complaining about

> > is pre-assignment of dynamic addresses with SETDASA when a device is

> > declared in the DT with a reg and dynamic-address property, then yes,

> > I think I can provide an helper for that. But this helper would still

> > have to be called from the master controller driver (from ->bus_init()

> > or after a Hot-Join).

> >

> > Now, if the question is, is there a way we can automate things even

> > more and completely implement DAA from the core? I doubt it, because

> > the way the core will trigger DAA, expose discovered devices or allow

> > you to declare manually assigned addresses is likely to be

> > controller-dependent.

> 

> Please refer to figure 90 of public specification. As you can see the DAA

> process should start with SETDASA command.

> 

> With the current flow of this patch the DAA process is limited to ENTDAA

> command only.

> 

> > When I designed the framework I took the decision to base my work on

> > the spec rather than focusing on the I3C master controller I had to

> > support (Cadence). This is the reason I decided to keep the interface

> > as simple as possible at the risk of encouraging code-duplication (at

> > first) rather than coming up with an interface that is designed with a

> > single controller in mind and having to break things every time a new

> > controller comes out.

> >

> > Thank you for you comments, but I'd like to know if some of my design

> > choices are blocking you to support your controller. What I've seen so

> > far is a collection of things that might be relevant to fix (though

> > most of them are subject to interpretation and/or a matter of taste),

> > but nothing that should really block you.

> >

> > Can you clarify that, and maybe come back with a list of things that

> > you think are preventing you from properly supporting the Synopsys

> > controller?

> >

> > Thanks,

> >

> > Boris

> 

> As you can check from my  comments my concerns are about the i3c

> specification without the controller in mind.

> 

> Best regards,

> Vitor Soares

>
Przemyslaw Sroka Feb. 27, 2018, 5:06 p.m. UTC | #21 
More detailed explanation...

> -----Original Message-----

> From: Przemyslaw Sroka

> Sent: Tuesday, February 27, 2018 5:43 PM

> To: 'Vitor Soares' <Vitor.Soares@synopsys.com>; Boris Brezillon

> <boris.brezillon@bootlin.com>

> Cc: Boris Brezillon <boris.brezillon@free-electrons.com>; Wolfram Sang

> <wsa@the-dreams.de>; linux-i2c@vger.kernel.org; Jonathan Corbet

> <corbet@lwn.net>; linux-doc@vger.kernel.org; Greg Kroah-Hartman

> <gregkh@linuxfoundation.org>; Arnd Bergmann <arnd@arndb.de>;

> Arkadiusz Golec <agolec@cadence.com>; Alan Douglas

> <adouglas@cadence.com>; Bartosz Folta <bfolta@cadence.com>; Damian

> Kos <dkos@cadence.com>; Alicja Jurasik-Urbaniak <alicja@cadence.com>;

> Cyprian Wronka <cwronka@cadence.com>; Suresh Punnoose

> <sureshp@cadence.com>; Thomas Petazzoni <thomas.petazzoni@free-

> electrons.com>; Nishanth Menon <nm@ti.com>; Rob Herring

> <robh+dt@kernel.org>; Pawel Moll <pawel.moll@arm.com>; Mark Rutland

> <mark.rutland@arm.com>; Ian Campbell <ijc+devicetree@hellion.org.uk>;

> Kumar Gala <galak@codeaurora.org>; devicetree@vger.kernel.org; linux-

> kernel@vger.kernel.org; Geert Uytterhoeven <geert@linux-m68k.org>; Linus

> Walleij <linus.walleij@linaro.org>

> Subject: RE: [PATCH v2 2/7] i3c: Add core I3C infrastructure

> 

> Hi Boris and Vitor

> 

> Find below my comment on DAA procedure.

> 

> > -----Original Message-----

> > From: Vitor Soares [mailto:Vitor.Soares@synopsys.com]

> > Sent: Tuesday, February 27, 2018 5:04 PM

> > To: Boris Brezillon <boris.brezillon@bootlin.com>; Vitor Soares

> > <Vitor.Soares@synopsys.com>

> > Cc: Boris Brezillon <boris.brezillon@free-electrons.com>; Wolfram Sang

> > <wsa@the-dreams.de>; linux-i2c@vger.kernel.org; Jonathan Corbet

> > <corbet@lwn.net>; linux-doc@vger.kernel.org; Greg Kroah-Hartman

> > <gregkh@linuxfoundation.org>; Arnd Bergmann <arnd@arndb.de>;

> > Przemyslaw Sroka <psroka@cadence.com>; Arkadiusz Golec

> > <agolec@cadence.com>; Alan Douglas <adouglas@cadence.com>; Bartosz

> > Folta <bfolta@cadence.com>; Damian Kos <dkos@cadence.com>; Alicja

> > Jurasik-Urbaniak <alicja@cadence.com>; Cyprian Wronka

> > <cwronka@cadence.com>; Suresh Punnoose <sureshp@cadence.com>;

> Thomas

> > Petazzoni <thomas.petazzoni@free-electrons.com>; Nishanth Menon

> > <nm@ti.com>; Rob Herring <robh+dt@kernel.org>; Pawel Moll

> > <pawel.moll@arm.com>; Mark Rutland <mark.rutland@arm.com>; Ian

> > Campbell <ijc+devicetree@hellion.org.uk>; Kumar Gala

> > <galak@codeaurora.org>; devicetree@vger.kernel.org; linux-

> > kernel@vger.kernel.org; Geert Uytterhoeven <geert@linux-m68k.org>;

> > Linus Walleij <linus.walleij@linaro.org>

> > Subject: Re: [PATCH v2 2/7] i3c: Add core I3C infrastructure

> >

> > EXTERNAL MAIL

> >

> >

> > Hi Boris

> >

> >

> > Às 8:36 PM de 2/26/2018, Boris Brezillon escreveu:

> > > Hi Vitor,

> > >

> > > On Mon, 26 Feb 2018 18:58:15 +0000

> > > Vitor Soares <Vitor.Soares@synopsys.com> wrote:

> > >

> > >>>>> +/**

> > >>>>> + * i3c_device_do_priv_xfers() - do I3C SDR private transfers

> > >>>>> +directed

> > to a

> > >>>>> + *				specific device

> > >>>>> + *

> > >>>>> + * @dev: device with which the transfers should be done

> > >>>>> + * @xfers: array of transfers

> > >>>>> + * @nxfers: number of transfers

> > >>>>> + *

> > >>>>> + * Initiate one or several private SDR transfers with @dev.

> > >>>>> + *

> > >>>>> + * This function can sleep and thus cannot be called in atomic

> > context.

> > >>>>> + *

> > >>>>> + * Return: 0 in case of success, a negative error core otherwise.

> > >>>>> + */

> > >>>>> +int i3c_device_do_priv_xfers(struct i3c_device *dev,

> > >>>>> +			     struct i3c_priv_xfer *xfers,

> > >>>>> +			     int nxfers)

> > >>>>> +{

> > >>>>> +	struct i3c_master_controller *master;

> > >>>>> +	int i, ret;

> > >>>>> +

> > >>>>> +	master = i3c_device_get_master(dev);

> > >>>>> +	if (!master)

> > >>>>> +		return -EINVAL;

> > >>>>> +

> > >>>>> +	i3c_bus_normaluse_lock(master->bus);

> > >>>>> +	for (i = 0; i < nxfers; i++)

> > >>>>> +		xfers[i].addr = dev->info.dyn_addr;

> > >>>>> +

> > >>>>> +	ret = i3c_master_do_priv_xfers_locked(master, xfers,

> > nxfers);

> > >>>>> +	i3c_bus_normaluse_unlock(master->bus);

> > >>>>> +

> > >>>>> +	return ret;

> > >>>>> +}

> > >>>>> +EXPORT_SYMBOL_GPL(i3c_device_do_priv_xfers);

> > >>>>  The controller should know the speed mode for each xfer. The

> > >>>> SDR0 mode is used by default but if any device have read or write

> > >>>> speed limitations the controller can use SDRx.

> > >>> I might be wrong, but that's not my understanding of the spec. A

> > >>> device can express a speed limitation for SDR priv transfers, but

> > >>> this limitation applies to all SDR transfers.

> > >>>

> > >>> The speed R/W speed limitation is encoded in the device object,

> > >>> so, if the controller has to configure that on a per-transfer

> > >>> basis, one solution would be to pass the device to the ->priv_xfers().

> > >> The speed R/W limitation is only for private transfers. Also the

> > >> device can have a limitation to write and not for read data.

> > >> This information is obtained with the command GETMXDS which

> returns

> > >> the Maximum Sustained Data Rate for non-CCC messages.

> > > And that's exactly what I expose in i3c_device_info, which is

> > > embedded in i3c_device, so you should have all the information you

> > > need to determine the speed in the controller driver if

> > > ->priv_xfer() is passed the device attached to those transfers.

> > > Would that be okay if we pass an i3c_device object to ->priv_xfers()?

> >

> > If you pass the i3c_device to ->priv_xfer(), then you won't need the

> > address too.

> >

> > Maybe someone else can give other point of view.

> >

> > >>>

> > >>>> This could be also applied to i2c transfers.

> > >>> Not really. The max SCL frequency is something that applies to the

> > >>> whole bus, because all I2C devices have to decode the address when

> > >>> messages are sent on the bus to determine if they should ignore or

> > >>> process the message.

> > >>>

> > >>>>> +#endif /* I3C_INTERNAL_H */

> > >>>>> diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c new

> > >>>>> file mode 100644 index 000000000000..1c85abac08d5

> > >>>>> --- /dev/null

> > >>>>> +++ b/drivers/i3c/master.c

> > >>>>> @@ -0,0 +1,1433 @@

> > >>>>> +// SPDX-License-Identifier: GPL-2.0

> > >>>>> +/*

> > >>>>> + * Copyright (C) 2017 Cadence Design Systems Inc.

> > >>>>> + *

> > >>>>> + * Author: Boris Brezillon<boris.brezillon@free-electrons.com>

> > >>>>> + */

> > >>>>> +

> > >>>>> +#include <linux/slab.h>

> > >>>>> +

> > >>>>> +#include "internals.h"

> > >>>>> +

> > >>>>> +/**

> > >>>>> + * i3c_master_entdaa_locked() - start a DAA (Dynamic Address

> > Assignment)

> > >>>>> + *				procedure

> > >>>>> + * @master: master used to send frames on the bus

> > >>>>> + *

> > >>>>> + * Send a ENTDAA CCC command to start a DAA procedure.

> > >>>>> + *

> > >>>>> + * Note that this function only sends the ENTDAA CCC command,

> > >>>>> +all the logic

> > >>>>> + * behind dynamic address assignment has to be handled in the

> > >>>>> +I3C master

> > >>>>> + * driver.

> > >>>>> + *

> > >>>>> + * This function must be called with the bus lock held in write

> > mode.

> > >>>>> + *

> > >>>>> + * Return: 0 in case of success, a negative error code otherwise.

> > >>>>> + */

> > >>>>> +int i3c_master_entdaa_locked(struct i3c_master_controller

> > >>>>> +*master) {

> > >>>>> +	struct i3c_ccc_cmd_dest dest = { };

> > >>>>> +	struct i3c_ccc_cmd cmd = { };

> > >>>>> +	int ret;

> > >>>>> +

> > >>>>> +	dest.addr = I3C_BROADCAST_ADDR;

> > >>>>> +	cmd.dests = &dest;

> > >>>>> +	cmd.ndests = 1;

> > >>>>> +	cmd.rnw = false;

> > >>>>> +	cmd.id = I3C_CCC_ENTDAA;

> > >>>>> +

> > >>>>> +	ret = i3c_master_send_ccc_cmd_locked(master, &cmd);

> > >>>>> +	if (ret)

> > >>>>> +		return ret;

> > >>>>> +

> > >>>>> +	return 0;

> > >>>>> +}

> > >>>>> +EXPORT_SYMBOL_GPL(i3c_master_entdaa_locked);

> > >>>>  can you explain the process?

> > >>> Not sure what you mean. The ENTDAA is just a CCC command that is

> > >>> used to trigger a DAA procedure. What the master controller does

> > >>> when it sends such a command is likely to be controller dependent,

> > >>> and it might even be possible that you don't need to call this

> > >>> function in your controller driver to trigger a DAA. If you want

> > >>> more details about the bus initialization steps and how the ENTDAA

> > >>> CCC command fits into it I recommend reading section "5.1.4 Bus

> > >>> Initialization and Dynamic Address Assignment Mode"

> > >>>

> > >>>> the command is only execute once, what if there is more devices

> > >>>> on the bus?

> > >>> Again, I'm not sure what you mean. The ENTDAA command is sent

> > every

> > >>> time a controller wants to discover new devices on the bus, that

> > >>> can be when initializing the bus, after a Hot Join event or simply

> > >>> triggered by the user (the last case is not supported yet though).

> > >>>

> > >>> Now, if you're interested in what happens after an ENTDAA CCC is

> > >>> sent, the controller will keep sending RepeatedStart until there's

> > >>> no more devices acking the request. You can have a look at "B.3

> > >>> Error Types in Dynamic Address Arbitration" for more details.

> > >> My understanding is this command shall be executed once, this mean

> > >> that only one slave will assign the dynamic address (cmd.ndests =

> > >> 1) and not trigger the whole process of DAA.

> > > No, that's not what happens. The master controller is supposed to

> > > continue until no one replies with an Ack on the bus, and by

> > > continue I don't mean resend an ENTDAA, but issue a RepeatedStart

> > > followed by the broadcast address (0x7e).

> >

> > I am sorry, you have point here. I misunderstood that the cmd.ndests =

> > 1 is for broadcast commands.

> >

> > >> Either important is the SETDASA for declared I3C devices. So the

> > >> DAA process should start by send an SETDASA and them ENTDAA CCC

> > command.

> > > My understanding was that SETDASA was not mandatory, and was only

> > > useful when one wants to assign a specific dynamic address to a

> > > slave that has a static address (which is again not mandatory).

> > > I've tested it, and even devices with a static address participate

> > > to the DAA procedure if they've not been assigned a dynamic address

> > > yet, so I don't see the need for this SETDASA step if you don't need

> > > to assign a particular dynamic address to the device.

> > >

> > > Could you tell me why you think SETDASA is required?

> >

> > Yes, you are right... But in my opinion it is required as it does part

> > of DAA process.

> 

> SETDASA is simply faster than ENTDAA, but only if there is no need to

> collect BCR/DCR/PID of such devices. I think most applications would like to

> have them as an status information so  after all ENTDAA can be regarded as

> an generic approach (unless I'm mistaken).


Below are 2 examples on how DAA can be executed:
1st:
A1) SETDASA to devices with SA
B1) DAA to remaining devices
C1) GET BCR/DCR/PID to devices that initially had SA
NOTES: C1 is optional and order of B1 and C1 can be changed 

2nd:
A2) DAA to all devices
NOTES: no need for any follow up steps as all information is collected during DAA

As we can see 2nd approach is more generic and do not see any reason to add special handling for SETDASA unless there is any reasonable reason to do otherwise.

> 

> >

> > >>>>> +static u32 i3c_master_i2c_functionalities(struct i2c_adapter

> > >>>>> +*adap) {

> > >>>>> +	return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_I2C |

> > I2C_FUNC_10BIT_ADDR;

> > >>>>> +}

> > >>>>  Is I2C_FUNC_10BIT_ADDR allowed ?

> > >>> According to "Table 4 I 2 C Features Allowed in I3C Slaves", yes

> > >>> (at least that my understanding). And the Cadence controller

> supports it.

> > >> The table say the oposite. The I2C extended address feature is not

> > >> used on I3C bus, thus this feature shall be disable.

> > > Actually, I was wrong when initially mentioning this table: it's

> > > about I2C features supported on I3C slaves, so not really what we're

> > > looking for. Here, we're wondering if I2C-only devices can have

> > > 10-bit addresses. The Cadence controller supports that, so there's

> > > probably nothing preventing use of 10-bit addresses for I2C

> > > transfers, but maybe not all I3C master controllers support that, so

> > > we should probably let the I3C master driver implement this method.

> >

> > The spec says that is "not used" so it will not interface with I3C bus.

> >

> > >> BTW it is optional on I2C devices.

> > > You mean I2C controllers? When an I2C device has a 10bit address,

> > > the controller has to support this mode to communicate with the

> > > device, at least that's my understanding. But we're digressing a

> > > bit. The question is not whether I2C devices can optionally use a 10

> > > bit address, but whether I3C master controller can support this mode

> > > for I2C transfers to I2C-only devices.

> >

> > By the i2c spec the 10-bit address is optional, however the 7-bit

> > address is mandatory.

> >

> > >>>

> > >>>>  > diff --git a/drivers/i3c/master/Kconfig

> > >>>> b/drivers/i3c/master/Kconfig

> > >>>>> new file mode 100644

> > >>>>> index 000000000000..e69de29bb2d1 diff --git

> > >>>>> a/drivers/i3c/master/Makefile b/drivers/i3c/master/Makefile new

> > >>>>> file mode 100644 index

> > >>>>> 000000000000..e69de29bb2d1 diff --git a/include/linux/i3c/ccc.h

> > >>>>> b/include/linux/i3c/ccc.h new file mode 100644 index

> > >>>>> 000000000000..ff3e1a3e2c4c

> > >>>>> --- /dev/null

> > >>>>> +++ b/include/linux/i3c/ccc.h

> > >>>>> @@ -0,0 +1,380 @@

> > >>>>> +/* SPDX-License-Identifier: GPL-2.0 */

> > >>>>> +/*

> > >>>>> + * Copyright (C) 2017 Cadence Design Systems Inc.

> > >>>>> + *

> > >>>>> + * Author: Boris Brezillon<boris.brezillon@free-electrons.com>

> > >>>>> + */

> > >>>>> +

> > >>>>> +

> > >>>>> +/**

> > >>>>> + * enum i3c_ccc_test_mode - enum listing all available test

> > >>>>> +modes

> > >>>>> + *

> > >>>>> + * @I3C_CCC_EXIT_TEST_MODE: exit test mode

> > >>>>> + * @I3C_CCC_VENDOR_TEST_MODE: enter vendor test mode  */

> > enum

> > >>>>> +i3c_ccc_test_mode {

> > >>>>> +	I3C_CCC_EXIT_TEST_MODE,

> > >>>>> +	I3C_CCC_VENDOR_TEST_MODE,

> > >>>>> +};

> > >>>>> +

> > >>>>> +/**

> > >>>>> + * struct i3c_ccc_enttm - payload passed to ENTTM CCC

> > >>>>> + *

> > >>>>> + * @mode: one of the &enum i3c_ccc_test_mode modes

> > >>>>> + *

> > >>>>> + * Information passed to the ENTTM CCC to instruct an I3C

> > >>>>> +device to enter a

> > >>>>> + * specific test mode.

> > >>>>> + */

> > >>>>> +struct i3c_ccc_enttm {

> > >>>>> +	u8 mode;

> > >>>>> +} __packed;

> > >>>>> +

> > >>>>> +/**

> > >>>>> + * struct i3c_ccc_setda - payload passed to ENTTM CCC

> > >>>>> + *

> > >>>>> + * @mode: one of the &enum i3c_ccc_test_mode modes

> > >>>>> + *

> > >>>>> + * Information passed to the ENTTM CCC to instruct an I3C

> > >>>>> +device to enter a

> > >>>>> + * specific test mode.

> > >>>>> + */

> > >>>>> +struct i3c_ccc_setda {

> > >>>>> +	u8 addr;

> > >>>>> +} __packed;

> > >>>>  what do you mean with struct? Maybe setdasa? if so, what is the

> > addr?

> > >> Do you have the function to use this structure? Because one command

> > >> use the static address and the other use the dynamic address.

> > >>

> > >>>>

> > >>>>  > +/**

> > >>>>> + * enum i3c_sdr_max_data_rate - max data rate values for

> > >>>>> +private SDR transfers  */ enum i3c_sdr_max_data_rate {

> > >>>>> +	I3C_SDR_DR_FSCL_MAX,

> > >>>>> +	I3C_SDR_DR_FSCL_8MHZ,

> > >>>>> +	I3C_SDR_DR_FSCL_6MHZ,

> > >>>>> +	I3C_SDR_DR_FSCL_4MHZ,

> > >>>>> +	I3C_SDR_DR_FSCL_2MHZ,

> > >>>>> +};

> > >>>> Can you change the names to:

> > >>>>

> > >>>> I3C_SDR0_FSCL_MAX,

> > >>>> I3C_SDR1_FSCL_8MHZ,

> > >>>> I3C_SDR2_FSCL_6MHZ,

> > >>>> I3C_SDR3_FSCL_4MHZ,

> > >>>> I3C_SDR4_FSCL_2MHZ,

> > >>>>

> > >>>> thus the data rate isn't repeated.

> > >>> What's the problem with the name I use? Moreover, I see no mention

> > >>> to the SDR0,1,2,3,4 modes in the public spec.

> > >> When you get the GETMXDS information, the maxWr and maxRd came

> > from 0

> > >> to 4, so in my opinion I think in this way is easier to have a

> relationship.

> > > It's an emum, and there's no mention of the SDRX modes you're using

> > > here in the I3C spec. I guess it's named this way in your I3C

> > > controller datasheet. I personally don't see a good reason to add

> > > SDRX in the name, but if you insist...

> >

> > The idea is to say that it is SDR mode and the value that GETMXDS

> > command return. It is what makes sense to me.

> >

> > >>>>> +

> > >>>>> +#endif /* I3C_CCC_H */

> > >>>>> diff --git a/include/linux/i3c/device.h

> > >>>>> b/include/linux/i3c/device.h new file mode 100644 index

> > >>>>> 000000000000..83958d3a02e2

> > >>>>> --- /dev/null

> > >>>>> +++ b/include/linux/i3c/device.h

> > >>>>> @@ -0,0 +1,321 @@

> > >>>>> +/* SPDX-License-Identifier: GPL-2.0 */

> > >>>>> +/*

> > >>>>> + * Copyright (C) 2017 Cadence Design Systems Inc.

> > >>>>> + *

> > >>>>> + * Author: Boris Brezillon<boris.brezillon@free-electrons.com>

> > >>>>> + */

> > >>>>> +

> > >>>>> +#ifndef I3C_DEV_H

> > >>>>> +#define I3C_DEV_H

> > >>>>> +

> > >>>>> +#include <linux/device.h>

> > >>>>> +#include <linux/i2c.h>

> > >>>>> +#include <linux/mod_devicetable.h> #include <linux/module.h>

> > >>>>> +

> > >>>>> +/**

> > >>>>> + * enum i3c_hdr_mode - HDR mode ids

> > >>>>> + * @I3C_HDR_DDR: DDR mode

> > >>>>> + * @I3C_HDR_TSP: TSP mode

> > >>>>> + * @I3C_HDR_TSL: TSL mode

> > >>>>> + */

> > >>>>> +enum i3c_hdr_mode {

> > >>>>> +	I3C_HDR_DDR,

> > >>>>> +	I3C_HDR_TSP,

> > >>>>> +	I3C_HDR_TSL,

> > >>>>> +};

> > >>>>> +

> > >>>>> +/**

> > >>>>> + * struct i3c_hdr_cmd - I3C HDR command

> > >>>>> + * @mode: HDR mode selected for this command

> > >>>>> + * @code: command opcode

> > >>>>> + * @addr: I3C dynamic address

> > >>>>> + * @ndatawords: number of data words (a word is 16bits wide)

> > >>>>> + * @data: input/output buffer

> > >>>>> + */

> > >>>>> +struct i3c_hdr_cmd {

> > >>>>> +	enum i3c_hdr_mode mode;

> > >>>>> +	u8 code;

> > >>>>> +	u8 addr;

> > >>>>> +	int ndatawords;

> > >>>>> +	union {

> > >>>>> +		u16 *in;

> > >>>>> +		const u16 *out;

> > >>>>> +	} data;

> > >>>>> +};

> > >> Please mention that the @code is what will define if the transfer

> > >> is read

> > or write.

> > > Well, I think it's pretty clear in the definition you'll find in the

> > > ccc.h file, but I can add a comment here too if you like.

> >

> > I don't find it in ccc.h file. Anyway is not good to put this

> > definition there because is not related.

> >

> > >>>>> +

> > >>>>> +/* Private SDR read transfer */

> > >>>>> +#define I3C_PRIV_XFER_READ		BIT(0)

> > >>>>> +/*

> > >>>>> + * Instruct the controller to issue a STOP after a specific

> > >>>>> +transfer instead

> > >>>>> + * of a REPEATED START.

> > >>>>> + */

> > >>>>> +#define I3C_PRIV_XFER_STOP		BIT(1)

> > >>>>> +

> > >>>>> +/**

> > >>>>> + * struct i3c_priv_xfer - I3C SDR private transfer

> > >>>>> + * @addr: I3C dynamic address

> > >>>>> + * @len: transfer length in bytes of the transfer

> > >>>>> + * @flags: combination of I3C_PRIV_XFER_xxx flags

> > >>>>> + * @data: input/output buffer

> > >>>>> + */

> > >>>>> +struct i3c_priv_xfer {

> > >>>>> +	u8 addr;

> > >>>>> +	u16 len;

> > >>>>> +	u32 flags;

> > >>>>> +	struct {

> > >>>>> +		void *in;

> > >>>>> +		const void *out;

> > >>>>> +	} data;

> > >>>>> +};

> > >>>>  Same as above, i3c_sdr_max_data_rate to change the bus scl.

> > >>> If I'm understanding the spec correctly, that's not something you

> > >>> want to change on a per-transfer basis. The constraint is on the

> > >>> device itself and should IMO not be part of the i3c_priv_xfer struct.

> > >> As mention before this is important.

> > >> You can do the same as for struct i3c_hdr_cmd and add a enum

> > i3c_sdr_max_data_rate.

> > >>

> > >> The @flag only have 2 bits of load, is the rest opened?

> > > If by open you mean that we can add more flags if we need to, then yes.

> > >

> > >>>

> > >>>>  > +

> > >>>>> +/**

> > >>>>> + * enum i3c_dcr - I3C DCR values

> > >>>>> + * @I3C_DCR_GENERIC_DEVICE: generic I3C device  */ enum

> i3c_dcr

> > {

> > >>>>> +	I3C_DCR_GENERIC_DEVICE = 0,

> > >>>>> +};

> > >>>>> +

> > >>>>> +#define I3C_PID_MANUF_ID(pid)		(((pid) &

> > GENMASK_ULL(47, 33)) >> 33)

> > >>>>> +#define I3C_PID_RND_LOWER_32BITS(pid)	(!!((pid) &

> > BIT_ULL(32)))

> > >>>>> +#define I3C_PID_RND_VAL(pid)		((pid) &

> GENMASK_ULL(31,

> > 0))

> > >>>>> +#define I3C_PID_PART_ID(pid)		(((pid) &

> GENMASK_ULL(31,

> > 16)) >> 16)

> > >>>>> +#define I3C_PID_INSTANCE_ID(pid)	(((pid) & GENMASK_ULL(15,

> > 12)) >> 12)

> > >>>>> +#define I3C_PID_EXTRA_INFO(pid)		((pid) &

> > GENMASK_ULL(11, 0))

> > >>>>> +

> > >>>>> +#define I3C_BCR_DEVICE_ROLE(bcr)	((bcr) & GENMASK(7, 6))

> > >>>>> +#define I3C_BCR_I3C_SLAVE		(0 << 6)

> > >>>>> +#define I3C_BCR_I3C_MASTER		(1 << 6)

> > >>>>> +#define I3C_BCR_HDR_CAP			BIT(5)

> > >>>>> +#define I3C_BCR_BRIDGE			BIT(4)

> > >>>>> +#define I3C_BCR_OFFLINE_CAP		BIT(3)

> > >>>>> +#define I3C_BCR_IBI_PAYLOAD		BIT(2)

> > >>>>> +#define I3C_BCR_IBI_REQ_CAP		BIT(1)

> > >>>>> +#define I3C_BCR_MAX_DATA_SPEED_LIM	BIT(0)

> > >>>>> +

> > >>>>> +/**

> > >>>>> + * struct i3c_device_info - I3C device information

> > >>>>> + * @pid: Provisional ID

> > >>>>> + * @bcr: Bus Characteristic Register

> > >>>>> + * @dcr: Device Characteristic Register

> > >>>>> + * @static_addr: static/I2C address

> > >>>>> + * @dyn_addr: dynamic address

> > >>>>> + * @hdr_cap: supported HDR modes

> > >>>>> + * @max_read_ds: max read speed information

> > >>>>> + * @max_write_ds: max write speed information

> > >>>>> + * @max_ibi_len: max IBI payload length

> > >>>>> + * @max_read_turnaround: max read turn-around time in

> > >>>>> +micro-seconds

> > >>>>> + * @max_read_len: max private SDR read length in bytes

> > >>>>> + * @max_write_len: max private SDR write length in bytes

> > >>>>> + *

> > >>>>> + * These are all basic information that should be advertised by

> > >>>>> +an

> > I3C device.

> > >>>>> + * Some of them are optional depending on the device type and

> > >>>>> +device

> > >>>>> + * capabilities.

> > >>>>> + * For each I3C slave attached to a master with

> > >>>>> + * i3c_master_add_i3c_dev_locked(), the core will send the

> > >>>>> +relevant CCC command

> > >>>>> + * to retrieve these data.

> > >>>>> + */

> > >>>>> +struct i3c_device_info {

> > >>>>> +	u64 pid;

> > >>>>> +	u8 bcr;

> > >>>>> +	u8 dcr;

> > >>>>> +	u8 static_addr;

> > >>>>> +	u8 dyn_addr;

> > >>>>> +	u8 hdr_cap;

> > >>>>> +	u8 max_read_ds;

> > >>>>> +	u8 max_write_ds;

> > >>>>> +	u8 max_ibi_len;

> > >>>>> +	u32 max_read_turnaround;

> > >>>>> +	u16 max_read_len;

> > >>>>> +	u16 max_write_len;

> > >>>>> +};

> > >>>>> +

> > >>>>  is this information filled with data provided from CCC commands?

> > >>> Yes, they are.

> > >> Ok, them the intention is to do this on bus_init(), right?

> > > Not only, it can be after a Hot-Join, or after the user has

> > > triggered a new DAA. Anyway, these information are retrieved anytime

> > > you add a device with i3c_master_add_i3c_dev_locked(), and the core

> > > uses CCC commands to do that.

> > >

> > >>>>> +

> > >>>>> +/**

> > >>>>> + * struct i3c_master_controller_ops - I3C master methods

> > >>>>> + * @bus_init: hook responsible for the I3C bus initialization. This

> > >>>>> + *	      initialization should follow the steps described in the I3C

> > >>>>> + *	      specification. This hook is called with the bus lock held

> > in

> > >>>>> + *	      write mode, which means all _locked() helpers can safely

> > be

> > >>>>> + *	      called from there

> > >>>>> + * @bus_cleanup: cleanup everything done in

> > >>>>> + *		 &i3c_master_controller_ops->bus_init(). This

> > function is

> > >>>>> + *		 optional and should only be implemented if

> > >>>>> + *		 &i3c_master_controller_ops->bus_init() attached

> > private data

> > >>>>> + *		 to I3C/I2C devices. This hook is called with the bus

> > lock

> > >>>>> + *		 held in write mode, which means all _locked()

> > helpers can

> > >>>>> + *		 safely be called from there

> > >>>>> + * @supports_ccc_cmd: should return true if the CCC command is

> > supported, false

> > >>>>> + *		      otherwise

> > >>>>> + * @send_ccc_cmd: send a CCC command

> > >>>>> + * @send_hdr_cmds: send one or several HDR commands. If there

> > >>>>> + is

> > more than one

> > >>>>> + *		   command, they should ideally be sent in the same

> > HDR

> > >>>>> + *		   transaction

> > >>>>> + * @priv_xfers: do one or several private I3C SDR transfers

> > >>>>> + * @i2c_xfers: do one or several I2C transfers

> > >>>>> + * @request_ibi: attach an IBI handler to an I3C device. This

> > >>>>> + implies

> > defining

> > >>>>> + *		 an IBI handler and the constraints of the IBI

> > (maximum payload

> > >>>>> + *		 length and number of pre-allocated slots).

> > >>>>> + *		 Some controllers support less IBI-capable devices

> > than regular

> > >>>>> + *		 devices, so this method might return -%EBUSY if

> > there's no

> > >>>>> + *		 more space for an extra IBI registration

> > >>>>> + * @free_ibi: free an IBI previously requested with ->request_ibi().

> > The IBI

> > >>>>> + *	      should have been disabled with ->disable_irq() prior to

> > that

> > >>>>> + * @enable_ibi: enable the IBI. Only valid if ->request_ibi()

> > >>>>> + has been

> > called

> > >>>>> + *		prior to ->enable_ibi(). The controller should first

> > enable

> > >>>>> + *		the IBI on the controller end (for example, unmask

> > the hardware

> > >>>>> + *		IRQ) and then send the ENEC CCC command (with

> > the IBI flag set)

> > >>>>> + *		to the I3C device

> > >>>>> + * @disable_ibi: disable an IBI. First send the DISEC CCC

> > >>>>> + command

> > with the IBI

> > >>>>> + *		 flag set and then deactivate the hardware IRQ on

> > the

> > >>>>> + *		 controller end

> > >>>>> + * @recycle_ibi_slot: recycle an IBI slot. Called every time an

> > >>>>> + IBI has

> > been

> > >>>>> + *		      processed by its handler. The IBI slot should be

> > put back

> > >>>>> + *		      in the IBI slot pool so that the controller can re-

> > use it

> > >>>>> + *		      for a future IBI

> > >>>>> + *

> > >>>>> + * One of the most important hooks in these ops is

> > >>>>> + * &i3c_master_controller_ops->bus_init(). Here is a

> > >>>>> +non-exhaustive list of

> > >>>>> + * things that should be done in &i3c_master_controller_ops-

> > >bus_init():

> > >>>>> + *

> > >>>>> + * 1) call i3c_master_set_info() with all information

> > >>>>> +describing the master

> > >>>>> + * 2) ask all slaves to drop their dynamic address by sending

> > >>>>> +the

> > RSTDAA CCC

> > >>>>> + *    with i3c_master_rstdaa_locked()

> > >>>>> + * 3) ask all slaves to disable IBIs using

> > >>>>> +i3c_master_disec_locked()

> > >>>>> + * 4) start a DDA procedure by sending the ENTDAA CCC with

> > >>>>> + *    i3c_master_entdaa_locked(), or using the internal DAA logic

> > provided by

> > >>>>> + *    your controller

> > >>>> You mean SETDASA CCC command?

> > >>> No, I really mean ENTDAA and DAA. By internal DAA logic I mean

> > >>> that some controllers are probably automating the whole DAA

> > >>> procedure, while others may let the SW control every step.

> > >> My understanding is that i3c_master_entdaa_locked() will trigger

> > >> the DAA process and DAA can be done by SETDASA, ENTDAA and later

> > >> after the bus initialization with SETNEWDA.

> > > No. Only ENTDAA can trigger a DAA procedure. SETDASA is here to

> > > assign a single dynamic address to a device that already has a

> > > static address but no dynamic address yet, and SETNEWDA is here to

> > > modify the

> > dynamic

> > > address of a device that already has one.

> >

> > >> I think the DAA process should be more generic, right now is only

> > >> made through the ENTDAA command with (cmd.ndests = 1).

> > >> I mean, shouldn't this be made by the core? First doing DAA for the

> > >> devices declared and them try do discover the rest of devices on the

> bus.

> > > Can you detail a bit more? If the only part you're complaining about

> > > is pre-assignment of dynamic addresses with SETDASA when a device is

> > > declared in the DT with a reg and dynamic-address property, then

> > > yes, I think I can provide an helper for that. But this helper would

> > > still have to be called from the master controller driver (from

> > > ->bus_init() or after a Hot-Join).

> > >

> > > Now, if the question is, is there a way we can automate things even

> > > more and completely implement DAA from the core? I doubt it, because

> > > the way the core will trigger DAA, expose discovered devices or

> > > allow you to declare manually assigned addresses is likely to be

> > > controller-dependent.

> >

> > Please refer to figure 90 of public specification. As you can see the

> > DAA process should start with SETDASA command.

> >

> > With the current flow of this patch the DAA process is limited to

> > ENTDAA command only.

> >

> > > When I designed the framework I took the decision to base my work on

> > > the spec rather than focusing on the I3C master controller I had to

> > > support (Cadence). This is the reason I decided to keep the

> > > interface as simple as possible at the risk of encouraging

> > > code-duplication (at

> > > first) rather than coming up with an interface that is designed with

> > > a single controller in mind and having to break things every time a

> > > new controller comes out.

> > >

> > > Thank you for you comments, but I'd like to know if some of my

> > > design choices are blocking you to support your controller. What

> > > I've seen so far is a collection of things that might be relevant to

> > > fix (though most of them are subject to interpretation and/or a

> > > matter of taste), but nothing that should really block you.

> > >

> > > Can you clarify that, and maybe come back with a list of things that

> > > you think are preventing you from properly supporting the Synopsys

> > > controller?

> > >

> > > Thanks,

> > >

> > > Boris

> >

> > As you can check from my  comments my concerns are about the i3c

> > specification without the controller in mind.

> >

> > Best regards,

> > Vitor Soares

> >
Boris Brezillon Feb. 27, 2018, 7:57 p.m. UTC | #22 
Hi Vitor,

On Tue, 27 Feb 2018 16:03:58 +0000
Vitor Soares <Vitor.Soares@synopsys.com> wrote:

> >>>
> >>> The speed R/W speed limitation is encoded in the device object, so, if
> >>> the controller has to configure that on a per-transfer basis, one
> >>> solution would be to pass the device to the ->priv_xfers().    
> >> The speed R/W limitation is only for private transfers. Also the device can have
> >> a limitation to write and not for read data.
> >> This information is obtained with the command GETMXDS which returns the Maximum
> >> Sustained Data Rate for non-CCC messages.  
> > And that's exactly what I expose in i3c_device_info, which is embedded
> > in i3c_device, so you should have all the information you need to
> > determine the speed in the controller driver if ->priv_xfer() is passed
> > the device attached to those transfers. Would that be okay if we pass an
> > i3c_device object to ->priv_xfers()?  
> 
> If you pass the i3c_device to ->priv_xfer(), then you won't need the address too.

That's true. So how about we pass the i3c_device to ->priv_xfer() and
drop the address field in i3c_priv_xfer. Or we could remove the address
field add an i3c_device pointer in i3c_priv_xfer, this way, if we ever
need to do cross-device sequence we'll be able to support it.

> 
> Maybe someone else can give other point of view.

That'd be great, but I'd like to hear your opinion, because it's not
clear to me what you think of my suggestion.


> >> Either important is the SETDASA for declared I3C devices. So the DAA process
> >> should start by send an SETDASA and them ENTDAA CCC command.  
> > My understanding was that SETDASA was not mandatory, and was only useful
> > when one wants to assign a specific dynamic address to a slave that has
> > a static address (which is again not mandatory).
> > I've tested it, and even devices with a static address participate to
> > the DAA procedure if they've not been assigned a dynamic address yet,
> > so I don't see the need for this SETDASA step if you don't need to
> > assign a particular dynamic address to the device.
> >
> > Could you tell me why you think SETDASA is required?  
> 
> Yes, you are right... But in my opinion it is required as it does part of DAA
> process.

As Przemek said in his reply, I don't think it's required, at least not
for the initial implementation. I'm definitely not saying we should
never support the feature, but it can easily be added afterwards.

BTW, can you give me a scenario where you'll want to assign a specific
dynamic address to a device before DAA takes place (by DAA, I mean what
happens after ENTDAA, which AIUI is what DAA describes)? I know it's
described in the spec, and might become useful at some point, but right
now, for a general purpose OS like Linux, I don't see a good reason to
assign a dynamic address using SETDASA.

> 
> >>>>> +static u32 i3c_master_i2c_functionalities(struct i2c_adapter *adap)
> >>>>> +{
> >>>>> +	return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR;
> >>>>> +}      
> >>>>  Is I2C_FUNC_10BIT_ADDR allowed ?    
> >>> According to "Table 4 I 2 C Features Allowed in I3C Slaves", yes (at
> >>> least that my understanding). And the Cadence controller supports it.    
> >> The table say the oposite. The I2C extended address feature is not used on I3C
> >> bus, thus this feature shall be disable.  
> > Actually, I was wrong when initially mentioning this table: it's about
> > I2C features supported on I3C slaves, so not really what we're looking
> > for. Here, we're wondering if I2C-only devices can have 10-bit
> > addresses. The Cadence controller supports that, so there's probably
> > nothing preventing use of 10-bit addresses for I2C transfers, but maybe
> > not all I3C master controllers support that, so we should probably
> > let the I3C master driver implement this method.  
> 
> The spec says that is "not used" so it will not interface with I3C bus.

Again, I should not have pointed you to this chapter, because it does
not describe what the I3C bus accept, but what I3C slave acting like
I2C devices accept (basically what they accept before being assigned a
dynamic address).

If you see in the I3C spec that I2C transfers using 10-bit addresses
is forbidden, could you tell me where it's stated, because I didn't
find it. 

> 
> >> BTW it is optional on I2C devices.  
> > You mean I2C controllers? When an I2C device has a 10bit address, the
> > controller has to support this mode to communicate with the device, at
> > least that's my understanding. But we're digressing a bit. The
> > question is not whether I2C devices can optionally use a 10 bit
> > address, but whether I3C master controller can support this mode for
> > I2C transfers to I2C-only devices.  
> 
> By the i2c spec the 10-bit address is optional, however the 7-bit address is
> mandatory.

The controller is not forced to support this feature, I think I already
said I agree on this aspect. But if you have a device with a 10-bit
address, it has to be connected to a controller that supports this
feature otherwise it won't work.

So, let's sum-up: I3C controllers can support I2C transfers with 10bit
addresses, but this feature should be optional. I think we might also
want to support optimized smbus methods, so maybe we should just let
I3C controllers fill the i2c_adapter object as they wish.


> >>>>> +/**
> >>>>> + * struct i3c_ccc_setda - payload passed to ENTTM CCC
> >>>>> + *
> >>>>> + * @mode: one of the &enum i3c_ccc_test_mode modes
> >>>>> + *
> >>>>> + * Information passed to the ENTTM CCC to instruct an I3C device to enter a
> >>>>> + * specific test mode.
> >>>>> + */
> >>>>> +struct i3c_ccc_setda {
> >>>>> +	u8 addr;
> >>>>> +} __packed;      
> >>>>  what do you mean with struct? Maybe setdasa? if so, what is the addr?    
> >> Do you have the function to use this structure? Because one command use the
> >> static address and the other use the dynamic address.

Forgot to answer this one in my previous reply. Unicast CCC commands
are always passed the destination in i3c_ccc_cmd->dest[x].addr, so, in
case of SETDASA, i3c_ccc_cmd->dest[x].addr will be the static address,
and in case of SETNEWDA i3c_ccc_cmd->dest[x].addr will be the old
dynamic address. In both cases, the payload will be a single byte
describing the new dynamic address, hence the common i3c_ccc_setda
struct.

> >>  
> >>>>    
> >>>>  > +/**
> >>>>> + * enum i3c_sdr_max_data_rate - max data rate values for private SDR transfers
> >>>>> + */
> >>>>> +enum i3c_sdr_max_data_rate {
> >>>>> +	I3C_SDR_DR_FSCL_MAX,
> >>>>> +	I3C_SDR_DR_FSCL_8MHZ,
> >>>>> +	I3C_SDR_DR_FSCL_6MHZ,
> >>>>> +	I3C_SDR_DR_FSCL_4MHZ,
> >>>>> +	I3C_SDR_DR_FSCL_2MHZ,
> >>>>> +};      
> >>>> Can you change the names to:
> >>>>
> >>>> I3C_SDR0_FSCL_MAX,
> >>>> I3C_SDR1_FSCL_8MHZ,
> >>>> I3C_SDR2_FSCL_6MHZ,
> >>>> I3C_SDR3_FSCL_4MHZ,
> >>>> I3C_SDR4_FSCL_2MHZ,
> >>>>
> >>>> thus the data rate isn't repeated.    
> >>> What's the problem with the name I use? Moreover, I see no mention to
> >>> the SDR0,1,2,3,4 modes in the public spec.    
> >> When you get the GETMXDS information, the maxWr and maxRd came from 0 to 4, so
> >> in my opinion I think in this way is easier to have a relationship.  
> > It's an emum, and there's no mention of the SDRX modes you're using
> > here in the I3C spec. I guess it's named this way in your I3C
> > controller datasheet. I personally don't see a good reason to add SDRX
> > in the name, but if you insist...  
> 
> The idea is to say that it is SDR mode and the value that GETMXDS command
> return. It is what makes sense to me.

Still don't see why this is needed, since what we care about here is
the actual max SCL frequency, which is given in the enum name. But I
don't want to argue more on this minor aspect, so, if everyone is okay,
I'll switch to your solution.

> >>>>> +
> >>>>> +/**
> >>>>> + * struct i3c_hdr_cmd - I3C HDR command
> >>>>> + * @mode: HDR mode selected for this command
> >>>>> + * @code: command opcode
> >>>>> + * @addr: I3C dynamic address
> >>>>> + * @ndatawords: number of data words (a word is 16bits wide)
> >>>>> + * @data: input/output buffer
> >>>>> + */
> >>>>> +struct i3c_hdr_cmd {
> >>>>> +	enum i3c_hdr_mode mode;
> >>>>> +	u8 code;
> >>>>> +	u8 addr;
> >>>>> +	int ndatawords;
> >>>>> +	union {
> >>>>> +		u16 *in;
> >>>>> +		const u16 *out;
> >>>>> +	} data;
> >>>>> +};    
> >> Please mention that the @code is what will define if the transfer is read or write.  
> > Well, I think it's pretty clear in the definition you'll find in the
> > ccc.h file, but I can add a comment here too if you like.  
> 
> I don't find it in ccc.h file. Anyway is not good to put this definition there
> because is not related.

Oops! Sorry, I mixed the CCC and HDR stuff. It's indeed not clear that
@code defines the transfer direction. I'll clarify this aspect. 
 
> >> I think the DAA process should be more generic, right now is only made through
> >> the ENTDAA command with (cmd.ndests = 1).
> >> I mean, shouldn't this be made by the core? First doing DAA for the devices
> >> declared and them try do discover the rest of devices on the bus.  
> > Can you detail a bit more? If the only part you're complaining about is
> > pre-assignment of dynamic addresses with SETDASA when a device is
> > declared in the DT with a reg and dynamic-address property, then yes, I
> > think I can provide an helper for that. But this helper would still have
> > to be called from the master controller driver (from ->bus_init() or
> > after a Hot-Join).
> >
> > Now, if the question is, is there a way we can automate things even more
> > and completely implement DAA from the core? I doubt it, because the way
> > the core will trigger DAA, expose discovered devices or allow you to
> > declare manually assigned addresses is likely to be
> > controller-dependent.  
> 
> Please refer to figure 90 of public specification. As you can see the DAA
> process should start with SETDASA command.

Only if devices with a static address needs to be assigned a specific
dynamic address. At least, that's my understanding. Are there plans to
create devices that would only reply to SETDASA commands but ignore
ENTDAA ones?

> 
> With the current flow of this patch the DAA process is limited to ENTDAA command
> only.

As a first step, yes. But again, nothing is set in stone, and the
SETDASA step can be added afterwards. As said above, I fail to see a
use case where it's really required (note that I said required, not
useful).

> 
> > When I designed the framework I took the decision to base my work on the
> > spec rather than focusing on the I3C master controller I had to support
> > (Cadence). This is the reason I decided to keep the interface as simple
> > as possible at the risk of encouraging code-duplication (at first)
> > rather than coming up with an interface that is designed with a single
> > controller in mind and having to break things every time a new
> > controller comes out.
> >
> > Thank you for you comments, but I'd like to know if some of my design
> > choices are blocking you to support your controller. What I've seen so
> > far is a collection of things that might be relevant to fix (though
> > most of them are subject to interpretation and/or a matter of taste),
> > but nothing that should really block you.
> >
> > Can you clarify that, and maybe come back with a list of things that you
> > think are preventing you from properly supporting the Synopsys
> > controller?
> >
> > Thanks,
> >
> > Boris   
> 
> As you can check from my  comments my concerns are about the i3c specification
> without the controller in mind.

Okay, then we're on the same page.

Regards,

Boris
Boris Brezillon Feb. 27, 2018, 8:13 p.m. UTC | #23 
Hi Przemek,

On Tue, 27 Feb 2018 16:43:27 +0000
Przemyslaw Sroka <psroka@cadence.com> wrote:

> >   
> > >> Either important is the SETDASA for declared I3C devices. So the DAA
> > >> process should start by send an SETDASA and them ENTDAA CCC  
> > command.  
> > > My understanding was that SETDASA was not mandatory, and was only
> > > useful when one wants to assign a specific dynamic address to a slave
> > > that has a static address (which is again not mandatory).
> > > I've tested it, and even devices with a static address participate to
> > > the DAA procedure if they've not been assigned a dynamic address yet,
> > > so I don't see the need for this SETDASA step if you don't need to
> > > assign a particular dynamic address to the device.
> > >
> > > Could you tell me why you think SETDASA is required?  
> > 
> > Yes, you are right... But in my opinion it is required as it does part of DAA
> > process.  
> 
> SETDASA is simply faster than ENTDAA, but only if there is no need to
> collect BCR/DCR/PID of such devices. I think most applications would
> like to have them as an status information so  after all ENTDAA can 
> be regarded as an generic approach (unless I'm mistaken).

Actually, we could retrieve BCR/DCR/PID (and all other relevant
information, like MAXDS) even with the SETDASA approach. We just
need to send the according CCC commands after SETDASA.

But that's also my understanding that ENTDAA should always work, and
SETDASA usage is only needed if you want to reserve a dynamic address
and assign it to a device before DAA takes place. This way you can
enforce the device priority (WRT IBIs). But honestly, that's the only
use case I can think of, and to me, it sounds like an advanced feature
we may want to support at some point, but don't need in the initial
implementation.
Przemyslaw Sroka Feb. 27, 2018, 8:24 p.m. UTC | #24 
Hi Boris

> -----Original Message-----
> From: Boris Brezillon [mailto:boris.brezillon@bootlin.com]
> Sent: Tuesday, February 27, 2018 9:13 PM
> To: Przemyslaw Sroka <psroka@cadence.com>
> Cc: Vitor Soares <Vitor.Soares@synopsys.com>; Boris Brezillon
> <boris.brezillon@free-electrons.com>; Wolfram Sang <wsa@the-
> dreams.de>; linux-i2c@vger.kernel.org; Jonathan Corbet <corbet@lwn.net>;
> linux-doc@vger.kernel.org; Greg Kroah-Hartman
> <gregkh@linuxfoundation.org>; Arnd Bergmann <arnd@arndb.de>;
> Arkadiusz Golec <agolec@cadence.com>; Alan Douglas
> <adouglas@cadence.com>; Bartosz Folta <bfolta@cadence.com>; Damian
> Kos <dkos@cadence.com>; Alicja Jurasik-Urbaniak <alicja@cadence.com>;
> Cyprian Wronka <cwronka@cadence.com>; Suresh Punnoose
> <sureshp@cadence.com>; Thomas Petazzoni <thomas.petazzoni@free-
> electrons.com>; Nishanth Menon <nm@ti.com>; Rob Herring
> <robh+dt@kernel.org>; Pawel Moll <pawel.moll@arm.com>; Mark Rutland
> <mark.rutland@arm.com>; Ian Campbell <ijc+devicetree@hellion.org.uk>;
> Kumar Gala <galak@codeaurora.org>; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; Geert Uytterhoeven <geert@linux-m68k.org>; Linus
> Walleij <linus.walleij@linaro.org>
> Subject: Re: [PATCH v2 2/7] i3c: Add core I3C infrastructure
> 
> EXTERNAL MAIL
> 
> 
> Hi Przemek,
> 
> On Tue, 27 Feb 2018 16:43:27 +0000
> Przemyslaw Sroka <psroka@cadence.com> wrote:
> 
> > >
> > > >> Either important is the SETDASA for declared I3C devices. So the
> > > >> DAA process should start by send an SETDASA and them ENTDAA
> CCC
> > > command.
> > > > My understanding was that SETDASA was not mandatory, and was
> only
> > > > useful when one wants to assign a specific dynamic address to a
> > > > slave that has a static address (which is again not mandatory).
> > > > I've tested it, and even devices with a static address participate
> > > > to the DAA procedure if they've not been assigned a dynamic
> > > > address yet, so I don't see the need for this SETDASA step if you
> > > > don't need to assign a particular dynamic address to the device.
> > > >
> > > > Could you tell me why you think SETDASA is required?
> > >
> > > Yes, you are right... But in my opinion it is required as it does
> > > part of DAA process.
> >
> > SETDASA is simply faster than ENTDAA, but only if there is no need to
> > collect BCR/DCR/PID of such devices. I think most applications would
> > like to have them as an status information so  after all ENTDAA can be
> > regarded as an generic approach (unless I'm mistaken).
> 
> Actually, we could retrieve BCR/DCR/PID (and all other relevant
> information, like MAXDS) even with the SETDASA approach. We just need to
> send the according CCC commands after SETDASA.
> 
I agree, what I meant by "SETDASA is simply faster than ENTDAA, but only if there is no need to collect BCR/DCR/PID of such devices." Is that it is faster than DAA but only if not followed by GET CCC commands to gather BCR/DCR/PID. I think we are on the same page here.

> But that's also my understanding that ENTDAA should always work, and
> SETDASA usage is only needed if you want to reserve a dynamic address
> and assign it to a device before DAA takes place. This way you can enforce
> the device priority (WRT IBIs). But honestly, that's the only use case I can
> think of, and to me, it sounds like an advanced feature we may want to
> support at some point, but don't need in the initial implementation.
>
Still ENTDAA seems to be sufficient for IBI prioritization but I can imagine some use cases where people would like to use it for such purposes. Note that SETDASA is applicable only for devices with SA so it is self-explanatory that it cannot be considered as utility to define priorities for all devices before ENTDAA. 

> --
> Boris Brezillon, Bootlin (formerly Free Electrons) Embedded Linux and
> Kernel engineering https://urldefense.proofpoint.com/v2/url?u=https-
> 3A__bootlin.com&d=DwICAg&c=aUq983L2pue2FqKFoP6PGHMJQyoJ7kl3s3G
> Z-_haXqY&r=b0WPdqYyu0KH4-vSatt-ViJE1riZ603zdXl3hHHp_TU&m=wM54-
> BGcSfHEklVRsw02O-bnyNkLTe9c0RyBP_ExzPA&s=pxQrogG-
> Nq4XOMU7SPZ2FZNbgnbnjdERtMm_h7ZcdCE&e=

Regards,
Przemek
Boris Brezillon Feb. 27, 2018, 8:25 p.m. UTC | #25 
Hi Przemek,

On Tue, 27 Feb 2018 17:06:37 +0000
Przemyslaw Sroka <psroka@cadence.com> wrote:

> > > >
> > > > Could you tell me why you think SETDASA is required?  
> > >
> > > Yes, you are right... But in my opinion it is required as it does part
> > > of DAA process.  
> > 
> > SETDASA is simply faster than ENTDAA, but only if there is no need to
> > collect BCR/DCR/PID of such devices. I think most applications would like to
> > have them as an status information so  after all ENTDAA can be regarded as
> > an generic approach (unless I'm mistaken).  
> 
> Below are 2 examples on how DAA can be executed:
> 1st:
> A1) SETDASA to devices with SA

I'm not even sure all devices with a static address needs to be
assigned a dynamic address with SETDASA (actually, I'm almost sure
it's not the case, since, according to section "5.1.9.3 CCC Command
Definitions" of the spec, all I3C slaves have to support ENTDAA). To me,
it looks like you'd want to do that only is you really need to reserve
a specific dynamic address and prevent the DAA step from assigning it
to another device.

> B1) DAA to remaining devices
> C1) GET BCR/DCR/PID to devices that initially had SA
> NOTES: C1 is optional and order of B1 and C1 can be changed

While that's true in principle, in Linux we'll always retrieve
BCR/DCR/PID (and more, like MAXDS), no matter how the device obtained
its dynamic address.

> 
> 2nd:
> A2) DAA to all devices
> NOTES: no need for any follow up steps as all information is collected during DAA

As said above, that's not exactly how the Linux implementation works.
Right now I'm ignoring the information retrieved during DAA and forcing
a GETPID/GETBCR/GETDCR for every discovered device. This approach is
generating a bit more traffic on the bus, but it also makes the
implementation more generic, because we have a single function to add
an I3C device, no matter how it's been assigned a dynamic address.

> 
> As we can see 2nd approach is more generic and do not see any reason to add special handling for SETDASA unless there is any reasonable reason to do otherwise.

I agree on one thing: as long as you don't have to reserve a specific
dynamic address, SETDASA is not required. At least, that's my
understanding.

Regards,

Boris
Boris Brezillon Feb. 27, 2018, 9:14 p.m. UTC | #26 
On Tue, 27 Feb 2018 20:24:43 +0000
Przemyslaw Sroka <psroka@cadence.com> wrote:


> > > SETDASA is simply faster than ENTDAA, but only if there is no
> > > need to collect BCR/DCR/PID of such devices. I think most
> > > applications would like to have them as an status information so
> > > after all ENTDAA can be regarded as an generic approach (unless
> > > I'm mistaken).  
> > 
> > Actually, we could retrieve BCR/DCR/PID (and all other relevant
> > information, like MAXDS) even with the SETDASA approach. We just
> > need to send the according CCC commands after SETDASA.
> >   
> I agree, what I meant by "SETDASA is simply faster than ENTDAA, but
> only if there is no need to collect BCR/DCR/PID of such devices." Is
> that it is faster than DAA but only if not followed by GET CCC
> commands to gather BCR/DCR/PID. I think we are on the same page here.

Yes, but right now it's not the case, see my other reply ;-).

> 
> > But that's also my understanding that ENTDAA should always work, and
> > SETDASA usage is only needed if you want to reserve a dynamic
> > address and assign it to a device before DAA takes place. This way
> > you can enforce the device priority (WRT IBIs). But honestly,
> > that's the only use case I can think of, and to me, it sounds like
> > an advanced feature we may want to support at some point, but don't
> > need in the initial implementation. 
> Still ENTDAA seems to be sufficient for IBI prioritization but I can
> imagine some use cases where people would like to use it for such
> purposes. Note that SETDASA is applicable only for devices with SA so
> it is self-explanatory that it cannot be considered as utility to
> define priorities for all devices before ENTDAA. 

We have SETNEWDA for other use cases: say you want one of your device to
have an higher priority, you can just manually set a new dynamic
address that is lower than any other devices on the bus (I plan to
expose that through sysfs, by making the address file writable).
diff mbox series

Patch

diff --git a/drivers/Kconfig b/drivers/Kconfig
index 152744c5ef0f..d7d78a812770 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -55,6 +55,8 @@  source "drivers/char/Kconfig"
 
 source "drivers/i2c/Kconfig"
 
+source "drivers/i3c/Kconfig"
+
 source "drivers/spi/Kconfig"
 
 source "drivers/spmi/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 1d034b680431..9790c8566918 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -112,7 +112,7 @@  obj-$(CONFIG_SERIO)		+= input/serio/
 obj-$(CONFIG_GAMEPORT)		+= input/gameport/
 obj-$(CONFIG_INPUT)		+= input/
 obj-$(CONFIG_RTC_LIB)		+= rtc/
-obj-y				+= i2c/ media/
+obj-y				+= i2c/ i3c/ media/
 obj-$(CONFIG_PPS)		+= pps/
 obj-y				+= ptp/
 obj-$(CONFIG_W1)		+= w1/
diff --git a/drivers/i3c/Kconfig b/drivers/i3c/Kconfig
new file mode 100644
index 000000000000..cf3752412ae9
--- /dev/null
+++ b/drivers/i3c/Kconfig
@@ -0,0 +1,24 @@ 
+# SPDX-License-Identifier: GPL-2.0
+
+menuconfig I3C
+	tristate "I3C support"
+	select I2C
+	help
+	  I3C is a serial protocol standardized by the MIPI alliance.
+
+	  It's supposed to be backward compatible with I2C while providing
+	  support for high speed transfers and native interrupt support
+	  without the need for extra pins.
+
+	  The I3C protocol also standardizes the slave device types and is
+	  mainly design to communicate with sensors.
+
+	  If you want I3C support, you should say Y here and also to the
+	  specific driver for your bus adapter(s) below.
+
+	  This I3C support can also be built as a module.  If so, the module
+	  will be called i3c.
+
+if I3C
+source "drivers/i3c/master/Kconfig"
+endif # I3C
diff --git a/drivers/i3c/Makefile b/drivers/i3c/Makefile
new file mode 100644
index 000000000000..3b6d1502d6e6
--- /dev/null
+++ b/drivers/i3c/Makefile
@@ -0,0 +1,4 @@ 
+# SPDX-License-Identifier: GPL-2.0
+i3c-y				:= core.o device.o master.o
+obj-$(CONFIG_I3C)		+= i3c.o
+obj-$(CONFIG_I3C)		+= master/
diff --git a/drivers/i3c/core.c b/drivers/i3c/core.c
new file mode 100644
index 000000000000..7eb8e84acd33
--- /dev/null
+++ b/drivers/i3c/core.c
@@ -0,0 +1,573 @@ 
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 Cadence Design Systems Inc.
+ *
+ * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
+ */
+
+#include <linux/idr.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/slab.h>
+
+#include "internals.h"
+
+static DEFINE_IDR(i3c_bus_idr);
+static DEFINE_MUTEX(i3c_core_lock);
+
+/**
+ * i3c_bus_maintenance_lock - Lock the bus for a maintenance operation
+ * @bus: I3C bus to take the lock on
+ *
+ * This function takes the bus lock so that no other operations can occur on
+ * the bus. This is needed for all kind of bus maintenance operation, like
+ * - enabling/disabling slave events
+ * - re-triggering DAA
+ * - changing the dynamic address of a device
+ * - relinquishing mastership
+ * - ...
+ *
+ * The reason for this kind of locking is that we don't want drivers and core
+ * logic to rely on I3C device information that could be changed behind their
+ * back.
+ */
+void i3c_bus_maintenance_lock(struct i3c_bus *bus)
+{
+	down_write(&bus->lock);
+}
+EXPORT_SYMBOL_GPL(i3c_bus_maintenance_lock);
+
+/**
+ * i3c_bus_maintenance_lock - Release the bus lock after a maintenance
+ *			      operation
+ * @bus: I3C bus to release the lock on
+ *
+ * Should be called when the bus maintenance operation is done. See
+ * i3c_bus_maintenance_lock() for more details on what these maintenance
+ * operations are.
+ */
+void i3c_bus_maintenance_unlock(struct i3c_bus *bus)
+{
+	up_write(&bus->lock);
+}
+EXPORT_SYMBOL_GPL(i3c_bus_maintenance_unlock);
+
+/**
+ * i3c_bus_normaluse_lock - Lock the bus for a normal operation
+ * @bus: I3C bus to take the lock on
+ *
+ * This function takes the bus lock for any operation that is not a maintenance
+ * operation (see i3c_bus_maintenance_lock() for a non-exhaustive list of
+ * maintenance operations). Basically all communications with I3C devices are
+ * normal operations (HDR, SDR transfers or CCC commands that do not change bus
+ * state or I3C dynamic address).
+ *
+ * Note that this lock is not guaranteeing serialization of normal operations.
+ * In other words, transfer requests passed to the I3C master can be submitted
+ * in parallel and I3C master drivers have to use their own locking to make
+ * sure two different communications are not inter-mixed, or access to the
+ * output/input queue is not done while the engine is busy.
+ */
+void i3c_bus_normaluse_lock(struct i3c_bus *bus)
+{
+	down_read(&bus->lock);
+}
+EXPORT_SYMBOL_GPL(i3c_bus_normaluse_lock);
+
+/**
+ * i3c_bus_normaluse_lock - Release the bus lock after a normal operation
+ * @bus: I3C bus to release the lock on
+ *
+ * Should be called when a normal operation is done. See
+ * i3c_bus_normaluse_lock() for more details on what these normal operations
+ * are.
+ */
+void i3c_bus_normaluse_unlock(struct i3c_bus *bus)
+{
+	up_read(&bus->lock);
+}
+EXPORT_SYMBOL_GPL(i3c_bus_normaluse_unlock);
+
+static ssize_t bcr_show(struct device *dev,
+			struct device_attribute *da,
+			char *buf)
+{
+	struct i3c_device *i3cdev = dev_to_i3cdev(dev);
+	struct i3c_bus *bus = i3c_device_get_bus(i3cdev);
+	ssize_t ret;
+
+	i3c_bus_normaluse_lock(bus);
+	ret = sprintf(buf, "%x\n", i3cdev->info.bcr);
+	i3c_bus_normaluse_unlock(bus);
+
+	return ret;
+}
+static DEVICE_ATTR_RO(bcr);
+
+static ssize_t dcr_show(struct device *dev,
+			struct device_attribute *da,
+			char *buf)
+{
+	struct i3c_device *i3cdev = dev_to_i3cdev(dev);
+	struct i3c_bus *bus = i3c_device_get_bus(i3cdev);
+	ssize_t ret;
+
+	i3c_bus_normaluse_lock(bus);
+	ret = sprintf(buf, "%x\n", i3cdev->info.dcr);
+	i3c_bus_normaluse_unlock(bus);
+
+	return ret;
+}
+static DEVICE_ATTR_RO(dcr);
+
+static ssize_t pid_show(struct device *dev,
+			struct device_attribute *da,
+			char *buf)
+{
+	struct i3c_device *i3cdev = dev_to_i3cdev(dev);
+	struct i3c_bus *bus = i3c_device_get_bus(i3cdev);
+	ssize_t ret;
+
+	i3c_bus_normaluse_lock(bus);
+	ret = sprintf(buf, "%llx\n", i3cdev->info.pid);
+	i3c_bus_normaluse_unlock(bus);
+
+	return ret;
+}
+static DEVICE_ATTR_RO(pid);
+
+static ssize_t address_show(struct device *dev,
+			    struct device_attribute *da,
+			    char *buf)
+{
+	struct i3c_device *i3cdev = dev_to_i3cdev(dev);
+	struct i3c_bus *bus = i3c_device_get_bus(i3cdev);
+	ssize_t ret;
+
+	i3c_bus_normaluse_lock(bus);
+	ret = sprintf(buf, "%02x\n", i3cdev->info.dyn_addr);
+	i3c_bus_normaluse_unlock(bus);
+
+	return ret;
+}
+static DEVICE_ATTR_RO(address);
+
+static const char * const hdrcap_strings[] = {
+	"hdr-ddr", "hdr-tsp", "hdr-tsl",
+};
+
+static ssize_t hdrcap_show(struct device *dev,
+			   struct device_attribute *da,
+			   char *buf)
+{
+	struct i3c_device *i3cdev = dev_to_i3cdev(dev);
+	struct i3c_bus *bus = i3c_device_get_bus(i3cdev);
+	unsigned long caps = i3cdev->info.hdr_cap;
+	ssize_t offset = 0, ret;
+	int mode;
+
+	i3c_bus_normaluse_lock(bus);
+	for_each_set_bit(mode, &caps, 8) {
+		if (mode >= ARRAY_SIZE(hdrcap_strings))
+			break;
+
+		if (!hdrcap_strings[mode])
+			continue;
+
+		ret = sprintf(buf + offset, offset ? " %s" : "%s",
+			      hdrcap_strings[mode]);
+		if (ret < 0)
+			goto out;
+
+		offset += ret;
+	}
+
+	ret = sprintf(buf + offset, "\n");
+	if (ret < 0)
+		goto out;
+
+	ret = offset + ret;
+
+out:
+	i3c_bus_normaluse_unlock(bus);
+
+	return ret;
+}
+static DEVICE_ATTR_RO(hdrcap);
+
+static struct attribute *i3c_device_attrs[] = {
+	&dev_attr_bcr.attr,
+	&dev_attr_dcr.attr,
+	&dev_attr_pid.attr,
+	&dev_attr_address.attr,
+	&dev_attr_hdrcap.attr,
+	NULL,
+};
+ATTRIBUTE_GROUPS(i3c_device);
+
+static int i3c_device_uevent(struct device *dev, struct kobj_uevent_env *env)
+{
+	struct i3c_device *i3cdev = dev_to_i3cdev(dev);
+	u16 manuf = I3C_PID_MANUF_ID(i3cdev->info.pid);
+	u16 part = I3C_PID_PART_ID(i3cdev->info.pid);
+	u16 ext = I3C_PID_EXTRA_INFO(i3cdev->info.pid);
+
+	if (I3C_PID_RND_LOWER_32BITS(i3cdev->info.pid))
+		return add_uevent_var(env, "MODALIAS=i3c:dcr%02Xmanuf%04X",
+				      i3cdev->info.dcr, manuf);
+
+	return add_uevent_var(env,
+			      "MODALIAS=i3c:dcr%02Xmanuf%04Xpart%04xext%04x",
+			      i3cdev->info.dcr, manuf, part, ext);
+}
+
+const struct device_type i3c_device_type = {
+	.groups	= i3c_device_groups,
+	.uevent = i3c_device_uevent,
+};
+
+const struct device_type i3c_master_type = {
+	.groups	= i3c_device_groups,
+};
+
+static int i3c_device_match(struct device *dev, struct device_driver *drv)
+{
+	struct i3c_device *i3cdev;
+	struct i3c_driver *i3cdrv;
+
+	if (dev->type != &i3c_device_type)
+		return 0;
+
+	i3cdev = dev_to_i3cdev(dev);
+	i3cdrv = drv_to_i3cdrv(drv);
+	if (i3c_device_match_id(i3cdev, i3cdrv->id_table))
+		return 1;
+
+	return 0;
+}
+
+static int i3c_device_probe(struct device *dev)
+{
+	struct i3c_device *i3cdev = dev_to_i3cdev(dev);
+	struct i3c_driver *driver = drv_to_i3cdrv(dev->driver);
+
+	return driver->probe(i3cdev);
+}
+
+static int i3c_device_remove(struct device *dev)
+{
+	struct i3c_device *i3cdev = dev_to_i3cdev(dev);
+	struct i3c_driver *driver = drv_to_i3cdrv(dev->driver);
+	int ret;
+
+	ret = driver->remove(i3cdev);
+	if (ret)
+		return ret;
+
+	if (WARN_ON(i3cdev->ibi))
+		i3c_device_free_ibi(i3cdev);
+
+	return ret;
+}
+
+struct bus_type i3c_bus_type = {
+	.name = "i3c",
+	.match = i3c_device_match,
+	.probe = i3c_device_probe,
+	.remove = i3c_device_remove,
+};
+
+enum i3c_addr_slot_status i3c_bus_get_addr_slot_status(struct i3c_bus *bus,
+						       u16 addr)
+{
+	int status, bitpos = addr * 2;
+
+	if (addr > I2C_MAX_ADDR)
+		return I3C_ADDR_SLOT_RSVD;
+
+	status = bus->addrslots[bitpos / BITS_PER_LONG];
+	status >>= bitpos % BITS_PER_LONG;
+
+	return status & I3C_ADDR_SLOT_STATUS_MASK;
+}
+
+void i3c_bus_set_addr_slot_status(struct i3c_bus *bus, u16 addr,
+				  enum i3c_addr_slot_status status)
+{
+	int bitpos = addr * 2;
+	unsigned long *ptr;
+
+	if (addr > I2C_MAX_ADDR)
+		return;
+
+	ptr = bus->addrslots + (bitpos / BITS_PER_LONG);
+	*ptr &= ~(I3C_ADDR_SLOT_STATUS_MASK << (bitpos % BITS_PER_LONG));
+	*ptr |= status << (bitpos % BITS_PER_LONG);
+}
+
+bool i3c_bus_dev_addr_is_avail(struct i3c_bus *bus, u8 addr)
+{
+	enum i3c_addr_slot_status status;
+
+	status = i3c_bus_get_addr_slot_status(bus, addr);
+
+	return status == I3C_ADDR_SLOT_FREE;
+}
+
+int i3c_bus_get_free_addr(struct i3c_bus *bus, u8 start_addr)
+{
+	enum i3c_addr_slot_status status;
+	u8 addr;
+
+	for (addr = start_addr; addr < I3C_MAX_ADDR; addr++) {
+		status = i3c_bus_get_addr_slot_status(bus, addr);
+		if (status == I3C_ADDR_SLOT_FREE)
+			return addr;
+	}
+
+	return -ENOMEM;
+}
+
+static void i3c_bus_init_addrslots(struct i3c_bus *bus)
+{
+	int i;
+
+	/* Addresses 0 to 7 are reserved. */
+	for (i = 0; i < 8; i++)
+		i3c_bus_set_addr_slot_status(bus, i, I3C_ADDR_SLOT_RSVD);
+
+	/*
+	 * Reserve broadcast address and all addresses that might collide
+	 * with the broadcast address when facing a single bit error.
+	 */
+	i3c_bus_set_addr_slot_status(bus, I3C_BROADCAST_ADDR,
+				     I3C_ADDR_SLOT_RSVD);
+	for (i = 0; i < 7; i++)
+		i3c_bus_set_addr_slot_status(bus, I3C_BROADCAST_ADDR ^ BIT(i),
+					     I3C_ADDR_SLOT_RSVD);
+}
+
+static const char * const i3c_bus_mode_strings[] = {
+	[I3C_BUS_MODE_PURE] = "pure",
+	[I3C_BUS_MODE_MIXED_FAST] = "mixed-fast",
+	[I3C_BUS_MODE_MIXED_SLOW] = "mixed-slow",
+};
+
+static ssize_t mode_show(struct device *dev,
+			 struct device_attribute *da,
+			 char *buf)
+{
+	struct i3c_bus *i3cbus = container_of(dev, struct i3c_bus, dev);
+	ssize_t ret;
+
+	i3c_bus_normaluse_lock(i3cbus);
+	if (i3cbus->mode < 0 ||
+	    i3cbus->mode > ARRAY_SIZE(i3c_bus_mode_strings) ||
+	    !i3c_bus_mode_strings[i3cbus->mode])
+		ret = sprintf(buf, "unknown\n");
+	else
+		ret = sprintf(buf, "%s\n", i3c_bus_mode_strings[i3cbus->mode]);
+	i3c_bus_normaluse_unlock(i3cbus);
+
+	return ret;
+}
+static DEVICE_ATTR_RO(mode);
+
+static ssize_t current_master_show(struct device *dev,
+				   struct device_attribute *da,
+				   char *buf)
+{
+	struct i3c_bus *i3cbus = container_of(dev, struct i3c_bus, dev);
+	ssize_t ret;
+
+	i3c_bus_normaluse_lock(i3cbus);
+	ret = sprintf(buf, "%s\n", dev_name(&i3cbus->cur_master->dev));
+	i3c_bus_normaluse_unlock(i3cbus);
+
+	return ret;
+}
+static DEVICE_ATTR_RO(current_master);
+
+static ssize_t i3c_scl_frequency_show(struct device *dev,
+				      struct device_attribute *da,
+				      char *buf)
+{
+	struct i3c_bus *i3cbus = container_of(dev, struct i3c_bus, dev);
+	ssize_t ret;
+
+	i3c_bus_normaluse_lock(i3cbus);
+	ret = sprintf(buf, "%ld\n", i3cbus->scl_rate.i3c);
+	i3c_bus_normaluse_unlock(i3cbus);
+
+	return ret;
+}
+static DEVICE_ATTR_RO(i3c_scl_frequency);
+
+static ssize_t i2c_scl_frequency_show(struct device *dev,
+				      struct device_attribute *da,
+				      char *buf)
+{
+	struct i3c_bus *i3cbus = container_of(dev, struct i3c_bus, dev);
+	ssize_t ret;
+
+	i3c_bus_normaluse_lock(i3cbus);
+	ret = sprintf(buf, "%ld\n", i3cbus->scl_rate.i2c);
+	i3c_bus_normaluse_unlock(i3cbus);
+
+	return ret;
+}
+static DEVICE_ATTR_RO(i2c_scl_frequency);
+
+static struct attribute *i3c_busdev_attrs[] = {
+	&dev_attr_mode.attr,
+	&dev_attr_current_master.attr,
+	&dev_attr_i3c_scl_frequency.attr,
+	&dev_attr_i2c_scl_frequency.attr,
+	NULL,
+};
+ATTRIBUTE_GROUPS(i3c_busdev);
+
+static void i3c_busdev_release(struct device *dev)
+{
+	struct i3c_bus *bus = container_of(dev, struct i3c_bus, dev);
+
+	while (!list_empty(&bus->devs.i2c)) {
+		struct i2c_device *i2cdev;
+
+		i2cdev = list_first_entry(&bus->devs.i2c, struct i2c_device,
+					  common.node);
+		list_del(&i2cdev->common.node);
+		of_node_put(i2cdev->info.of_node);
+		kfree(i2cdev);
+	}
+
+	while (!list_empty(&bus->devs.i3c)) {
+		struct i3c_device *i3cdev;
+
+		i3cdev = list_first_entry(&bus->devs.i3c, struct i3c_device,
+					  common.node);
+		list_del(&i3cdev->common.node);
+		put_device(&i3cdev->dev);
+	}
+
+	mutex_lock(&i3c_core_lock);
+	idr_remove(&i3c_bus_idr, bus->id);
+	mutex_unlock(&i3c_core_lock);
+
+	of_node_put(bus->dev.of_node);
+	kfree(bus);
+}
+
+static const struct device_type i3c_busdev_type = {
+	.groups	= i3c_busdev_groups,
+};
+
+void i3c_bus_unref(struct i3c_bus *bus)
+{
+	put_device(&bus->dev);
+}
+
+struct i3c_bus *i3c_bus_create(struct device *parent)
+{
+	struct i3c_bus *i3cbus;
+	int ret;
+
+	i3cbus = kzalloc(sizeof(*i3cbus), GFP_KERNEL);
+	if (!i3cbus)
+		return ERR_PTR(-ENOMEM);
+
+	init_rwsem(&i3cbus->lock);
+	INIT_LIST_HEAD(&i3cbus->devs.i2c);
+	INIT_LIST_HEAD(&i3cbus->devs.i3c);
+	i3c_bus_init_addrslots(i3cbus);
+	i3cbus->mode = I3C_BUS_MODE_PURE;
+	i3cbus->dev.parent = parent;
+	i3cbus->dev.of_node = of_node_get(parent->of_node);
+	i3cbus->dev.bus = &i3c_bus_type;
+	i3cbus->dev.type = &i3c_busdev_type;
+	i3cbus->dev.release = i3c_busdev_release;
+
+	mutex_lock(&i3c_core_lock);
+	ret = idr_alloc(&i3c_bus_idr, i3cbus, 0, 0, GFP_KERNEL);
+	mutex_unlock(&i3c_core_lock);
+	if (ret < 0)
+		goto err_free_bus;
+
+	i3cbus->id = ret;
+	device_initialize(&i3cbus->dev);
+
+	return i3cbus;
+
+err_free_bus:
+	kfree(i3cbus);
+
+	return ERR_PTR(ret);
+}
+
+void i3c_bus_unregister(struct i3c_bus *bus)
+{
+	device_unregister(&bus->dev);
+}
+
+int i3c_bus_register(struct i3c_bus *i3cbus)
+{
+	struct i2c_device *i2cdev;
+
+	i3c_bus_for_each_i2cdev(i3cbus, i2cdev) {
+		switch (i2cdev->lvr & I3C_LVR_I2C_INDEX_MASK) {
+		case I3C_LVR_I2C_INDEX(0):
+			if (i3cbus->mode < I3C_BUS_MODE_MIXED_FAST)
+				i3cbus->mode = I3C_BUS_MODE_MIXED_FAST;
+			break;
+
+		case I3C_LVR_I2C_INDEX(1):
+		case I3C_LVR_I2C_INDEX(2):
+			if (i3cbus->mode < I3C_BUS_MODE_MIXED_SLOW)
+				i3cbus->mode = I3C_BUS_MODE_MIXED_SLOW;
+			break;
+
+		default:
+			return -EINVAL;
+		}
+	}
+
+	if (!i3cbus->scl_rate.i3c)
+		i3cbus->scl_rate.i3c = I3C_BUS_TYP_I3C_SCL_RATE;
+
+	if (!i3cbus->scl_rate.i2c) {
+		if (i3cbus->mode == I3C_BUS_MODE_MIXED_SLOW)
+			i3cbus->scl_rate.i2c = I3C_BUS_I2C_FM_SCL_RATE;
+		else
+			i3cbus->scl_rate.i2c = I3C_BUS_I2C_FM_PLUS_SCL_RATE;
+	}
+
+	/*
+	 * I3C/I2C frequency may have been overridden, check that user-provided
+	 * values are not exceeding max possible frequency.
+	 */
+	if (i3cbus->scl_rate.i3c > I3C_BUS_MAX_I3C_SCL_RATE ||
+	    i3cbus->scl_rate.i2c > I3C_BUS_I2C_FM_PLUS_SCL_RATE) {
+		return -EINVAL;
+	}
+
+	dev_set_name(&i3cbus->dev, "i3c-%d", i3cbus->id);
+
+	return device_add(&i3cbus->dev);
+}
+
+static int __init i3c_init(void)
+{
+	return bus_register(&i3c_bus_type);
+}
+subsys_initcall(i3c_init);
+
+static void __exit i3c_exit(void)
+{
+	idr_destroy(&i3c_bus_idr);
+	bus_unregister(&i3c_bus_type);
+}
+module_exit(i3c_exit);
+
+MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
+MODULE_DESCRIPTION("I3C core");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/i3c/device.c b/drivers/i3c/device.c
new file mode 100644
index 000000000000..dcf51150b7cb
--- /dev/null
+++ b/drivers/i3c/device.c
@@ -0,0 +1,344 @@ 
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 Cadence Design Systems Inc.
+ *
+ * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
+ */
+
+#include <linux/slab.h>
+
+#include "internals.h"
+
+/**
+ * i3c_device_do_priv_xfers() - do I3C SDR private transfers directed to a
+ *				specific device
+ *
+ * @dev: device with which the transfers should be done
+ * @xfers: array of transfers
+ * @nxfers: number of transfers
+ *
+ * Initiate one or several private SDR transfers with @dev.
+ *
+ * This function can sleep and thus cannot be called in atomic context.
+ *
+ * Return: 0 in case of success, a negative error core otherwise.
+ */
+int i3c_device_do_priv_xfers(struct i3c_device *dev,
+			     struct i3c_priv_xfer *xfers,
+			     int nxfers)
+{
+	struct i3c_master_controller *master;
+	int i, ret;
+
+	master = i3c_device_get_master(dev);
+	if (!master)
+		return -EINVAL;
+
+	i3c_bus_normaluse_lock(master->bus);
+	for (i = 0; i < nxfers; i++)
+		xfers[i].addr = dev->info.dyn_addr;
+
+	ret = i3c_master_do_priv_xfers_locked(master, xfers, nxfers);
+	i3c_bus_normaluse_unlock(master->bus);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(i3c_device_do_priv_xfers);
+
+/**
+ * i3c_device_send_hdr_cmds() - send HDR commands to a specific device
+ *
+ * @dev: device to which these commands should be sent
+ * @cmds: array of commands
+ * @ncmds: number of commands
+ *
+ * Send one or several HDR commands to @dev.
+ *
+ * This function can sleep and thus cannot be called in atomic context.
+ *
+ * Return: 0 in case of success, a negative error core otherwise.
+ */
+int i3c_device_send_hdr_cmds(struct i3c_device *dev,
+			     struct i3c_hdr_cmd *cmds,
+			     int ncmds)
+{
+	struct i3c_master_controller *master;
+	enum i3c_hdr_mode mode;
+	int ret, i;
+
+	if (ncmds < 1)
+		return 0;
+
+	mode = cmds[0].mode;
+	for (i = 1; i < ncmds; i++) {
+		if (mode != cmds[i].mode)
+			return -EINVAL;
+	}
+
+	master = i3c_device_get_master(dev);
+	if (!master)
+		return -EINVAL;
+
+	i3c_bus_normaluse_lock(master->bus);
+	for (i = 0; i < ncmds; i++)
+		cmds[i].addr = dev->info.dyn_addr;
+
+	ret = i3c_master_send_hdr_cmds_locked(master, cmds, ncmds);
+	i3c_bus_normaluse_unlock(master->bus);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(i3c_device_send_hdr_cmds);
+
+void i3c_device_get_info(struct i3c_device *dev,
+			 struct i3c_device_info *info)
+{
+	if (info)
+		*info = dev->info;
+}
+EXPORT_SYMBOL_GPL(i3c_device_get_info);
+
+/**
+ * i3c_device_disable_ibi() - Disable IBIs coming from a specific device
+ * @dev: device on which IBIs should be disabled
+ *
+ * This function disable IBIs coming from a specific device and wait for
+ * all pending IBIs to be processed.
+ *
+ * Return: 0 in case of success, a negative error core otherwise.
+ */
+int i3c_device_disable_ibi(struct i3c_device *dev)
+{
+	struct i3c_master_controller *master = i3c_device_get_master(dev);
+	int ret;
+
+	mutex_lock(&dev->ibi_lock);
+	if (!dev->ibi) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	ret = master->ops->disable_ibi(master, dev);
+	if (ret)
+		goto out;
+
+	reinit_completion(&dev->ibi->all_ibis_handled);
+	if (atomic_read(&dev->ibi->pending_ibis))
+		wait_for_completion(&dev->ibi->all_ibis_handled);
+
+	dev->ibi->enabled = false;
+
+out:
+	mutex_unlock(&dev->ibi_lock);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(i3c_device_disable_ibi);
+
+/**
+ * i3c_device_enable_ibi() - Enable IBIs coming from a specific device
+ * @dev: device on which IBIs should be enabled
+ *
+ * This function enable IBIs coming from a specific device and wait for
+ * all pending IBIs to be processed. This should be called on a device
+ * where i3c_device_request_ibi() has succeeded.
+ *
+ * Note that IBIs from this device might be received before this function
+ * returns to its caller.
+ *
+ * Return: 0 in case of success, a negative error core otherwise.
+ */
+int i3c_device_enable_ibi(struct i3c_device *dev)
+{
+	struct i3c_master_controller *master = i3c_device_get_master(dev);
+	int ret;
+
+	mutex_lock(&dev->ibi_lock);
+	if (!dev->ibi) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	ret = master->ops->enable_ibi(master, dev);
+	if (!ret)
+		dev->ibi->enabled = true;
+
+out:
+	mutex_unlock(&dev->ibi_lock);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(i3c_device_enable_ibi);
+
+/**
+ * i3c_device_request_ibi() - Request an IBI
+ * @dev: device for which we should enable IBIs
+ * @req: setup requested for this IBI
+ *
+ * This function is responsible for pre-allocating all resources needed to
+ * process IBIs coming from @dev. When this function returns, the IBI is not
+ * enabled until i3c_device_enable_ibi() is called.
+ *
+ * Return: 0 in case of success, a negative error core otherwise.
+ */
+int i3c_device_request_ibi(struct i3c_device *dev,
+			   const struct i3c_ibi_setup *req)
+{
+	struct i3c_master_controller *master = dev->common.master;
+	struct i3c_device_ibi_info *ibi;
+	int ret;
+
+	if (!master->ops->request_ibi)
+		return -ENOTSUPP;
+
+	if (!req->handler || !req->num_slots)
+		return -EINVAL;
+
+	mutex_lock(&dev->ibi_lock);
+	if (dev->ibi) {
+		ret = -EBUSY;
+		goto err_unlock_dev;
+	}
+
+	ibi = kzalloc(sizeof(*ibi), GFP_KERNEL);
+	if (!ibi) {
+		ret = -ENOMEM;
+		goto err_unlock_dev;
+	}
+
+	atomic_set(&ibi->pending_ibis, 0);
+	init_completion(&ibi->all_ibis_handled);
+	ibi->handler = req->handler;
+	ibi->max_payload_len = req->max_payload_len;
+
+	dev->ibi = ibi;
+	ret = master->ops->request_ibi(master, dev, req);
+	if (ret)
+		goto err_free_ibi;
+
+	mutex_unlock(&dev->ibi_lock);
+
+	return 0;
+
+err_free_ibi:
+	mutex_unlock(&dev->ibi_lock);
+	kfree(ibi);
+	dev->ibi = NULL;
+
+err_unlock_dev:
+	mutex_unlock(&dev->ibi_lock);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(i3c_device_request_ibi);
+
+/**
+ * i3c_device_free_ibi() - Free all resources needed for IBI handling
+ * @dev: device on which you want to release IBI resources
+ *
+ * This function is responsible for de-allocating resources previously
+ * allocated by i3c_device_request_ibi(). It should be called after disabling
+ * IBIs with i3c_device_disable_ibi().
+ */
+void i3c_device_free_ibi(struct i3c_device *dev)
+{
+	struct i3c_master_controller *master = dev->common.master;
+
+	mutex_lock(&dev->ibi_lock);
+	if (!dev->ibi)
+		goto out;
+
+	if (WARN_ON(dev->ibi->enabled))
+		BUG_ON(i3c_device_disable_ibi(dev));
+
+	master->ops->free_ibi(master, dev);
+	kfree(dev->ibi);
+	dev->ibi = NULL;
+
+out:
+	mutex_unlock(&dev->ibi_lock);
+}
+EXPORT_SYMBOL_GPL(i3c_device_free_ibi);
+
+/**
+ * i3c_device_match_id() - Find the I3C device ID entry matching an I3C dev
+ * @i3cdev: the I3C device we're searching a match for
+ * @id_table: the I3C device ID table
+ *
+ * Return: a pointer to the first entry matching @i3cdev, or NULL if there's
+ *	   no match.
+ */
+const struct i3c_device_id *
+i3c_device_match_id(struct i3c_device *i3cdev,
+		    const struct i3c_device_id *id_table)
+{
+	const struct i3c_device_id *id;
+
+	/*
+	 * The lower 32bits of the provisional ID is just filled with a random
+	 * value, try to match using DCR info.
+	 */
+	if (!I3C_PID_RND_LOWER_32BITS(i3cdev->info.pid)) {
+		u16 manuf = I3C_PID_MANUF_ID(i3cdev->info.pid);
+		u16 part = I3C_PID_PART_ID(i3cdev->info.pid);
+		u16 ext_info = I3C_PID_EXTRA_INFO(i3cdev->info.pid);
+
+		/* First try to match by manufacturer/part ID. */
+		for (id = id_table; id->match_flags != 0; id++) {
+			if ((id->match_flags & I3C_MATCH_MANUF_AND_PART) !=
+			    I3C_MATCH_MANUF_AND_PART)
+				continue;
+
+			if (manuf != id->manuf_id || part != id->part_id)
+				continue;
+
+			if ((id->match_flags & I3C_MATCH_EXTRA_INFO) &&
+			    ext_info != id->extra_info)
+				continue;
+
+			return id;
+		}
+	}
+
+	/* Fallback to DCR match. */
+	for (id = id_table; id->match_flags != 0; id++) {
+		if ((id->match_flags & I3C_MATCH_DCR) &&
+		    id->dcr == i3cdev->info.dcr)
+			return id;
+	}
+
+	return NULL;
+}
+EXPORT_SYMBOL_GPL(i3c_device_match_id);
+
+/**
+ * i3c_driver_register_with_owner() - register an I3C device driver
+ *
+ * @drv: driver to register
+ * @owner: module that owns this driver
+ *
+ * Register @drv to the core.
+ *
+ * Return: 0 in case of success, a negative error core otherwise.
+ */
+int i3c_driver_register_with_owner(struct i3c_driver *drv, struct module *owner)
+{
+	drv->driver.owner = owner;
+	drv->driver.bus = &i3c_bus_type;
+
+	return driver_register(&drv->driver);
+}
+EXPORT_SYMBOL_GPL(i3c_driver_register_with_owner);
+
+/**
+ * i3c_driver_unregister() - unregister an I3C device driver
+ *
+ * @drv: driver to unregister
+ *
+ * Unregister @drv.
+ */
+void i3c_driver_unregister(struct i3c_driver *drv)
+{
+	driver_unregister(&drv->driver);
+}
+EXPORT_SYMBOL_GPL(i3c_driver_unregister);
diff --git a/drivers/i3c/internals.h b/drivers/i3c/internals.h
new file mode 100644
index 000000000000..798367b318cf
--- /dev/null
+++ b/drivers/i3c/internals.h
@@ -0,0 +1,34 @@ 
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 Cadence Design Systems Inc.
+ *
+ * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
+ */
+
+#ifndef I3C_INTERNALS_H
+#define I3C_INTERNALS_H
+
+#include <linux/i3c/master.h>
+
+extern struct bus_type i3c_bus_type;
+extern const struct device_type i3c_master_type;
+extern const struct device_type i3c_device_type;
+
+void i3c_bus_unref(struct i3c_bus *bus);
+struct i3c_bus *i3c_bus_create(struct device *parent);
+void i3c_bus_unregister(struct i3c_bus *bus);
+int i3c_bus_register(struct i3c_bus *i3cbus);
+int i3c_bus_get_free_addr(struct i3c_bus *bus, u8 start_addr);
+bool i3c_bus_dev_addr_is_avail(struct i3c_bus *bus, u8 addr);
+void i3c_bus_set_addr_slot_status(struct i3c_bus *bus, u16 addr,
+				  enum i3c_addr_slot_status status);
+enum i3c_addr_slot_status i3c_bus_get_addr_slot_status(struct i3c_bus *bus,
+						       u16 addr);
+
+int i3c_master_do_priv_xfers_locked(struct i3c_master_controller *master,
+				    const struct i3c_priv_xfer *xfers,
+				    int nxfers);
+int i3c_master_send_hdr_cmds_locked(struct i3c_master_controller *master,
+				    const struct i3c_hdr_cmd *cmds, int ncmds);
+
+#endif /* I3C_INTERNAL_H */
diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c
new file mode 100644
index 000000000000..1c85abac08d5
--- /dev/null
+++ b/drivers/i3c/master.c
@@ -0,0 +1,1433 @@ 
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 Cadence Design Systems Inc.
+ *
+ * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
+ */
+
+#include <linux/slab.h>
+
+#include "internals.h"
+
+static inline struct i3c_master_controller *
+i2c_adapter_to_i3c_master(struct i2c_adapter *adap)
+{
+	return container_of(adap, struct i3c_master_controller, i2c);
+}
+
+static inline struct i2c_adapter *
+i3c_master_to_i2c_adapter(struct i3c_master_controller *master)
+{
+	return &master->i2c;
+}
+
+static void i3c_i2c_dev_init(struct i3c_master_controller *master,
+			     struct i3c_i2c_dev *dev, bool i2cdev)
+{
+	dev->bus = master->bus;
+	dev->master = master;
+}
+
+static struct i2c_device *
+i3c_master_alloc_i2c_dev(struct i3c_master_controller *master,
+			 const struct i2c_board_info *info, u8 lvr)
+{
+	struct i2c_device *dev;
+
+	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+	if (!dev)
+		return ERR_PTR(-ENOMEM);
+
+	i3c_i2c_dev_init(master, &dev->common, true);
+	dev->info = *info;
+	dev->lvr = lvr;
+	dev->info.of_node = of_node_get(info->of_node);
+	i3c_bus_set_addr_slot_status(master->bus, info->addr,
+				     I3C_ADDR_SLOT_I2C_DEV);
+
+	return dev;
+}
+
+static int i3c_master_send_ccc_cmd_locked(struct i3c_master_controller *master,
+					  struct i3c_ccc_cmd *cmd)
+{
+	if (WARN_ON(!rwsem_is_locked(&master->bus->lock)))
+		return -EINVAL;
+
+	if (!cmd || !master)
+		return -EINVAL;
+
+	if (!master->ops->send_ccc_cmd)
+		return -ENOTSUPP;
+
+	if ((cmd->id & I3C_CCC_DIRECT)) {
+		enum i3c_addr_slot_status status;
+		int i;
+
+		if (!cmd->dests || !cmd->ndests)
+			return -EINVAL;
+
+		for (i = 0; i < cmd->ndests; i++) {
+			status = i3c_bus_get_addr_slot_status(master->bus,
+							cmd->dests[i].addr);
+			if (status != I3C_ADDR_SLOT_I3C_DEV)
+				return -EINVAL;
+		}
+	}
+
+	if (master->ops->supports_ccc_cmd &&
+	    !master->ops->supports_ccc_cmd(master, cmd))
+		return -ENOTSUPP;
+
+	return master->ops->send_ccc_cmd(master, cmd);
+}
+
+int i3c_master_send_hdr_cmds_locked(struct i3c_master_controller *master,
+				    const struct i3c_hdr_cmd *cmds, int ncmds)
+{
+	int i;
+
+	if (!cmds || !master || ncmds <= 0)
+		return -EINVAL;
+
+	if (!master->ops->send_hdr_cmds)
+		return -ENOTSUPP;
+
+	for (i = 0; i < ncmds; i++) {
+		if (!(master->this->info.hdr_cap & BIT(cmds->mode)))
+			return -ENOTSUPP;
+	}
+
+	return master->ops->send_hdr_cmds(master, cmds, ncmds);
+}
+
+/**
+ * i3c_master_send_hdr_cmds() - send HDR commands on the I3C bus
+ * @master: master used to send frames on the bus
+ * @cmds: array of HDR commands
+ * @ncmds: number of commands to send
+ *
+ * Send one or several HDR commands.
+ *
+ * This function can sleep and thus cannot be called in atomic context.
+ *
+ * Return: 0 in case of success, a negative error code otherwise.
+ */
+int i3c_master_send_hdr_cmds(struct i3c_master_controller *master,
+			     const struct i3c_hdr_cmd *cmds, int ncmds)
+{
+	int ret;
+
+	i3c_bus_normaluse_lock(master->bus);
+	ret = i3c_master_send_hdr_cmds_locked(master, cmds, ncmds);
+	i3c_bus_normaluse_unlock(master->bus);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(i3c_master_send_hdr_cmds);
+
+int i3c_master_do_priv_xfers_locked(struct i3c_master_controller *master,
+				    const struct i3c_priv_xfer *xfers,
+				    int nxfers)
+{
+	int i;
+
+	if (!xfers || !master || nxfers <= 0)
+		return -EINVAL;
+
+	if (!master->ops->priv_xfers)
+		return -ENOTSUPP;
+
+	for (i = 0; i < nxfers; i++) {
+		enum i3c_addr_slot_status status;
+
+		status = i3c_bus_get_addr_slot_status(master->bus,
+						      xfers[i].addr);
+		if (status != I3C_ADDR_SLOT_I3C_DEV)
+			return -EINVAL;
+	}
+
+	return master->ops->priv_xfers(master, xfers, nxfers);
+}
+
+/**
+ * i3c_master_do_priv_xfers() - do SDR private transfers on the I3C bus
+ * @master: master used to send frames on the bus
+ * @xfers: array of SDR private transfers
+ * @nxfers: number of transfers
+ *
+ * Do one or several private SDR I3C transfers.
+ *
+ * This function can sleep and thus cannot be called in atomic context.
+ *
+ * Return: 0 in case of success, a negative error code otherwise.
+ */
+int i3c_master_do_priv_xfers(struct i3c_master_controller *master,
+			     const struct i3c_priv_xfer *xfers,
+			     int nxfers)
+{
+	int ret;
+
+	i3c_bus_normaluse_lock(master->bus);
+	ret = i3c_master_do_priv_xfers_locked(master, xfers, nxfers);
+	i3c_bus_normaluse_unlock(master->bus);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(i3c_master_do_priv_xfers);
+
+/**
+ * i3c_master_do_i2c_xfers() - do I2C transfers on the I3C bus
+ * @master: master used to send frames on the bus
+ * @xfers: array of I2C transfers
+ * @nxfers: number of transfers
+ *
+ * Does one or several I2C transfers.
+ *
+ * This function can sleep and thus cannot be called in atomic context.
+ *
+ * Return: 0 in case of success, a negative error code otherwise.
+ */
+int i3c_master_do_i2c_xfers(struct i3c_master_controller *master,
+			    const struct i2c_msg *xfers,
+			    int nxfers)
+{
+	int ret, i;
+
+	if (!xfers || !master || nxfers <= 0)
+		return -EINVAL;
+
+	if (!master->ops->i2c_xfers)
+		return -ENOTSUPP;
+
+	i3c_bus_normaluse_lock(master->bus);
+
+	for (i = 0; i < nxfers; i++) {
+		enum i3c_addr_slot_status status;
+
+		status = i3c_bus_get_addr_slot_status(master->bus,
+						      xfers[i].addr);
+		if (status != I3C_ADDR_SLOT_I2C_DEV) {
+			ret = -EINVAL;
+			goto out;
+		}
+	}
+
+	ret = master->ops->i2c_xfers(master, xfers, nxfers);
+
+out:
+	i3c_bus_normaluse_unlock(master->bus);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(i3c_master_do_i2c_xfers);
+
+/**
+ * i3c_master_get_free_addr() - get a free address on the bus
+ * @master: I3C master object
+ * @start_addr: where to start searching
+ *
+ * This function must be called with the bus lock held in write mode.
+ *
+ * Return: the first free address starting at @start_addr (included) or -ENOMEM
+ * if there's no more address available.
+ */
+int i3c_master_get_free_addr(struct i3c_master_controller *master,
+			     u8 start_addr)
+{
+	return i3c_bus_get_free_addr(master->bus, start_addr);
+}
+EXPORT_SYMBOL_GPL(i3c_master_get_free_addr);
+
+static void i3c_device_release(struct device *dev)
+{
+	struct i3c_device *i3cdev = dev_to_i3cdev(dev);
+
+	of_node_put(dev->of_node);
+	kfree(i3cdev);
+}
+
+static struct i3c_device *
+i3c_master_alloc_i3c_dev(struct i3c_master_controller *master,
+			 const struct i3c_device_info *info,
+			 const struct device_type *devtype)
+{
+	struct i3c_device *dev;
+
+	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+	if (!dev)
+		return ERR_PTR(-ENOMEM);
+
+	i3c_i2c_dev_init(master, &dev->common, false);
+	dev->dev.parent = &master->bus->dev;
+	dev->dev.type = devtype;
+	dev->dev.bus = &i3c_bus_type;
+	dev->dev.release = i3c_device_release;
+	dev->info = *info;
+	dev->new = true;
+	mutex_init(&dev->ibi_lock);
+	dev_set_name(&dev->dev, "%d-%llx", master->bus->id, info->pid);
+
+	device_initialize(&dev->dev);
+
+	return dev;
+}
+
+/**
+ * i3c_master_set_info() - set master device information
+ * @master: master used to send frames on the bus
+ * @info: I3C device information
+ *
+ * Set master device info. This should be done in
+ * &i3c_master_controller_ops->bus_init().
+ *
+ * Not all &i3c_device_info fields are meaningful for a master device.
+ * Here is a list of fields that should be properly filled:
+ *
+ * - &i3c_device_info->dyn_addr
+ * - &i3c_device_info->bcr
+ * - &i3c_device_info->dcr
+ * - &i3c_device_info->pid
+ * - &i3c_device_info->hdr_cap if %I3C_BCR_HDR_CAP bit is set in
+ *   &i3c_device_info->bcr
+ *
+ * This function must be called with the bus lock held in write mode.
+ *
+ * Return: 0 if @info contains valid information (not every piece of
+ * information can be checked, but we can at least make sure @info->dyn_addr
+ * and @info->bcr are correct), -EINVAL otherwise.
+ */
+int i3c_master_set_info(struct i3c_master_controller *master,
+			const struct i3c_device_info *info)
+{
+	struct i3c_device *i3cdev;
+
+	if (!i3c_bus_dev_addr_is_avail(master->bus, info->dyn_addr))
+		return -EINVAL;
+
+	if (I3C_BCR_DEVICE_ROLE(info->bcr) == I3C_BCR_I3C_MASTER &&
+	    master->secondary)
+		return -EINVAL;
+
+	if (master->this)
+		return -EINVAL;
+
+	i3cdev = i3c_master_alloc_i3c_dev(master, info,	&i3c_master_type);
+	if (IS_ERR(i3cdev))
+		return PTR_ERR(i3cdev);
+
+	master->this = i3cdev;
+	master->bus->cur_master = master->this;
+	list_add_tail(&i3cdev->common.node, &master->bus->devs.i3c);
+	i3c_bus_set_addr_slot_status(master->bus, info->dyn_addr,
+				     I3C_ADDR_SLOT_I3C_DEV);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(i3c_master_set_info);
+
+/**
+ * i3c_master_rstdaa_locked() - reset dev(s) dynamic address
+ * @master: master used to send frames on the bus
+ * @addr: a valid I3C device address or %I3C_BROADCAST_ADDR
+ *
+ * Send a RSTDAA CCC command to ask a specific slave (or all slave if @addr is
+ * %I3C_BROADCAST_ADDR) to drop their dynamic address.
+ *
+ * This function must be called with the bus lock held in write mode.
+ *
+ * Return: 0 in case of success, a negative error code otherwise.
+ */
+int i3c_master_rstdaa_locked(struct i3c_master_controller *master, u8 addr)
+{
+	struct i3c_ccc_cmd_dest dest = { };
+	struct i3c_ccc_cmd cmd = { };
+	enum i3c_addr_slot_status addrstat;
+	int ret;
+
+	if (!master)
+		return -EINVAL;
+
+	addrstat = i3c_bus_get_addr_slot_status(master->bus, addr);
+	if (addr != I3C_BROADCAST_ADDR && addrstat != I3C_ADDR_SLOT_I3C_DEV)
+		return -EINVAL;
+
+	dest.addr = addr;
+	cmd.dests = &dest;
+	cmd.ndests = 1;
+	cmd.rnw = false;
+	cmd.id = I3C_CCC_RSTDAA(addr == I3C_BROADCAST_ADDR);
+
+	ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(i3c_master_rstdaa_locked);
+
+/**
+ * i3c_master_entdaa_locked() - start a DAA (Dynamic Address Assignment)
+ *				procedure
+ * @master: master used to send frames on the bus
+ *
+ * Send a ENTDAA CCC command to start a DAA procedure.
+ *
+ * Note that this function only sends the ENTDAA CCC command, all the logic
+ * behind dynamic address assignment has to be handled in the I3C master
+ * driver.
+ *
+ * This function must be called with the bus lock held in write mode.
+ *
+ * Return: 0 in case of success, a negative error code otherwise.
+ */
+int i3c_master_entdaa_locked(struct i3c_master_controller *master)
+{
+	struct i3c_ccc_cmd_dest dest = { };
+	struct i3c_ccc_cmd cmd = { };
+	int ret;
+
+	dest.addr = I3C_BROADCAST_ADDR;
+	cmd.dests = &dest;
+	cmd.ndests = 1;
+	cmd.rnw = false;
+	cmd.id = I3C_CCC_ENTDAA;
+
+	ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(i3c_master_entdaa_locked);
+
+/**
+ * i3c_master_disec_locked() - send a DISEC CCC command
+ * @master: master used to send frames on the bus
+ * @addr: a valid I3C slave address or %I3C_BROADCAST_ADDR
+ * @evts: events to disable
+ *
+ * Send a DISEC CCC command to disable some or all events coming from a
+ * specific slave, or all devices if @addr is %I3C_BROADCAST_ADDR.
+ *
+ * This function must be called with the bus lock held in write mode.
+ *
+ * Return: 0 in case of success, a negative error code otherwise.
+ */
+int i3c_master_disec_locked(struct i3c_master_controller *master, u8 addr,
+			    const struct i3c_ccc_events *evts)
+{
+	struct i3c_ccc_events events = *evts;
+	struct i3c_ccc_cmd_dest dest = {
+		.addr = addr,
+		.payload.len = sizeof(events),
+		.payload.data = &events,
+	};
+	struct i3c_ccc_cmd cmd = {
+		.id = I3C_CCC_DISEC(addr == I3C_BROADCAST_ADDR),
+		.dests = &dest,
+		.ndests = 1,
+	};
+
+	return i3c_master_send_ccc_cmd_locked(master, &cmd);
+}
+EXPORT_SYMBOL_GPL(i3c_master_disec_locked);
+
+/**
+ * i3c_master_enec_locked() - send an ENEC CCC command
+ * @master: master used to send frames on the bus
+ * @addr: a valid I3C slave address or %I3C_BROADCAST_ADDR
+ * @evts: events to disable
+ *
+ * Sends an ENEC CCC command to enable some or all events coming from a
+ * specific slave, or all devices if @addr is %I3C_BROADCAST_ADDR.
+ *
+ * This function must be called with the bus lock held in write mode.
+ *
+ * Return: 0 in case of success, a negative error code otherwise.
+ */
+int i3c_master_enec_locked(struct i3c_master_controller *master, u8 addr,
+			   const struct i3c_ccc_events *evts)
+{
+	struct i3c_ccc_events events = *evts;
+	struct i3c_ccc_cmd_dest dest = {
+		.addr = addr,
+		.payload.len = sizeof(events),
+		.payload.data = &events,
+	};
+	struct i3c_ccc_cmd cmd = {
+		.id = I3C_CCC_ENEC(addr == I3C_BROADCAST_ADDR),
+		.dests = &dest,
+		.ndests = 1,
+	};
+
+	return i3c_master_send_ccc_cmd_locked(master, &cmd);
+}
+EXPORT_SYMBOL_GPL(i3c_master_enec_locked);
+
+/**
+ * i3c_master_defslvs_locked() - send a DEFSLVS CCC command
+ * @master: master used to send frames on the bus
+ *
+ * Send a DEFSLVS CCC command containing all the devices known to the @master.
+ * This is useful when you have secondary masters on the bus to propagate
+ * device information.
+ *
+ * This should be called after all I3C devices have been discovered (in other
+ * words, after the DAA procedure has finished) and instantiated in
+ * i3c_master_controller_ops->bus_init().
+ * It should also be called if a master ACKed an Hot-Join request and assigned
+ * a dynamic address to the device joining the bus.
+ *
+ * This function must be called with the bus lock held in write mode.
+ *
+ * Return: 0 in case of success, a negative error code otherwise.
+ */
+int i3c_master_defslvs_locked(struct i3c_master_controller *master)
+{
+	struct i3c_ccc_cmd_dest dest = {
+		.addr = I3C_BROADCAST_ADDR,
+	};
+	struct i3c_ccc_cmd cmd = {
+		.id = I3C_CCC_DEFSLVS,
+		.dests = &dest,
+		.ndests = 1,
+	};
+	struct i3c_ccc_defslvs *defslvs;
+	struct i3c_ccc_dev_desc *desc;
+	struct i3c_device *i3cdev;
+	struct i2c_device *i2cdev;
+	struct i3c_bus *bus;
+	bool send = false;
+	int ndevs = 0, ret;
+
+	if (!master)
+		return -EINVAL;
+
+	bus = i3c_master_get_bus(master);
+	i3c_bus_for_each_i3cdev(bus, i3cdev) {
+		ndevs++;
+		if (I3C_BCR_DEVICE_ROLE(i3cdev->info.bcr) == I3C_BCR_I3C_MASTER)
+			send = true;
+	}
+
+	/* No other master on the bus, skip DEFSLVS. */
+	if (!send)
+		return 0;
+
+	i3c_bus_for_each_i2cdev(bus, i2cdev)
+		ndevs++;
+
+	dest.payload.len = sizeof(*defslvs) +
+			   ((ndevs - 1) * sizeof(struct i3c_ccc_dev_desc));
+	defslvs = kzalloc(dest.payload.len, GFP_KERNEL);
+	if (!defslvs)
+		return -ENOMEM;
+
+	dest.payload.data = defslvs;
+
+	defslvs->count = ndevs;
+	defslvs->master.bcr = master->this->info.bcr;
+	defslvs->master.dcr = master->this->info.dcr;
+	defslvs->master.dyn_addr = master->this->info.dyn_addr;
+	defslvs->master.static_addr = I3C_BROADCAST_ADDR;
+
+	desc = defslvs->slaves;
+	i3c_bus_for_each_i2cdev(bus, i2cdev) {
+		desc->lvr = i2cdev->lvr;
+		desc->static_addr = i2cdev->info.addr;
+		desc++;
+	}
+
+	i3c_bus_for_each_i3cdev(bus, i3cdev) {
+		/* Skip the I3C dev representing this master. */
+		if (i3cdev == master->this)
+			continue;
+
+		desc->bcr = i3cdev->info.bcr;
+		desc->dcr = i3cdev->info.dcr;
+		desc->dyn_addr = i3cdev->info.dyn_addr;
+		desc->static_addr = i3cdev->info.static_addr;
+		desc++;
+	}
+
+	ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
+	kfree(defslvs);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(i3c_master_defslvs_locked);
+
+static int i3c_master_getmrl_locked(struct i3c_master_controller *master,
+				    struct i3c_device_info *info)
+{
+	struct i3c_ccc_mrl mrl;
+	struct i3c_ccc_cmd_dest dest = {
+		.addr = info->dyn_addr,
+		.payload.len = sizeof(mrl),
+		.payload.data = &mrl,
+	};
+	struct i3c_ccc_cmd cmd = {
+		.rnw = true,
+		.id = I3C_CCC_GETMRL,
+		.dests = &dest,
+		.ndests = 1,
+	};
+	int ret;
+
+	/*
+	 * When the device does not have IBI payload GETMRL only returns 2
+	 * bytes of data.
+	 */
+	if (!(info->bcr & I3C_BCR_IBI_PAYLOAD))
+		dest.payload.len -= 1;
+
+	ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
+	if (ret)
+		return ret;
+
+	if (dest.payload.len != sizeof(mrl))
+		return -EIO;
+
+	info->max_read_len = be16_to_cpu(mrl.read_len);
+
+	if (info->bcr & I3C_BCR_IBI_PAYLOAD)
+		info->max_ibi_len = mrl.ibi_len;
+
+	return 0;
+}
+
+static int i3c_master_getmwl_locked(struct i3c_master_controller *master,
+				    struct i3c_device_info *info)
+{
+	struct i3c_ccc_mwl mwl;
+	struct i3c_ccc_cmd_dest dest = {
+		.addr = info->dyn_addr,
+		.payload.len = sizeof(mwl),
+		.payload.data = &mwl,
+	};
+	struct i3c_ccc_cmd cmd = {
+		.rnw = true,
+		.id = I3C_CCC_GETMWL,
+		.dests = &dest,
+		.ndests = 1,
+	};
+	int ret;
+
+	ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
+	if (ret)
+		return ret;
+
+	if (dest.payload.len != sizeof(mwl))
+		return -EIO;
+
+	info->max_write_len = be16_to_cpu(mwl.len);
+
+	return 0;
+}
+
+static int i3c_master_getmxds_locked(struct i3c_master_controller *master,
+				     struct i3c_device_info *info)
+{
+	struct i3c_ccc_getmxds getmaxds;
+	struct i3c_ccc_cmd_dest dest = {
+		.addr = info->dyn_addr,
+		.payload.len = sizeof(getmaxds),
+		.payload.data = &getmaxds,
+	};
+	struct i3c_ccc_cmd cmd = {
+		.rnw = true,
+		.id = I3C_CCC_GETMXDS,
+		.dests = &dest,
+		.ndests = 1,
+	};
+	int ret;
+
+	ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
+	if (ret)
+		return ret;
+
+	if (dest.payload.len != 2 && dest.payload.len != 5)
+		return -EIO;
+
+	info->max_read_ds = getmaxds.maxrd;
+	info->max_read_ds = getmaxds.maxwr;
+	if (dest.payload.len == 5)
+		info->max_read_turnaround = getmaxds.maxrdturn[0] |
+					    ((u32)getmaxds.maxrdturn[1] << 8) |
+					    ((u32)getmaxds.maxrdturn[2] << 16);
+
+	return 0;
+}
+
+static int i3c_master_gethdrcap_locked(struct i3c_master_controller *master,
+				       struct i3c_device_info *info)
+{
+	struct i3c_ccc_gethdrcap gethdrcap;
+	struct i3c_ccc_cmd_dest dest = {
+		.addr = info->dyn_addr,
+		.payload.len = sizeof(gethdrcap),
+		.payload.data = &gethdrcap,
+	};
+	struct i3c_ccc_cmd cmd = {
+		.rnw = true,
+		.id = I3C_CCC_GETHDRCAP,
+		.dests = &dest,
+		.ndests = 1,
+	};
+	int ret;
+
+	ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
+	if (ret)
+		return ret;
+
+	if (dest.payload.len != 1)
+		return -EIO;
+
+	info->hdr_cap = gethdrcap.modes;
+
+	return 0;
+}
+
+static int i3c_master_getpid_locked(struct i3c_master_controller *master,
+				    struct i3c_device_info *info)
+{
+	struct i3c_ccc_getpid getpid;
+	struct i3c_ccc_cmd_dest dest = {
+		.addr = info->dyn_addr,
+		.payload.len = sizeof(struct i3c_ccc_getpid),
+		.payload.data = &getpid,
+	};
+	struct i3c_ccc_cmd cmd = {
+		.rnw = true,
+		.id = I3C_CCC_GETPID,
+		.dests = &dest,
+		.ndests = 1,
+	};
+	int ret, i;
+
+	ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
+	if (ret)
+		return ret;
+
+	info->pid = 0;
+	for (i = 0; i < sizeof(getpid.pid); i++) {
+		int sft = (sizeof(getpid.pid) - i - 1) * 8;
+
+		info->pid |= (u64)getpid.pid[i] << sft;
+	}
+
+	return 0;
+}
+
+static int i3c_master_getbcr_locked(struct i3c_master_controller *master,
+				    struct i3c_device_info *info)
+{
+	struct i3c_ccc_getbcr getbcr;
+	struct i3c_ccc_cmd_dest dest = {
+		.addr = info->dyn_addr,
+		.payload.len = sizeof(struct i3c_ccc_getbcr),
+		.payload.data = &getbcr,
+	};
+	struct i3c_ccc_cmd cmd = {
+		.rnw = true,
+		.id = I3C_CCC_GETBCR,
+		.dests = &dest,
+		.ndests = 1,
+	};
+	int ret;
+
+	ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
+	if (ret)
+		return ret;
+
+	info->bcr = getbcr.bcr;
+
+	return 0;
+}
+
+static int i3c_master_getdcr_locked(struct i3c_master_controller *master,
+				    struct i3c_device_info *info)
+{
+	struct i3c_ccc_getdcr getdcr;
+	struct i3c_ccc_cmd_dest dest = {
+		.addr = info->dyn_addr,
+		.payload.len = sizeof(struct i3c_ccc_getdcr),
+		.payload.data = &getdcr,
+	};
+	struct i3c_ccc_cmd cmd = {
+		.rnw = true,
+		.id = I3C_CCC_GETDCR,
+		.dests = &dest,
+		.ndests = 1,
+	};
+	int ret;
+
+	ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
+	if (ret)
+		return ret;
+
+	info->dcr = getdcr.dcr;
+
+	return 0;
+}
+
+static int i3c_master_retrieve_dev_info(struct i3c_master_controller *master,
+					struct i3c_device_info *info, u8 addr)
+{
+	enum i3c_addr_slot_status slot_status;
+	int ret;
+
+	if (!master || !info)
+		return -EINVAL;
+
+	memset(info, 0, sizeof(*info));
+	info->dyn_addr = addr;
+
+	slot_status = i3c_bus_get_addr_slot_status(master->bus,
+						   info->dyn_addr);
+	if (slot_status == I3C_ADDR_SLOT_RSVD ||
+	    slot_status == I3C_ADDR_SLOT_I2C_DEV)
+		return -EINVAL;
+
+	ret = i3c_master_getpid_locked(master, info);
+	if (ret)
+		return ret;
+
+	ret = i3c_master_getbcr_locked(master, info);
+	if (ret)
+		return ret;
+
+	ret = i3c_master_getdcr_locked(master, info);
+	if (ret)
+		return ret;
+
+	if (info->bcr & I3C_BCR_MAX_DATA_SPEED_LIM) {
+		ret = i3c_master_getmxds_locked(master, info);
+		if (ret)
+			return ret;
+	}
+
+	if (info->bcr & I3C_BCR_IBI_PAYLOAD)
+		info->max_ibi_len = 1;
+
+	i3c_master_getmrl_locked(master, info);
+	i3c_master_getmwl_locked(master, info);
+
+	if (info->bcr & I3C_BCR_HDR_CAP) {
+		ret = i3c_master_gethdrcap_locked(master, info);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+/**
+ * i3c_master_add_i3c_dev_locked() - add an I3C slave to the bus
+ * @master: master used to send frames on the bus
+ * @addr: I3C slave dynamic address assigned to the device
+ *
+ * This function is instantiating an I3C device object and adding it to the
+ * I3C device list. All device information are automatically retrieved using
+ * standard CCC commands.
+ *
+ * The I3C device object is returned in case the master wants to attach
+ * private data to it using i3c_device_set_master_data().
+ *
+ * This function must be called with the bus lock held in write mode.
+ *
+ * Return: a pointer to a &struct i3c_device object in case of success,
+ * an ERR_PTR() otherwise.
+ */
+struct i3c_device *
+i3c_master_add_i3c_dev_locked(struct i3c_master_controller *master, u8 addr)
+{
+	enum i3c_addr_slot_status status;
+	struct i3c_device *i3cdev;
+	struct i3c_device_info info;
+	int ret;
+
+	if (!master)
+		return ERR_PTR(-EINVAL);
+
+	status = i3c_bus_get_addr_slot_status(master->bus, addr);
+	if (status != I3C_ADDR_SLOT_FREE)
+		return ERR_PTR(-EINVAL);
+
+	i3c_bus_set_addr_slot_status(master->bus, addr, I3C_ADDR_SLOT_I3C_DEV);
+
+	ret = i3c_master_retrieve_dev_info(master, &info, addr);
+	if (ret)
+		goto err_release_addr;
+
+	i3cdev = i3c_master_alloc_i3c_dev(master, &info, &i3c_device_type);
+	if (IS_ERR(i3cdev)) {
+		ret = PTR_ERR(i3cdev);
+		goto err_release_addr;
+	}
+
+	list_add_tail(&i3cdev->common.node, &master->bus->devs.i3c);
+
+	return i3cdev;
+
+err_release_addr:
+	i3c_bus_set_addr_slot_status(master->bus, addr, I3C_ADDR_SLOT_FREE);
+
+	return ERR_PTR(ret);
+}
+EXPORT_SYMBOL_GPL(i3c_master_add_i3c_dev_locked);
+
+static int of_i3c_master_add_dev(struct i3c_master_controller *master,
+				 struct device_node *node)
+{
+	struct device *dev = master->parent;
+	struct i2c_board_info info = { };
+	struct i2c_device *i2cdev;
+	u32 lvr, addr;
+	int ret;
+
+	if (!master || !node)
+		return -EINVAL;
+
+	/*
+	 * This node is not describing an I2C device, skip it.
+	 * We only add I2C devices here (i.e. nodes with an i3c-lvr property).
+	 * I3C devices will be discovered during DAA, even if they have a
+	 * static address.
+	 */
+	if (of_property_read_u32(node, "reg", &addr) ||
+	    of_property_read_u32(node, "i3c-lvr", &lvr))
+		return 0;
+
+	ret = of_i2c_get_board_info(master->parent, node, &info);
+	if (ret)
+		return ret;
+
+	/*
+	 * We do not register the I2C device here, because the bus is not
+	 * necessarily ready to transmit I2C frames, and the I2C adapter has
+	 * not been registered yet.
+	 * This is done in i3c_master_i2c_adapter_init() once everything is
+	 * ready.
+	 */
+	i2cdev = i3c_master_alloc_i2c_dev(master, &info, lvr);
+	if (IS_ERR(i2cdev)) {
+		dev_err(dev, "Failed to allocate device %02x\n", addr);
+		return ret;
+	}
+
+	if (lvr & I3C_LVR_I2C_FM_MODE)
+		master->bus->scl_rate.i2c = I3C_BUS_I2C_FM_SCL_RATE;
+
+	list_add_tail(&i2cdev->common.node, &master->bus->devs.i2c);
+
+	return 0;
+}
+
+static int of_populate_i3c_bus(struct i3c_master_controller *master)
+{
+	struct device *dev = &master->bus->dev;
+	struct device_node *i3cbus_np = dev->of_node;
+	struct device_node *node;
+	int ret;
+	u32 val;
+
+	if (!i3cbus_np)
+		return 0;
+
+	for_each_available_child_of_node(i3cbus_np, node) {
+		ret = of_i3c_master_add_dev(master, node);
+		if (ret)
+			return ret;
+	}
+
+	/*
+	 * The user might want to limit I2C and I3C speed in case some devices
+	 * on the bus are not supporting typical rates, or if the bus topology
+	 * prevents it from using max possible rate.
+	 */
+	if (!of_property_read_u32(i3cbus_np, "i2c-scl-frequency", &val))
+		master->bus->scl_rate.i2c = val;
+
+	if (!of_property_read_u32(i3cbus_np, "i3c-scl-frequency", &val))
+		master->bus->scl_rate.i3c = val;
+
+	return 0;
+}
+
+static int i3c_master_i2c_adapter_xfer(struct i2c_adapter *adap,
+				       struct i2c_msg *xfers, int nxfers)
+{
+	struct i3c_master_controller *master = i2c_adapter_to_i3c_master(adap);
+	int i, ret;
+
+	for (i = 0; i < nxfers; i++) {
+		enum i3c_addr_slot_status status;
+
+		status = i3c_bus_get_addr_slot_status(master->bus,
+						      xfers[i].addr);
+		if (status != I3C_ADDR_SLOT_I2C_DEV)
+			return -EINVAL;
+	}
+
+	ret = i3c_master_do_i2c_xfers(master, xfers, nxfers);
+	if (ret)
+		return ret;
+
+	return nxfers;
+}
+
+static u32 i3c_master_i2c_functionalities(struct i2c_adapter *adap)
+{
+	return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR;
+}
+
+static const struct i2c_algorithm i3c_master_i2c_algo = {
+	.master_xfer = i3c_master_i2c_adapter_xfer,
+	.functionality = i3c_master_i2c_functionalities,
+};
+
+static int i3c_master_i2c_adapter_init(struct i3c_master_controller *master)
+{
+	struct i2c_adapter *adap = i3c_master_to_i2c_adapter(master);
+	struct i2c_device *i2cdev;
+	int ret;
+
+	adap->dev.parent = master->parent;
+	adap->owner = master->parent->driver->owner;
+	adap->algo = &i3c_master_i2c_algo;
+	strncpy(adap->name, dev_name(master->parent), sizeof(adap->name));
+
+	/* FIXME: Should we allow i3c masters to override these values? */
+	adap->timeout = 1000;
+	adap->retries = 3;
+
+	ret = i2c_add_adapter(adap);
+	if (ret)
+		return ret;
+
+	/*
+	 * We silently ignore failures here. The bus should keep working
+	 * correctly even if one or more i2c devices are not registered.
+	 */
+	i3c_bus_for_each_i2cdev(master->bus, i2cdev)
+		i2cdev->client = i2c_new_device(adap, &i2cdev->info);
+
+	return 0;
+}
+
+static void i3c_master_i2c_adapter_cleanup(struct i3c_master_controller *master)
+{
+	i2c_del_adapter(&master->i2c);
+}
+
+static void i3c_master_unregister_i3c_devs(struct i3c_master_controller *master)
+{
+	struct i3c_device *i3cdev;
+
+	i3c_bus_for_each_i3cdev(master->bus, i3cdev) {
+		if (device_is_registered(&i3cdev->dev))
+			device_del(&i3cdev->dev);
+	}
+}
+
+/**
+ * i3c_device_queue_ibi() - Queue an IBI
+ * @dev: the device this IBI is coming from
+ * @slot: the IBI slot used to store the payload
+ *
+ * Queue an IBI to the controller workqueue. The IBI handler attached to
+ * the dev will be called from a workqueue context.
+ */
+void i3c_device_queue_ibi(struct i3c_device *dev, struct i3c_ibi_slot *slot)
+{
+	atomic_inc(&dev->ibi->pending_ibis);
+	queue_work(dev->common.master->wq, &slot->work);
+}
+EXPORT_SYMBOL_GPL(i3c_device_queue_ibi);
+
+static void i3c_device_handle_ibi(struct work_struct *work)
+{
+	struct i3c_ibi_slot *slot = container_of(work, struct i3c_ibi_slot,
+						 work);
+	struct i3c_device *dev = slot->dev;
+	struct i3c_master_controller *master = i3c_device_get_master(dev);
+	struct i3c_ibi_payload payload;
+
+	payload.data = slot->data;
+	payload.len = slot->len;
+
+	dev->ibi->handler(dev, &payload);
+	master->ops->recycle_ibi_slot(master, dev, slot);
+	if (atomic_dec_and_test(&dev->ibi->pending_ibis))
+		complete(&dev->ibi->all_ibis_handled);
+}
+
+/**
+ * i3c_device_init_ibi_slot() - Initialize an IBI slot
+ * @dev: the device this IBI slot will be attached to
+ * @slot: the IBI slot to initialze
+ *
+ * Initialize an IBI slot so that it can later be queued using
+ * i3c_device_queue_ibi(). This should be done at allocation time when the IBI
+ * slot pool is created.
+ */
+void i3c_device_init_ibi_slot(struct i3c_device *dev,
+			      struct i3c_ibi_slot *slot)
+{
+	slot->dev = dev;
+	INIT_WORK(&slot->work, i3c_device_handle_ibi);
+}
+EXPORT_SYMBOL_GPL(i3c_device_init_ibi_slot);
+
+struct i3c_generic_ibi_slot {
+	struct list_head node;
+	struct i3c_ibi_slot base;
+};
+
+struct i3c_generic_ibi_pool {
+	spinlock_t lock;
+	unsigned int num_slots;
+	struct list_head free_slots;
+	struct list_head pending;
+};
+
+/**
+ * i3c_generic_ibi_free_pool() - Free a generic IBI pool
+ * @pool: the IBI pool to free
+ *
+ * Free all IBI slots allated by a generic IBI pool.
+ */
+void i3c_generic_ibi_free_pool(struct i3c_generic_ibi_pool *pool)
+{
+	struct i3c_generic_ibi_slot *slot;
+	unsigned int nslots = 0;
+
+	while (!list_empty(&pool->free_slots)) {
+		slot = list_first_entry(&pool->free_slots,
+					struct i3c_generic_ibi_slot, node);
+		list_del(&slot->node);
+		kfree(slot->base.data);
+		kfree(slot);
+		nslots++;
+	}
+
+	/*
+	 * If the number of freed slots is not equal to the number of allocated
+	 * slots we have a leak somewhere.
+	 */
+	WARN_ON(nslots != pool->num_slots);
+}
+EXPORT_SYMBOL_GPL(i3c_generic_ibi_free_pool);
+
+/**
+ * i3c_generic_ibi_alloc_pool() - Create a generic IBI pool
+ * @dev: the device this pool will be used for
+ * @req: IBI setup request describing what the device driver expects
+ *
+ * Create a generic IBI pool based on the information provided in @req.
+ *
+ * Return: a valid IBI pool in case of success, an ERR_PTR() otherwise.
+ */
+struct i3c_generic_ibi_pool *
+i3c_generic_ibi_alloc_pool(struct i3c_device *dev,
+			   const struct i3c_ibi_setup *req)
+{
+	struct i3c_generic_ibi_pool *pool;
+	struct i3c_generic_ibi_slot *slot;
+	unsigned int i;
+	int ret;
+
+	pool = kzalloc(sizeof(*pool), GFP_KERNEL);
+	if (!pool)
+		return ERR_PTR(-ENOMEM);
+
+	spin_lock_init(&pool->lock);
+	INIT_LIST_HEAD(&pool->free_slots);
+	INIT_LIST_HEAD(&pool->pending);
+
+	for (i = 0; i < req->num_slots; i++) {
+		slot = kzalloc(sizeof(*slot), GFP_KERNEL);
+		if (!slot)
+			return ERR_PTR(-ENOMEM);
+
+		i3c_device_init_ibi_slot(dev, &slot->base);
+
+		if (req->max_payload_len) {
+			slot->base.data = kzalloc(req->max_payload_len,
+						  GFP_KERNEL);
+			if (!slot->base.data) {
+				kfree(slot);
+				ret = -ENOMEM;
+				goto err_free_pool;
+			}
+		}
+
+		list_add_tail(&slot->node, &pool->free_slots);
+		pool->num_slots++;
+	}
+
+	return pool;
+
+err_free_pool:
+	i3c_generic_ibi_free_pool(pool);
+	return ERR_PTR(ret);
+}
+EXPORT_SYMBOL_GPL(i3c_generic_ibi_alloc_pool);
+
+/**
+ * i3c_generic_ibi_get_free_slot() - Get a free slot from a generic IBI pool
+ * @pool: the pool to query an IBI slot on
+ *
+ * Search for a free slot in a generic IBI pool.
+ * The slot should be returned to the pool using i3c_generic_ibi_recycle_slot()
+ * when it's no longer needed.
+ *
+ * Return: a pointer to a free slot, or NULL if there's no free slot available.
+ */
+struct i3c_ibi_slot *
+i3c_generic_ibi_get_free_slot(struct i3c_generic_ibi_pool *pool)
+{
+	struct i3c_generic_ibi_slot *slot;
+	unsigned long flags;
+
+	spin_lock_irqsave(&pool->lock, flags);
+	slot = list_first_entry_or_null(&pool->free_slots,
+					struct i3c_generic_ibi_slot, node);
+	if (slot)
+		list_del(&slot->node);
+	spin_unlock_irqrestore(&pool->lock, flags);
+
+	return slot ? &slot->base : NULL;
+}
+EXPORT_SYMBOL_GPL(i3c_generic_ibi_get_free_slot);
+
+/**
+ * i3c_generic_ibi_recycle_slot() - Return a slot to a generic IBI pool
+ * @pool: the pool to return the IBI slot to
+ *
+ * Add an IBI slot back to its generic IBI pool. Should be called from the
+ * master driver struct_master_controller_ops->recycle_ibi() method.
+ */
+void i3c_generic_ibi_recycle_slot(struct i3c_generic_ibi_pool *pool,
+				  struct i3c_ibi_slot *s)
+{
+	struct i3c_generic_ibi_slot *slot;
+	unsigned long flags;
+
+	if (!s)
+		return;
+
+	slot = container_of(s, struct i3c_generic_ibi_slot, base);
+	spin_lock_irqsave(&pool->lock, flags);
+	list_add_tail(&slot->node, &pool->free_slots);
+	spin_unlock_irqrestore(&pool->lock, flags);
+}
+EXPORT_SYMBOL_GPL(i3c_generic_ibi_recycle_slot);
+
+/**
+ * i3c_master_register_new_i3c_devs() - register I3C devs that have been
+ *					plugged after the bus initialization
+ * @master: the master device these I3C devs have been attached to
+ *
+ * This is meant to be used when devices are discovered after the bus
+ * initialization, either because they sent a Hot-Join request which has
+ * been accepted by the master, or because the master has been asked to
+ * do a new DAA.
+ */
+void i3c_master_register_new_i3c_devs(struct i3c_master_controller *master)
+{
+	struct i3c_device *i3cdev;
+	int ret;
+
+	i3c_bus_for_each_i3cdev(master->bus, i3cdev) {
+		if (!i3cdev->new)
+			continue;
+
+		ret = device_add(&i3cdev->dev);
+		if (ret)
+			dev_err(master->parent,
+				"Failed to add I3C device (err = %d)\n", ret);
+
+		i3cdev->new = false;
+	}
+}
+EXPORT_SYMBOL_GPL(i3c_master_register_new_i3c_devs);
+
+static int i3c_master_init_bus(struct i3c_master_controller *master)
+{
+	int ret;
+
+	if (!master->ops->bus_init)
+		return 0;
+
+	/*
+	 * Take an exclusive lock on the bus before calling ->bus_init(), so
+	 * that all _locked() helpers can safely be called within this hook.
+	 */
+	i3c_bus_maintenance_lock(master->bus);
+	ret = master->ops->bus_init(master);
+	i3c_bus_maintenance_unlock(master->bus);
+
+	return ret;
+}
+
+static void i3c_master_cleanup_bus(struct i3c_master_controller *master)
+{
+	if (master->ops->bus_cleanup) {
+		/*
+		 * Take an exclusive lock on the bus before calling
+		 * ->bus_cleanup(), so that all _locked() helpers can safely be
+		 * called within this hook.
+		 */
+		i3c_bus_maintenance_lock(master->bus);
+		master->ops->bus_cleanup(master);
+		i3c_bus_maintenance_unlock(master->bus);
+	}
+}
+
+static void i3c_master_destroy_bus(struct i3c_master_controller *master)
+{
+	i3c_bus_unregister(master->bus);
+}
+
+static int i3c_master_create_bus(struct i3c_master_controller *master)
+{
+	struct i3c_bus *i3cbus;
+	int ret;
+
+	i3cbus = i3c_bus_create(master->parent);
+	if (IS_ERR(i3cbus))
+		return PTR_ERR(i3cbus);
+
+	master->bus = i3cbus;
+
+	if (i3cbus->dev.of_node) {
+		ret = of_populate_i3c_bus(master);
+		if (ret)
+			goto err_destroy_bus;
+	}
+
+	ret = i3c_bus_register(i3cbus);
+	if (ret)
+		goto err_destroy_bus;
+
+	return 0;
+
+err_destroy_bus:
+	i3c_bus_unref(i3cbus);
+
+	return ret;
+}
+
+/**
+ * i3c_master_register() - register an I3C master
+ * @master: master used to send frames on the bus
+ * @parent: the parent device (the one that provides this I3C master
+ *	    controller)
+ * @ops: the master controller operations
+ * @secondary: true if you are registering a secondary master. Will return
+ *	       -ENOTSUPP if set to true since secondary masters are not yet
+ *	       supported
+ *
+ * This function takes care of everything for you:
+ *
+ * - creates and initializes the I3C bus
+ * - populates the bus with static I2C devs if @parent->of_node is not
+ *   NULL
+ * - registers all I3C devices added by the controller during bus
+ *   initialization
+ * - registers the I2C adapter and all I2C devices
+ *
+ * Return: 0 in case of success, a negative error code otherwise.
+ */
+int i3c_master_register(struct i3c_master_controller *master,
+			struct device *parent,
+			const struct i3c_master_controller_ops *ops,
+			bool secondary)
+{
+	int ret;
+
+	/* We do not support secondary masters yet. */
+	if (secondary)
+		return -ENOTSUPP;
+
+	master->parent = parent;
+	master->ops = ops;
+	master->secondary = secondary;
+
+	ret = i3c_master_create_bus(master);
+	if (ret)
+		return ret;
+
+	/*
+	 * Before doing any operation on the bus, we need to initialize it.
+	 * This operation is highly controller dependent, but it is expected
+	 * to do the following operations:
+	 * 1/ reset all addresses of all devices on the bus (using RSTDAA CCC
+	 *    command)
+	 * 2/ start a DAA (Dynamic Address Assignment) procedure
+	 * 3/ populate the bus with all I3C devices discovered during DAA using
+	 *
+	 */
+	ret = i3c_master_init_bus(master);
+	if (ret)
+		goto err_destroy_bus;
+
+	master->wq = alloc_workqueue("%s", 0, 0, dev_name(parent));
+	if (!master->wq) {
+		ret = -ENOMEM;
+		goto err_cleanup_bus;
+	}
+
+	/* Register all I3C devs that have been added during DAA. */
+	i3c_master_register_new_i3c_devs(master);
+
+	/*
+	 * This is the last step: expose our i3c bus as an i2c adapter so that
+	 * i2c devices are exposed through the i2c subsystem.
+	 */
+	ret = i3c_master_i2c_adapter_init(master);
+	if (ret)
+		goto err_unreg_i3c_devs;
+
+	return 0;
+
+err_unreg_i3c_devs:
+	i3c_master_unregister_i3c_devs(master);
+	destroy_workqueue(master->wq);
+
+err_cleanup_bus:
+	i3c_master_cleanup_bus(master);
+
+err_destroy_bus:
+	i3c_master_destroy_bus(master);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(i3c_master_register);
+
+/**
+ * i3c_master_unregister() - unregister an I3C master
+ * @master: master used to send frames on the bus
+ *
+ * Basically undo everything done in i3c_master_register().
+ *
+ * Return: 0 in case of success, a negative error code otherwise.
+ */
+int i3c_master_unregister(struct i3c_master_controller *master)
+{
+	i3c_master_i2c_adapter_cleanup(master);
+
+	i3c_master_unregister_i3c_devs(master);
+
+	destroy_workqueue(master->wq);
+
+	i3c_master_cleanup_bus(master);
+
+	i3c_master_destroy_bus(master);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(i3c_master_unregister);
diff --git a/drivers/i3c/master/Kconfig b/drivers/i3c/master/Kconfig
new file mode 100644
index 000000000000..e69de29bb2d1
diff --git a/drivers/i3c/master/Makefile b/drivers/i3c/master/Makefile
new file mode 100644
index 000000000000..e69de29bb2d1
diff --git a/include/linux/i3c/ccc.h b/include/linux/i3c/ccc.h
new file mode 100644
index 000000000000..ff3e1a3e2c4c
--- /dev/null
+++ b/include/linux/i3c/ccc.h
@@ -0,0 +1,380 @@ 
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2017 Cadence Design Systems Inc.
+ *
+ * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
+ */
+
+#ifndef I3C_CCC_H
+#define I3C_CCC_H
+
+/* I3C CCC (Common Command Codes) related definitions */
+#define I3C_CCC_DIRECT			BIT(7)
+
+#define I3C_CCC_ID(id, broadcast)	\
+	((id) | ((broadcast) ? 0 : I3C_CCC_DIRECT))
+
+/* Commands valid in both broadcast and unicast modes */
+#define I3C_CCC_ENEC(broadcast)		I3C_CCC_ID(0x0, broadcast)
+#define I3C_CCC_DISEC(broadcast)	I3C_CCC_ID(0x1, broadcast)
+#define I3C_CCC_ENTAS(as, broadcast)	I3C_CCC_ID(0x2 + (as), broadcast)
+#define I3C_CCC_RSTDAA(broadcast)	I3C_CCC_ID(0x6, broadcast)
+#define I3C_CCC_SETMWL(broadcast)	I3C_CCC_ID(0x9, broadcast)
+#define I3C_CCC_SETMRL(broadcast)	I3C_CCC_ID(0xa, broadcast)
+#define I3C_CCC_SETXTIME(broadcast)	((broadcast) ? 0x28 : 0x98)
+#define I3C_CCC_VENDOR(id, broadcast)	((id) + ((broadcast) ? 0x61 : 0xe0))
+
+/* Broadcast-only commands */
+#define I3C_CCC_ENTDAA			I3C_CCC_ID(0x7, true)
+#define I3C_CCC_DEFSLVS			I3C_CCC_ID(0x8, true)
+#define I3C_CCC_ENTTM			I3C_CCC_ID(0xb, true)
+#define I3C_CCC_ENTHDR(x)		I3C_CCC_ID(0x20 + (x), true)
+
+/* Unicast-only commands */
+#define I3C_CCC_SETDASA			I3C_CCC_ID(0x7, false)
+#define I3C_CCC_SETNEWDA		I3C_CCC_ID(0x8, false)
+#define I3C_CCC_GETMWL			I3C_CCC_ID(0xb, false)
+#define I3C_CCC_GETMRL			I3C_CCC_ID(0xc, false)
+#define I3C_CCC_GETPID			I3C_CCC_ID(0xd, false)
+#define I3C_CCC_GETBCR			I3C_CCC_ID(0xe, false)
+#define I3C_CCC_GETDCR			I3C_CCC_ID(0xf, false)
+#define I3C_CCC_GETSTATUS		I3C_CCC_ID(0x10, false)
+#define I3C_CCC_GETACCMST		I3C_CCC_ID(0x11, false)
+#define I3C_CCC_SETBRGTGT		I3C_CCC_ID(0x13, false)
+#define I3C_CCC_GETMXDS			I3C_CCC_ID(0x14, false)
+#define I3C_CCC_GETHDRCAP		I3C_CCC_ID(0x15, false)
+#define I3C_CCC_GETXTIME		I3C_CCC_ID(0x19, false)
+
+#define I3C_CCC_EVENT_SIR		BIT(0)
+#define I3C_CCC_EVENT_MR		BIT(1)
+#define I3C_CCC_EVENT_HJ		BIT(3)
+
+/**
+ * struct i3c_ccc_events - payload passed to ENEC/DISEC CCC
+ *
+ * @events: bitmask of I3C_CCC_EVENT_xxx events.
+ *
+ * Depending on the CCC command, the specific events coming from all devices
+ * (broadcast version) or a specific device (unicast version) will be
+ * enabled (ENEC) or disabled (DISEC).
+ */
+struct i3c_ccc_events {
+	u8 events;
+} __packed;
+
+/**
+ * struct i3c_ccc_mwl - payload passed to SETMWL/GETMWL CCC
+ *
+ * @len: maximum write length in bytes
+ *
+ * The maximum write length is only applicable to SDR private messages or
+ * extended Write CCCs (like SETXTIME).
+ */
+struct i3c_ccc_mwl {
+	__be16 len;
+} __packed;
+
+/**
+ * struct i3c_ccc_mrl - payload passed to SETMRL/GETMRL CCC
+ *
+ * @len: maximum read length in bytes
+ * @ibi_len: maximum IBI payload length
+ *
+ * The maximum read length is only applicable to SDR private messages or
+ * extended Read CCCs (like GETXTIME).
+ * The IBI length is only valid if the I3C slave is IBI capable
+ * (%I3C_BCR_IBI_REQ_CAP is set).
+ */
+struct i3c_ccc_mrl {
+	__be16 read_len;
+	u8 ibi_len;
+} __packed;
+
+/**
+ * struct i3c_ccc_dev_desc - I3C/I3C device descriptor used for DEFSLVS
+ *
+ * @dyn_addr: dynamic address assigned to the I3C slave or 0 if the entry is
+ *	      describing an I2C slave.
+ * @dcr: DCR value (not applicable to entries describing I2C devices)
+ * @lvr: LVR value (not applicable to entries describing I3C devices)
+ * @bcr: BCR value or 0 if this entry is describing an I2C slave
+ * @static_addr: static address or 0 if the device does not have a static
+ *		 address
+ *
+ * The DEFSLVS command should be passed an array of i3c_ccc_dev_desc
+ * descriptors (one entry per I3C/I2C dev controlled by the master).
+ */
+struct i3c_ccc_dev_desc {
+	u8 dyn_addr;
+	union {
+		u8 dcr;
+		u8 lvr;
+	};
+	u8 bcr;
+	u8 static_addr;
+} __packed;
+
+/**
+ * struct i3c_ccc_defslvs - payload passed to DEFSLVS CCC
+ *
+ * @count: number of dev descriptors
+ * @master: descriptor describing the current master
+ * @slaves: array of descriptors describing slaves controlled by the
+ *	    current master
+ *
+ * Information passed to the broadcast DEFSLVS to propagate device
+ * information to all masters currently acting as slaves on the bus.
+ * This is only meaningful if you have more than one master.
+ */
+struct i3c_ccc_defslvs {
+	u8 count;
+	struct i3c_ccc_dev_desc master;
+	struct i3c_ccc_dev_desc slaves[0];
+} __packed;
+
+/**
+ * enum i3c_ccc_test_mode - enum listing all available test modes
+ *
+ * @I3C_CCC_EXIT_TEST_MODE: exit test mode
+ * @I3C_CCC_VENDOR_TEST_MODE: enter vendor test mode
+ */
+enum i3c_ccc_test_mode {
+	I3C_CCC_EXIT_TEST_MODE,
+	I3C_CCC_VENDOR_TEST_MODE,
+};
+
+/**
+ * struct i3c_ccc_enttm - payload passed to ENTTM CCC
+ *
+ * @mode: one of the &enum i3c_ccc_test_mode modes
+ *
+ * Information passed to the ENTTM CCC to instruct an I3C device to enter a
+ * specific test mode.
+ */
+struct i3c_ccc_enttm {
+	u8 mode;
+} __packed;
+
+/**
+ * struct i3c_ccc_setda - payload passed to ENTTM CCC
+ *
+ * @mode: one of the &enum i3c_ccc_test_mode modes
+ *
+ * Information passed to the ENTTM CCC to instruct an I3C device to enter a
+ * specific test mode.
+ */
+struct i3c_ccc_setda {
+	u8 addr;
+} __packed;
+
+/**
+ * struct i3c_ccc_getpid - payload passed to GETPID CCC
+ *
+ * @pid: 48 bits PID in big endian
+ */
+struct i3c_ccc_getpid {
+	u8 pid[6];
+} __packed;
+
+/**
+ * struct i3c_ccc_getbcr - payload passed to GETBCR CCC
+ *
+ * @bcr: BCR (Bus Characteristic Register) value
+ */
+struct i3c_ccc_getbcr {
+	u8 bcr;
+} __packed;
+
+/**
+ * struct i3c_ccc_getdcr - payload passed to GETDCR CCC
+ *
+ * @dcr: DCR (Device Characteristic Register) value
+ */
+struct i3c_ccc_getdcr {
+	u8 dcr;
+} __packed;
+
+#define I3C_CCC_STATUS_PENDING_INT(status)	((status) & GENMASK(3, 0))
+#define I3C_CCC_STATUS_PROTOCOL_ERROR		BIT(5)
+#define I3C_CCC_STATUS_ACTIVITY_MODE(status)	\
+	(((status) & GENMASK(7, 6)) >> 6)
+
+/**
+ * struct i3c_ccc_getstatus - payload passed to GETSTATUS CCC
+ *
+ * @status: status of the I3C slave (see I3C_CCC_STATUS_xxx macros for more
+ *	    information).
+ */
+struct i3c_ccc_getstatus {
+	__be16 status;
+} __packed;
+
+/**
+ * struct i3c_ccc_getaccmst - payload passed to GETACCMST CCC
+ *
+ * @newmaster: address of the master taking bus ownership
+ */
+struct i3c_ccc_getaccmst {
+	u8 newmaster;
+} __packed;
+
+/**
+ * struct i3c_ccc_bridged_slave_desc - bridged slave descriptor
+ *
+ * @addr: dynamic address of the bridged device
+ * @id: ID of the slave device behind the bridge
+ */
+struct i3c_ccc_bridged_slave_desc {
+	u8 addr;
+	__be16 id;
+} __packed;
+
+/**
+ * struct i3c_ccc_setbrgtgt - payload passed to SETBRGTGT CCC
+ *
+ * @count: number of bridged slaves
+ * @bslaves: bridged slave descriptors
+ */
+struct i3c_ccc_setbrgtgt {
+	u8 count;
+	struct i3c_ccc_bridged_slave_desc bslaves[0];
+} __packed;
+
+/**
+ * enum i3c_sdr_max_data_rate - max data rate values for private SDR transfers
+ */
+enum i3c_sdr_max_data_rate {
+	I3C_SDR_DR_FSCL_MAX,
+	I3C_SDR_DR_FSCL_8MHZ,
+	I3C_SDR_DR_FSCL_6MHZ,
+	I3C_SDR_DR_FSCL_4MHZ,
+	I3C_SDR_DR_FSCL_2MHZ,
+};
+
+/**
+ * enum i3c_tsco - clock to data turn-around
+ */
+enum i3c_tsco {
+	I3C_TSCO_LT_8NS,
+	I3C_TSCO_LT_9NS,
+	I3C_TSCO_LT_10NS,
+	I3C_TSCO_LT_11NS,
+	I3C_TSCO_LT_12NS,
+};
+
+#define I3C_CCC_MAX_SDR_FSCL_MASK	GENMASK(2, 0)
+#define I3C_CCC_MAX_SDR_FSCL(x)		((x) & I3C_CCC_MAX_SDR_FSCL_MASK)
+
+/**
+ * struct i3c_ccc_getmxds - payload passed to GETMXDS CCC
+ *
+ * @maxwr: write limitations
+ * @maxrd: read limitations
+ * @maxrdturn: maximum read turn-around expressed micro-seconds and
+ *	       little-endian formatted
+ */
+struct i3c_ccc_getmxds {
+	u8 maxwr;
+	u8 maxrd;
+	u8 maxrdturn[3];
+} __packed;
+
+#define I3C_CCC_HDR_MODE(mode)		BIT(mode)
+
+/**
+ * struct i3c_ccc_gethdrcap - payload passed to GETHDRCAP CCC
+ *
+ * @modes: bitmap of supported HDR modes
+ */
+struct i3c_ccc_gethdrcap {
+	u8 modes;
+} __packed;
+
+/**
+ * enum i3c_ccc_setxtime_subcmd - SETXTIME sub-commands
+ */
+enum i3c_ccc_setxtime_subcmd {
+	I3C_CCC_SETXTIME_ST = 0x7f,
+	I3C_CCC_SETXTIME_DT = 0xbf,
+	I3C_CCC_SETXTIME_ENTER_ASYNC_MODE0 = 0xdf,
+	I3C_CCC_SETXTIME_ENTER_ASYNC_MODE1 = 0xef,
+	I3C_CCC_SETXTIME_ENTER_ASYNC_MODE2 = 0xf7,
+	I3C_CCC_SETXTIME_ENTER_ASYNC_MODE3 = 0xfb,
+	I3C_CCC_SETXTIME_ASYNC_TRIGGER = 0xfd,
+	I3C_CCC_SETXTIME_TPH = 0x3f,
+	I3C_CCC_SETXTIME_TU = 0x9f,
+	I3C_CCC_SETXTIME_ODR = 0x8f,
+};
+
+/**
+ * struct i3c_ccc_setxtime - payload passed to SETXTIME CCC
+ *
+ * @subcmd: one of the sub-commands ddefined in &enum i3c_ccc_setxtime_subcmd
+ * @data: sub-command payload. Amount of data is determined by
+ *	  &i3c_ccc_setxtime->subcmd
+ */
+struct i3c_ccc_setxtime {
+	u8 subcmd;
+	u8 data[0];
+} __packed;
+
+#define I3C_CCC_GETXTIME_SYNC_MODE	BIT(0)
+#define I3C_CCC_GETXTIME_ASYNC_MODE(x)	BIT((x) + 1)
+#define I3C_CCC_GETXTIME_OVERFLOW	BIT(7)
+
+/**
+ * struct i3c_ccc_getxtime - payload retrieved from GETXTIME CCC
+ *
+ * @supported_modes: bitmap describing supported XTIME modes
+ * @state: current status (enabled mode and overflow status)
+ * @frequency: slave's internal oscillator frequency in 500KHz steps
+ * @inaccuracy: slave's internal oscillator inaccuracy in 0.1% steps
+ */
+struct i3c_ccc_getxtime {
+	u8 supported_modes;
+	u8 state;
+	u8 frequency;
+	u8 inaccuracy;
+} __packed;
+
+/**
+ * struct i3c_ccc_cmd_payload - CCC payload
+ *
+ * @len: payload length
+ * @data: payload data
+ */
+struct i3c_ccc_cmd_payload {
+	u16 len;
+	void *data;
+};
+
+/**
+ * struct i3c_ccc_cmd_dest - CCC command destination
+ *
+ * @addr: can be an I3C device address or the broadcast address if this is a
+ *	  broadcast CCC
+ * @payload: payload to be sent to this device or broadcasted
+ */
+struct i3c_ccc_cmd_dest {
+	u8 addr;
+	struct i3c_ccc_cmd_payload payload;
+};
+
+/**
+ * struct i3c_ccc_cmd - CCC command
+ *
+ * @rnw: true if the CCC should retrieve data from the device. Only valid for
+ *	 unicast commands
+ * @id: CCC command id
+ * @dests: array of destinations and associated payload for this CCC. Most of
+ *	   the time, only one destination is provided
+ * @ndests: number of destinations. Should always be one for broadcast commands
+ */
+struct i3c_ccc_cmd {
+	bool rnw;
+	u8 id;
+	struct i3c_ccc_cmd_dest *dests;
+	int ndests;
+};
+
+#endif /* I3C_CCC_H */
diff --git a/include/linux/i3c/device.h b/include/linux/i3c/device.h
new file mode 100644
index 000000000000..83958d3a02e2
--- /dev/null
+++ b/include/linux/i3c/device.h
@@ -0,0 +1,321 @@ 
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2017 Cadence Design Systems Inc.
+ *
+ * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
+ */
+
+#ifndef I3C_DEV_H
+#define I3C_DEV_H
+
+#include <linux/device.h>
+#include <linux/i2c.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+
+/**
+ * enum i3c_hdr_mode - HDR mode ids
+ * @I3C_HDR_DDR: DDR mode
+ * @I3C_HDR_TSP: TSP mode
+ * @I3C_HDR_TSL: TSL mode
+ */
+enum i3c_hdr_mode {
+	I3C_HDR_DDR,
+	I3C_HDR_TSP,
+	I3C_HDR_TSL,
+};
+
+/**
+ * struct i3c_hdr_cmd - I3C HDR command
+ * @mode: HDR mode selected for this command
+ * @code: command opcode
+ * @addr: I3C dynamic address
+ * @ndatawords: number of data words (a word is 16bits wide)
+ * @data: input/output buffer
+ */
+struct i3c_hdr_cmd {
+	enum i3c_hdr_mode mode;
+	u8 code;
+	u8 addr;
+	int ndatawords;
+	union {
+		u16 *in;
+		const u16 *out;
+	} data;
+};
+
+/* Private SDR read transfer */
+#define I3C_PRIV_XFER_READ		BIT(0)
+/*
+ * Instruct the controller to issue a STOP after a specific transfer instead
+ * of a REPEATED START.
+ */
+#define I3C_PRIV_XFER_STOP		BIT(1)
+
+/**
+ * struct i3c_priv_xfer - I3C SDR private transfer
+ * @addr: I3C dynamic address
+ * @len: transfer length in bytes of the transfer
+ * @flags: combination of I3C_PRIV_XFER_xxx flags
+ * @data: input/output buffer
+ */
+struct i3c_priv_xfer {
+	u8 addr;
+	u16 len;
+	u32 flags;
+	struct {
+		void *in;
+		const void *out;
+	} data;
+};
+
+/**
+ * enum i3c_dcr - I3C DCR values
+ * @I3C_DCR_GENERIC_DEVICE: generic I3C device
+ */
+enum i3c_dcr {
+	I3C_DCR_GENERIC_DEVICE = 0,
+};
+
+#define I3C_PID_MANUF_ID(pid)		(((pid) & GENMASK_ULL(47, 33)) >> 33)
+#define I3C_PID_RND_LOWER_32BITS(pid)	(!!((pid) & BIT_ULL(32)))
+#define I3C_PID_RND_VAL(pid)		((pid) & GENMASK_ULL(31, 0))
+#define I3C_PID_PART_ID(pid)		(((pid) & GENMASK_ULL(31, 16)) >> 16)
+#define I3C_PID_INSTANCE_ID(pid)	(((pid) & GENMASK_ULL(15, 12)) >> 12)
+#define I3C_PID_EXTRA_INFO(pid)		((pid) & GENMASK_ULL(11, 0))
+
+#define I3C_BCR_DEVICE_ROLE(bcr)	((bcr) & GENMASK(7, 6))
+#define I3C_BCR_I3C_SLAVE		(0 << 6)
+#define I3C_BCR_I3C_MASTER		(1 << 6)
+#define I3C_BCR_HDR_CAP			BIT(5)
+#define I3C_BCR_BRIDGE			BIT(4)
+#define I3C_BCR_OFFLINE_CAP		BIT(3)
+#define I3C_BCR_IBI_PAYLOAD		BIT(2)
+#define I3C_BCR_IBI_REQ_CAP		BIT(1)
+#define I3C_BCR_MAX_DATA_SPEED_LIM	BIT(0)
+
+/**
+ * struct i3c_device_info - I3C device information
+ * @pid: Provisional ID
+ * @bcr: Bus Characteristic Register
+ * @dcr: Device Characteristic Register
+ * @static_addr: static/I2C address
+ * @dyn_addr: dynamic address
+ * @hdr_cap: supported HDR modes
+ * @max_read_ds: max read speed information
+ * @max_write_ds: max write speed information
+ * @max_ibi_len: max IBI payload length
+ * @max_read_turnaround: max read turn-around time in micro-seconds
+ * @max_read_len: max private SDR read length in bytes
+ * @max_write_len: max private SDR write length in bytes
+ *
+ * These are all basic information that should be advertised by an I3C device.
+ * Some of them are optional depending on the device type and device
+ * capabilities.
+ * For each I3C slave attached to a master with
+ * i3c_master_add_i3c_dev_locked(), the core will send the relevant CCC command
+ * to retrieve these data.
+ */
+struct i3c_device_info {
+	u64 pid;
+	u8 bcr;
+	u8 dcr;
+	u8 static_addr;
+	u8 dyn_addr;
+	u8 hdr_cap;
+	u8 max_read_ds;
+	u8 max_write_ds;
+	u8 max_ibi_len;
+	u32 max_read_turnaround;
+	u16 max_read_len;
+	u16 max_write_len;
+};
+
+/*
+ * I3C device internals are kept hidden from I3C device users. It's just
+ * simpler to refactor things when everything goes through getter/setters, and
+ * I3C device drivers should not have to worry about internal representation
+ * anyway.
+ */
+struct i3c_device;
+
+/* These macros should be used to i3c_device_id entries. */
+#define I3C_MATCH_MANUF_AND_PART (I3C_MATCH_MANUF | I3C_MATCH_PART)
+
+#define I3C_DEVICE(_manufid, _partid, _drvdata)				\
+	{								\
+		.match_flags = I3C_MATCH_MANUF_AND_PART,		\
+		.manuf_id = _manufid,					\
+		.part_id = _partid,					\
+		.data = _drvdata,					\
+	}
+
+#define I3C_DEVICE_EXTRA_INFO(_manufid, _partid, _info, _drvdata)	\
+	{								\
+		.match_flags = I3C_MATCH_MANUF_AND_PART |		\
+			       I3C_MATCH_EXTRA_INFO,			\
+		.manuf_id = _manufid,					\
+		.part_id = _partid,					\
+		.extra_info = _info,					\
+		.data = _drvdata,					\
+	}
+
+#define I3C_CLASS(_dcr, _drvdata)					\
+	{								\
+		.match_flags = I3C_MATCH_DCR,				\
+		.dcr = _dcr,						\
+	}
+
+/**
+ * struct i3c_driver - I3C device driver
+ * @driver: inherit from device_driver
+ * @probe: I3C device probe method
+ * @remove: I3C device remove method
+ * @id_table: I3C device match table. Will be used by the framework to decide
+ *	      which device to bind to this driver
+ */
+struct i3c_driver {
+	struct device_driver driver;
+	int (*probe)(struct i3c_device *dev);
+	int (*remove)(struct i3c_device *dev);
+	const struct i3c_device_id *id_table;
+};
+
+static inline struct i3c_driver *drv_to_i3cdrv(struct device_driver *drv)
+{
+	return container_of(drv, struct i3c_driver, driver);
+}
+
+const struct i3c_device_id *
+i3c_device_match_id(struct i3c_device *i3cdev,
+		    const struct i3c_device_id *id_table);
+
+int i3c_driver_register_with_owner(struct i3c_driver *drv,
+				   struct module *owner);
+void i3c_driver_unregister(struct i3c_driver *drv);
+
+#define i3c_driver_register(__drv)		\
+	i3c_driver_register_with_owner(__drv, THIS_MODULE)
+
+/**
+ * module_i3c_driver() - Register a module providing an I3C driver
+ * @__drv: the I3C driver to register
+ *
+ * Provide generic init/exit functions that simply register/unregister an I3C
+ * driver.
+ * Should be used by any driver that does not require extra init/cleanup steps.
+ */
+#define module_i3c_driver(__drv)		\
+	module_driver(__drv, i3c_driver_register, i3c_driver_unregister)
+
+/**
+ * i3c_i2c_driver_register() - Register an i2c and an i3c driver
+ * @i3cdrv: the I3C driver to register
+ * @i2cdrv: the I2C driver to register
+ *
+ * This function registers both @i2cdev and @i3cdev, and fails if one of these
+ * registrations fails. This is mainly useful for devices that support both I2C
+ * and I3C modes.
+ * Note that when CONFIG_I3C is not enabled, this function only registers the
+ * I2C driver.
+ *
+ * Return: 0 if both registrations succeeds, a negative error code otherwise.
+ */
+static inline int i3c_i2c_driver_register(struct i3c_driver *i3cdrv,
+					  struct i2c_driver *i2cdrv)
+{
+	int ret;
+
+	ret = i2c_add_driver(i2cdrv);
+	if (ret || !IS_ENABLED(CONFIG_I3C))
+		return ret;
+
+	ret = i3c_driver_register(i3cdrv);
+	if (ret)
+		i2c_del_driver(i2cdrv);
+
+	return ret;
+}
+
+/**
+ * i3c_i2c_driver_unregister() - Unregister an i2c and an i3c driver
+ * @i3cdrv: the I3C driver to register
+ * @i2cdrv: the I2C driver to register
+ *
+ * This function unregisters both @i3cdrv and @i2cdrv.
+ * Note that when CONFIG_I3C is not enabled, this function only unregisters the
+ * @i2cdrv.
+ */
+static inline void i3c_i2c_driver_unregister(struct i3c_driver *i3cdrv,
+					     struct i2c_driver *i2cdrv)
+{
+	if (IS_ENABLED(CONFIG_I3C))
+		i3c_driver_unregister(i3cdrv);
+
+	i2c_del_driver(i2cdrv);
+}
+
+/**
+ * module_i3c_i2c_driver() - Register a module providing an I3C and an I2C
+ *			     driver
+ * @__i3cdrv: the I3C driver to register
+ * @__i2cdrv: the I3C driver to register
+ *
+ * Provide generic init/exit functions that simply register/unregister an I3C
+ * and an I2C driver.
+ * This macro can be used even if CONFIG_I3C is disabled, in this case, only
+ * the I2C driver will be registered.
+ * Should be used by any driver that does not require extra init/cleanup steps.
+ */
+#define module_i3c_i2c_driver(__i3cdrv, __i2cdrv)	\
+	module_driver(__i3cdrv,				\
+		      i3c_i2c_driver_register,		\
+		      i3c_i2c_driver_unregister)
+
+int i3c_device_do_priv_xfers(struct i3c_device *dev,
+			     struct i3c_priv_xfer *xfers,
+			     int nxfers);
+int i3c_device_send_hdr_cmds(struct i3c_device *dev,
+			     struct i3c_hdr_cmd *cmds,
+			     int ncmds);
+
+void i3c_device_get_info(struct i3c_device *dev, struct i3c_device_info *info);
+
+struct i3c_ibi_payload {
+	unsigned int len;
+	const void *data;
+};
+
+/**
+ * struct i3c_ibi_setup - IBI setup object
+ * @max_payload_len: maximum length of the payload associated to an IBI. If one
+ *		     IBI appears to have a payload that is bigger than this
+ *		     number, the IBI will be rejected.
+ * @num_slots: number of pre-allocated IBI slots. This should be chosen so that
+ *	       the system never runs out of IBI slots, otherwise you'll lose
+ *	       IBIs.
+ * @handler: IBI handler, every time an IBI is received. This handler is called
+ *	     in a workqueue context. It is allowed to sleep and send new
+ *	     messages on the bus, though it's recommended to keep the
+ *	     processing done there as fast as possible to avoid delaying
+ *	     processing of other queued on the same workqueue.
+ *
+ * Temporary structure used to pass information to i3c_device_request_ibi().
+ * This object can be allocated on the stack since i3c_device_request_ibi()
+ * copies every bit of information and do not use it after
+ * i3c_device_request_ibi() has returned.
+ */
+struct i3c_ibi_setup {
+	unsigned int max_payload_len;
+	unsigned int num_slots;
+	void (*handler)(struct i3c_device *dev,
+			const struct i3c_ibi_payload *payload);
+};
+
+int i3c_device_request_ibi(struct i3c_device *dev,
+			   const struct i3c_ibi_setup *setup);
+void i3c_device_free_ibi(struct i3c_device *dev);
+int i3c_device_enable_ibi(struct i3c_device *dev);
+int i3c_device_disable_ibi(struct i3c_device *dev);
+
+#endif /* I3C_DEV_H */
diff --git a/include/linux/i3c/master.h b/include/linux/i3c/master.h
new file mode 100644
index 000000000000..7ec9a4821bac
--- /dev/null
+++ b/include/linux/i3c/master.h
@@ -0,0 +1,564 @@ 
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2017 Cadence Design Systems Inc.
+ *
+ * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
+ */
+
+#ifndef I3C_MASTER_H
+#define I3C_MASTER_H
+
+#include <linux/i2c.h>
+#include <linux/i3c/ccc.h>
+#include <linux/i3c/device.h>
+#include <linux/spinlock.h>
+
+#define I3C_HOT_JOIN_ADDR		0x2
+#define I3C_BROADCAST_ADDR		0x7e
+#define I3C_MAX_ADDR			GENMASK(6, 0)
+
+struct i3c_master_controller;
+struct i3c_bus;
+
+/**
+ * struct i3c_i2c_dev - I3C/I2C common information
+ * @node: node element used to insert the device into the I2C or I3C device
+ *	  list
+ * @bus: I3C bus this device is connected to
+ * @master: I3C master that instantiated this device. Will be used to send
+ *	    I2C/I3C frames on the bus
+ * @master_priv: master private data assigned to the device. Can be used to
+ *		 add master specific information
+ *
+ * This structure is describing common I3C/I2C dev information.
+ */
+struct i3c_i2c_dev {
+	struct list_head node;
+	struct i3c_bus *bus;
+	struct i3c_master_controller *master;
+	void *master_priv;
+};
+
+#define I3C_LVR_I2C_INDEX_MASK		GENMASK(7, 5)
+#define I3C_LVR_I2C_INDEX(x)		((x) << 5)
+#define I3C_LVR_I2C_FM_MODE		BIT(4)
+
+#define I2C_MAX_ADDR			GENMASK(9, 0)
+
+/**
+ * struct i2c_device - I2C device object
+ * @common: inherit common I3C/I2C description
+ * @info: I2C board info used to instantiate the I2C device. If you are
+ *	  using DT to describe your hardware, this will be filled for you
+ * @client: I2C client object created by the I2C framework. This will only
+ *	    be valid after i3c_master_register() returns
+ * @lvr: Legacy Virtual Register value as described in the I3C specification
+ *
+ * I2C device object. Note that the real I2C device is represented by
+ * i2c_device->client, but we need extra information to handle the device when
+ * it's connected to an I3C bus, hence the &struct i2c_device wrapper.
+ *
+ * The I2C framework is not impacted by this new representation.
+ */
+struct i2c_device {
+	struct i3c_i2c_dev common;
+	struct i2c_board_info info;
+	struct i2c_client *client;
+	u8 lvr;
+};
+
+/**
+ * struct i3c_ibi_slot - I3C IBI (In-Band Interrupt) slot
+ * @work: work associated to this slot. The IBI handler will be called from
+ *	  there
+ * @dev: the I3C device that has generated this IBI
+ * @len: length of the payload associated to this IBI
+ * @data: payload buffer
+ *
+ * An IBI slot is an object pre-allocated by the controller and used when an
+ * IBI comes in.
+ * Every time an IBI comes in, the I3C master driver should find a free IBI
+ * slot in its IBI slot pool, retrieve the IBI payload and queue the IBI using
+ * i3c_device_queue_ibi().
+ *
+ * How IBI slots are allocated is left to the I3C master driver, though, for
+ * simple kmalloc-based allocation, the generic IBI slot pool can be used.
+ */
+struct i3c_ibi_slot {
+	struct work_struct work;
+	struct i3c_device *dev;
+	unsigned int len;
+	void *data;
+};
+
+/**
+ * struct i3c_device_ibi_info - IBI information attached to a specific device
+ * @all_ibis_handled: used to be informed when no more IBIs are waiting to be
+ *		      processed. Used by i3c_device_disable_ibi() to wait for
+ *		      all IBIs to be dequeued
+ * @pending_ibis: count the number of pending IBIs. Each pending IBI has its
+ *		  work element queued to the controller workqueue
+ * @max_payload_len: maximum payload length for an IBI coming from this device.
+ *		     this value is specified when calling
+ *		     i3c_device_request_ibi() and should not change at run
+ *		     time. All messages IBIs exceeding this limit should be
+ *		     rejected by the master
+ * @enabled: reflect the IBI status
+ * @handler: IBI handler specified at i3c_device_request_ibi() call time. This
+ *	     handler will be called from the controller workqueue, and as such
+ *	     is allowed to sleep (though it is recommended to process the IBI
+ *	     as fast as possible to not stall processing of other IBIs queued
+ *	     on the same workqueue).
+ *	     New I3C messages can be sent from the IBI handler
+ *
+ * The &struct_i3c_device_ibi_info object is allocated when
+ * i3c_device_request_ibi() is called and attached to a specific device. This
+ * object is here to manage IBIs coming from a specific I3C device.
+ *
+ * Note that this structure is the generic view of the IBI management
+ * infrastructure. I3C master drivers may have their own internal
+ * representation which they can associate to the device using
+ * controller-private data.
+ */
+struct i3c_device_ibi_info {
+	struct completion all_ibis_handled;
+	atomic_t pending_ibis;
+	unsigned int max_payload_len;
+	bool enabled;
+	void (*handler)(struct i3c_device *dev,
+			const struct i3c_ibi_payload *payload);
+};
+
+/**
+ * struct i3c_device - I3C device object
+ * @common: inherit common I3C/I2C description
+ * @dev: device object to register the I3C dev to the device model
+ * @new: true if the device has not yet been registered to the device model.
+ *	 Will be set to false after device_add() is called on this device
+ *	 even if device_add() fails
+ * @info: I3C device information. Will be automatically filled when you create
+ *	  your device with i3c_master_add_i3c_dev_locked()
+ * @ibi_lock: lock used to protect the &struct_i3c_device->ibi
+ * @ibi: IBI info attached to a device. Should be NULL until
+ *	 i3c_device_request_ibi() is called
+ *
+ * I3C device object. Every I3C devs on the I3C bus are represented, including
+ * I3C masters. For each of them, we have an instance of &struct i3c_device.
+ */
+struct i3c_device {
+	struct i3c_i2c_dev common;
+	struct device dev;
+	bool new;
+	struct i3c_device_info info;
+	struct mutex ibi_lock;
+	struct i3c_device_ibi_info *ibi;
+};
+
+/*
+ * The I3C specification says the maximum number of devices connected on the
+ * bus is 11, but this number depends on external parameters like trace length,
+ * capacitive load per Device, and the types of Devices present on the Bus.
+ * I3C master can also have limitations, so this number is just here as a
+ * reference and should be adjusted on a per-controller/per-board basis.
+ */
+#define I3C_BUS_MAX_DEVS		11
+
+#define I3C_BUS_MAX_I3C_SCL_RATE	12900000
+#define I3C_BUS_TYP_I3C_SCL_RATE	12500000
+#define I3C_BUS_I2C_FM_PLUS_SCL_RATE	1000000
+#define I3C_BUS_I2C_FM_SCL_RATE		400000
+#define I3C_BUS_TLOW_OD_MIN_NS		200
+
+/**
+ * enum i3c_bus_mode - I3C bus mode
+ * @I3C_BUS_MODE_PURE: only I3C devices are connected to the bus. No limitation
+ *		       expected
+ * @I3C_BUS_MODE_MIXED_FAST: I2C devices with 50ns spike filter are present on
+ *			     the bus. The only impact in this mode is that the
+ *			     high SCL pulse has to stay below 50ns to trick I2C
+ *			     devices when transmitting I3C frames
+ * @I3C_BUS_MODE_MIXED_SLOW: I2C devices without 50ns spike filter are present
+ *			     on the bus
+ */
+enum i3c_bus_mode {
+	I3C_BUS_MODE_PURE,
+	I3C_BUS_MODE_MIXED_FAST,
+	I3C_BUS_MODE_MIXED_SLOW,
+};
+
+/**
+ * enum i3c_addr_slot_status - I3C address slot status
+ * @I3C_ADDR_SLOT_FREE: address is free
+ * @I3C_ADDR_SLOT_RSVD: address is reserved
+ * @I3C_ADDR_SLOT_I2C_DEV: address is assigned to an I2C device
+ * @I3C_ADDR_SLOT_I3C_DEV: address is assigned to an I3C device
+ * @I3C_ADDR_SLOT_STATUS_MASK: address slot mask
+ *
+ * On an I3C bus, addresses are assigned dynamically, and we need to know which
+ * addresses are free to use and which ones are already assigned.
+ *
+ * Addresses marked as reserved are those reserved by the I3C protocol
+ * (broadcast address, ...).
+ */
+enum i3c_addr_slot_status {
+	I3C_ADDR_SLOT_FREE,
+	I3C_ADDR_SLOT_RSVD,
+	I3C_ADDR_SLOT_I2C_DEV,
+	I3C_ADDR_SLOT_I3C_DEV,
+	I3C_ADDR_SLOT_STATUS_MASK = 3,
+};
+
+/**
+ * struct i3c_bus - I3C bus object
+ * @dev: device to be registered to the device-model
+ * @cur_master: I3C master currently driving the bus. Since I3C is multi-master
+ *		this can change over the time. Will be used to let a master
+ *		know whether it needs to request bus ownership before sending
+ *		a frame or not
+ * @id: bus ID. Assigned by the framework when register the bus
+ * @addrslots: a bitmap with 2-bits per-slot to encode the address status and
+ *	       ease the DAA (Dynamic Address Assignment) procedure (see
+ *	       &enum i3c_addr_slot_status)
+ * @mode: bus mode (see &enum i3c_bus_mode)
+ * @scl_rate: SCL signal rate for I3C and I2C mode
+ * @devs: 2 lists containing all I3C/I2C devices connected to the bus
+ * @lock: read/write lock on the bus. This is needed to protect against
+ *	  operations that have an impact on the whole bus and the devices
+ *	  connected to it. For example, when asking slaves to drop their
+ *	  dynamic address (RSTDAA CCC), we need to make sure no one is trying
+ *	  to send I3C frames to these devices.
+ *	  Note that this lock does not protect against concurrency between
+ *	  devices: several drivers can send different I3C/I2C frames through
+ *	  the same master in parallel. This is the responsibility of the
+ *	  master to guarantee that frames are actually sent sequentially and
+ *	  not interlaced
+ *
+ * The I3C bus is represented with its own object and not implicitly described
+ * by the I3C master to cope with the multi-master functionality, where one bus
+ * can be shared amongst several masters, each of them requesting bus ownership
+ * when they need to.
+ */
+struct i3c_bus {
+	struct device dev;
+	struct i3c_device *cur_master;
+	int id;
+	unsigned long addrslots[((I2C_MAX_ADDR + 1) * 2) / BITS_PER_LONG];
+	enum i3c_bus_mode mode;
+	struct {
+		unsigned long i3c;
+		unsigned long i2c;
+	} scl_rate;
+	struct {
+		struct list_head i3c;
+		struct list_head i2c;
+	} devs;
+	struct rw_semaphore lock;
+};
+
+static inline struct i3c_device *dev_to_i3cdev(struct device *dev)
+{
+	return container_of(dev, struct i3c_device, dev);
+}
+
+struct i3c_master_controller;
+
+/**
+ * struct i3c_master_controller_ops - I3C master methods
+ * @bus_init: hook responsible for the I3C bus initialization. This
+ *	      initialization should follow the steps described in the I3C
+ *	      specification. This hook is called with the bus lock held in
+ *	      write mode, which means all _locked() helpers can safely be
+ *	      called from there
+ * @bus_cleanup: cleanup everything done in
+ *		 &i3c_master_controller_ops->bus_init(). This function is
+ *		 optional and should only be implemented if
+ *		 &i3c_master_controller_ops->bus_init() attached private data
+ *		 to I3C/I2C devices. This hook is called with the bus lock
+ *		 held in write mode, which means all _locked() helpers can
+ *		 safely be called from there
+ * @supports_ccc_cmd: should return true if the CCC command is supported, false
+ *		      otherwise
+ * @send_ccc_cmd: send a CCC command
+ * @send_hdr_cmds: send one or several HDR commands. If there is more than one
+ *		   command, they should ideally be sent in the same HDR
+ *		   transaction
+ * @priv_xfers: do one or several private I3C SDR transfers
+ * @i2c_xfers: do one or several I2C transfers
+ * @request_ibi: attach an IBI handler to an I3C device. This implies defining
+ *		 an IBI handler and the constraints of the IBI (maximum payload
+ *		 length and number of pre-allocated slots).
+ *		 Some controllers support less IBI-capable devices than regular
+ *		 devices, so this method might return -%EBUSY if there's no
+ *		 more space for an extra IBI registration
+ * @free_ibi: free an IBI previously requested with ->request_ibi(). The IBI
+ *	      should have been disabled with ->disable_irq() prior to that
+ * @enable_ibi: enable the IBI. Only valid if ->request_ibi() has been called
+ *		prior to ->enable_ibi(). The controller should first enable
+ *		the IBI on the controller end (for example, unmask the hardware
+ *		IRQ) and then send the ENEC CCC command (with the IBI flag set)
+ *		to the I3C device
+ * @disable_ibi: disable an IBI. First send the DISEC CCC command with the IBI
+ *		 flag set and then deactivate the hardware IRQ on the
+ *		 controller end
+ * @recycle_ibi_slot: recycle an IBI slot. Called every time an IBI has been
+ *		      processed by its handler. The IBI slot should be put back
+ *		      in the IBI slot pool so that the controller can re-use it
+ *		      for a future IBI
+ *
+ * One of the most important hooks in these ops is
+ * &i3c_master_controller_ops->bus_init(). Here is a non-exhaustive list of
+ * things that should be done in &i3c_master_controller_ops->bus_init():
+ *
+ * 1) call i3c_master_set_info() with all information describing the master
+ * 2) ask all slaves to drop their dynamic address by sending the RSTDAA CCC
+ *    with i3c_master_rstdaa_locked()
+ * 3) ask all slaves to disable IBIs using i3c_master_disec_locked()
+ * 4) start a DDA procedure by sending the ENTDAA CCC with
+ *    i3c_master_entdaa_locked(), or using the internal DAA logic provided by
+ *    your controller
+ * 5) assign a dynamic address to each I3C device discovered during DAA and
+ *    for each of them, call i3c_master_add_i3c_dev_locked()
+ * 6) propagate device table to secondary masters by calling
+ *    i3c_master_defslvs_locked()
+ *
+ * Note that these steps do not include all controller specific initialization.
+ */
+struct i3c_master_controller_ops {
+	int (*bus_init)(struct i3c_master_controller *master);
+	void (*bus_cleanup)(struct i3c_master_controller *master);
+	bool (*supports_ccc_cmd)(struct i3c_master_controller *master,
+				 const struct i3c_ccc_cmd *cmd);
+	int (*send_ccc_cmd)(struct i3c_master_controller *master,
+			    struct i3c_ccc_cmd *cmd);
+	int (*send_hdr_cmds)(struct i3c_master_controller *master,
+			     const struct i3c_hdr_cmd *cmds,
+			     int ncmds);
+	int (*priv_xfers)(struct i3c_master_controller *master,
+			  const struct i3c_priv_xfer *xfers,
+			  int nxfers);
+	int (*i2c_xfers)(struct i3c_master_controller *master,
+			 const struct i2c_msg *xfers, int nxfers);
+	int (*request_ibi)(struct i3c_master_controller *master,
+			   struct i3c_device *dev,
+			   const struct i3c_ibi_setup *req);
+	void (*free_ibi)(struct i3c_master_controller *master,
+			 struct i3c_device *dev);
+	int (*enable_ibi)(struct i3c_master_controller *master,
+			  struct i3c_device *dev);
+	int (*disable_ibi)(struct i3c_master_controller *master,
+			   struct i3c_device *dev);
+	void (*recycle_ibi_slot)(struct i3c_master_controller *master,
+				 struct i3c_device *dev,
+				 struct i3c_ibi_slot *slot);
+};
+
+/**
+ * struct i3c_master_controller - I3C master controller object
+ * @parent: parent device that instantiated this master
+ * @this: an I3C device object representing this master. This device will be
+ *	  added to the list of I3C devs available on the bus
+ * @i2c: I2C adapter used for backward compatibility. This adapter is
+ *	 registered to the I2C subsystem to be as transparent as possible to
+ *	 existing I2C drivers
+ * @ops: master operations. See &struct i3c_master_controller_ops
+ * @secondary: true if the master is a secondary master
+ * @bus: I3C bus object created by this master
+ * @wq: workqueue used to execute IBI handlers. Can also be used by master
+ *	drivers if they need to postpone operations that need to take place
+ *	in a thread context. Typical examples are Hot Join processing which
+ *	requires taking the bus lock in maintenance, which in turn, can only
+ *	be done from a sleep-able context
+ *
+ * A &struct i3c_master_controller has to be registered to the I3C subsystem
+ * through i3c_master_register(). None of &struct i3c_master_controller fields
+ * should be set manually, just pass appropriate values to
+ * i3c_master_register().
+ */
+struct i3c_master_controller {
+	struct device *parent;
+	struct i3c_device *this;
+	struct i2c_adapter i2c;
+	const struct i3c_master_controller_ops *ops;
+	bool secondary;
+	struct i3c_bus *bus;
+	struct workqueue_struct *wq;
+};
+
+/**
+ * i3c_bus_for_each_i2cdev() - iterate over all I2C devices present on the bus
+ * @bus: the I3C bus
+ * @i2cdev: an I2C device updated to point to the current device at each loop
+ *	    iteration
+ *
+ * Iterate over all I2C devs present on the bus.
+ */
+#define i3c_bus_for_each_i2cdev(bus, i2cdev)				\
+	list_for_each_entry(i2cdev, &(bus)->devs.i2c, common.node)
+
+/**
+ * i3c_bus_for_each_i3cdev() - iterate over all I3C devices present on the bus
+ * @bus: the I3C bus
+ * @i3cdev: an I3C device updated to point to the current device at each loop
+ *	    iteration
+ *
+ * Iterate over all I3C devs present on the bus.
+ */
+#define i3c_bus_for_each_i3cdev(bus, i3cdev)				\
+	list_for_each_entry(i3cdev, &(bus)->devs.i3c, common.node)
+
+void i3c_bus_maintenance_lock(struct i3c_bus *bus);
+void i3c_bus_maintenance_unlock(struct i3c_bus *bus);
+void i3c_bus_normaluse_lock(struct i3c_bus *bus);
+void i3c_bus_normaluse_unlock(struct i3c_bus *bus);
+
+int i3c_master_send_hdr_cmds(struct i3c_master_controller *master,
+			     const struct i3c_hdr_cmd *cmds,
+			     int ncmds);
+int i3c_master_do_priv_xfers(struct i3c_master_controller *master,
+			     const struct i3c_priv_xfer *xfers,
+			     int nxfers);
+int i3c_master_do_i2c_xfers(struct i3c_master_controller *master,
+			    const struct i2c_msg *xfers,
+			    int nxfers);
+
+int i3c_master_disec_locked(struct i3c_master_controller *master, u8 addr,
+			    const struct i3c_ccc_events *evts);
+int i3c_master_enec_locked(struct i3c_master_controller *master, u8 addr,
+			   const struct i3c_ccc_events *evts);
+int i3c_master_rstdaa_locked(struct i3c_master_controller *master, u8 addr);
+int i3c_master_entdaa_locked(struct i3c_master_controller *master);
+int i3c_master_defslvs_locked(struct i3c_master_controller *master);
+
+int i3c_master_get_free_addr(struct i3c_master_controller *master,
+			     u8 start_addr);
+
+struct i3c_device *
+i3c_master_add_i3c_dev_locked(struct i3c_master_controller *master, u8 addr);
+void i3c_master_register_new_i3c_devs(struct i3c_master_controller *master);
+
+int i3c_master_set_info(struct i3c_master_controller *master,
+			const struct i3c_device_info *info);
+
+int i3c_master_register(struct i3c_master_controller *master,
+			struct device *parent,
+			const struct i3c_master_controller_ops *ops,
+			bool secondary);
+int i3c_master_unregister(struct i3c_master_controller *master);
+
+/**
+ * i3c_device_get_master_data() - get master private data attached to an I3C
+ *				  device
+ * @dev: the I3C dev to attach private data to
+ *
+ * Return: the private data previously attached with
+ *	   i3c_device_set_master_data() or NULL if no data has been attached
+ *	   to the device.
+ */
+static inline void *i3c_device_get_master_data(const struct i3c_device *dev)
+{
+	return dev->common.master_priv;
+}
+
+/**
+ * i3c_device_set_master_data() - attach master private data to an I3C device
+ * @dev: the I3C dev to attach private data to
+ * @data: private data
+ *
+ * This functions allows a master controller to attach per-device private data
+ * which can then be retrieved with i3c_device_get_master_data().
+ *
+ * Attaching private data to a device is usually done just after calling
+ * i3c_master_add_i3c_dev_locked().
+ */
+static inline void i3c_device_set_master_data(struct i3c_device *dev,
+					      void *data)
+{
+	dev->common.master_priv = data;
+}
+
+/**
+ * i2c_device_get_master_data() - get master private data attached to an I2C
+ *				  device
+ * @dev: the I2C dev to attach private data to
+ *
+ * Return: the private data previously attached with
+ *	   i2c_device_set_master_data() or NULL if no data has been attached
+ *	   to the device.
+ */
+static inline void *i2c_device_get_master_data(const struct i2c_device *dev)
+{
+	return dev->common.master_priv;
+}
+
+/**
+ * i2c_device_set_master_data() - attach master private data to an I2C device
+ * @dev: the I2C dev to attach private data to
+ * @data: private data
+ *
+ * This functions allows a master controller to attach per-device private data
+ * which can then be retrieved with i2c_device_get_master_data().
+ *
+ * Attaching private data to a device is usually done during
+ * &master_controller_ops->bus_init(), by iterating over all I2C devices
+ * instantiated by the core (using i3c_bus_for_each_i2cdev()).
+ */
+static inline void i2c_device_set_master_data(struct i2c_device *dev,
+					      void *data)
+{
+	dev->common.master_priv = data;
+}
+
+/**
+ * i3c_device_get_master() - get master used to communicate with a device
+ * @dev: I3C dev
+ *
+ * Return: the master controller driving @dev
+ */
+static inline struct i3c_master_controller *
+i3c_device_get_master(struct i3c_device *dev)
+{
+	return dev->common.master;
+}
+
+/**
+ * i3c_master_get_bus() - get the bus attached to a master
+ * @master: master object
+ *
+ * Return: the I3C bus @master is connected to
+ */
+static inline struct i3c_bus *
+i3c_master_get_bus(struct i3c_master_controller *master)
+{
+	return master->bus;
+}
+
+/**
+ * i3c_device_get_bus() - get the bus attached to a device
+ * @dev: an I3C device
+ *
+ * Return: the I3C bus @dev is connected to
+ */
+static inline struct i3c_bus *i3c_device_get_bus(struct i3c_device *dev)
+{
+	return i3c_master_get_bus(i3c_device_get_master(dev));
+}
+
+struct i3c_generic_ibi_pool;
+
+void i3c_device_init_ibi_slot(struct i3c_device *dev,
+			      struct i3c_ibi_slot *slot);
+struct i3c_generic_ibi_pool *
+i3c_generic_ibi_alloc_pool(struct i3c_device *dev,
+			   const struct i3c_ibi_setup *req);
+void i3c_generic_ibi_free_pool(struct i3c_generic_ibi_pool *pool);
+
+struct i3c_ibi_slot *
+i3c_generic_ibi_get_free_slot(struct i3c_generic_ibi_pool *pool);
+void i3c_generic_ibi_recycle_slot(struct i3c_generic_ibi_pool *pool,
+				  struct i3c_ibi_slot *slot);
+
+void i3c_device_queue_ibi(struct i3c_device *dev, struct i3c_ibi_slot *slot);
+
+struct i3c_ibi_slot *i3c_device_ibi_get_free_slot(struct i3c_device *dev);
+
+#endif /* I3C_MASTER_H */
diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h
index abb6dc2ebbf8..e59da92d8ac9 100644
--- a/include/linux/mod_devicetable.h
+++ b/include/linux/mod_devicetable.h
@@ -442,6 +442,23 @@  struct pci_epf_device_id {
 	kernel_ulong_t driver_data;
 };
 
+/* i3c */
+
+#define I3C_MATCH_DCR			BIT(0)
+#define I3C_MATCH_MANUF			BIT(1)
+#define I3C_MATCH_PART			BIT(2)
+#define I3C_MATCH_EXTRA_INFO		BIT(3)
+
+struct i3c_device_id {
+	__u8 match_flags;
+	__u8 dcr;
+	__u16 manuf_id;
+	__u16 part_id;
+	__u16 extra_info;
+
+	const void *data;
+};
+
 /* spi */
 
 #define SPI_NAME_SIZE	32