From patchwork Fri Jun 7 19:30:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bitan Biswas X-Patchwork-Id: 1112205 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-i2c-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="r67UJEj8"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45LCLH1qV0z9sN4 for ; Sat, 8 Jun 2019 05:30:47 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729972AbfFGTap (ORCPT ); Fri, 7 Jun 2019 15:30:45 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:15390 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729172AbfFGTao (ORCPT ); Fri, 7 Jun 2019 15:30:44 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 07 Jun 2019 12:30:28 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 07 Jun 2019 12:30:44 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 07 Jun 2019 12:30:44 -0700 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 7 Jun 2019 19:30:43 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 7 Jun 2019 19:30:43 +0000 Received: from dhcp-10-19-65-14.client.nvidia.com (Not Verified[10.19.65.14]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 07 Jun 2019 12:30:43 -0700 From: Bitan Biswas To: Laxman Dewangan , Thierry Reding , Jonathan Hunter , , , , Peter Rosin , Wolfram Sang , Dmitry Osipenko CC: Shardar Mohammed , Sowjanya Komatineni , Mantravadi Karthik , Bitan Biswas Subject: [PATCH V2 4/6] i2c: tegra: add spinlock definition comment Date: Fri, 7 Jun 2019 12:30:24 -0700 Message-ID: <1559935826-25812-4-git-send-email-bbiswas@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1559935826-25812-1-git-send-email-bbiswas@nvidia.com> References: <1559935826-25812-1-git-send-email-bbiswas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1559935828; bh=3cpCcddyT2qPq3Wnu1Z2qlvBOHM7S82lD9AAMomje2Q=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=r67UJEj8/fYJp+YNfFh+bY9VFP15TSLpWCCCe9PJJfy0PKslecpMH5qnbTU+YBJdz +NsC6/TWgrbKWZivTrcKecP5GRkin+efWo4J1ItvrJudWCvcLgk9O0pidbeXN1WH5o fwpgMgU6x4O0KhZKn9Fjus1RRrImSS++r+rWKm3rD/2UsI26ZTmbOFSl27dvf+B62C PxmoVqFLnt2ZPV9qSle15GVgRwdIjAP1YpVCGPgCjEiG9jvHV1HTeXrAUzjtvtRPwt wA3llUSEEPbCw1tK2SB3yS5Xsn6RME5tZYL/XkI63dPZiDr6M49Oq2b3jVdSVUMe7e twlum8+jQCnNg== Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Fix checkpatch.pl CHECK as follows: CHECK: spinlock_t definition without comment + spinlock_t xfer_lock; Signed-off-by: Bitan Biswas Reviewed-by: Dmitry Osipenko --- drivers/i2c/busses/i2c-tegra.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 2d381de..bececa6 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -269,6 +269,7 @@ struct tegra_i2c_dev { u32 bus_clk_rate; u16 clk_divisor_non_hs_mode; bool is_multimaster_mode; + /* xfer_lock: lock to serialize transfer submission and processing */ spinlock_t xfer_lock; struct dma_chan *tx_dma_chan; struct dma_chan *rx_dma_chan;