From patchwork Thu Jun 23 15:58:58 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 639733 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3rb5kr2kMZz9s5g for ; Fri, 24 Jun 2016 01:59:48 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751760AbcFWP7q (ORCPT ); Thu, 23 Jun 2016 11:59:46 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:4742 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751751AbcFWP7p (ORCPT ); Thu, 23 Jun 2016 11:59:45 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Thu, 23 Jun 2016 08:59:12 -0700 Received: from HQMAIL108.nvidia.com ([172.18.146.13]) by hqnvupgp08.nvidia.com (PGP Universal service); Thu, 23 Jun 2016 08:58:42 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Thu, 23 Jun 2016 08:58:42 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Thu, 23 Jun 2016 15:59:38 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Thu, 23 Jun 2016 15:59:38 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1130.7 via Frontend Transport; Thu, 23 Jun 2016 15:59:39 +0000 Received: from jonathanh-lm.nvidia.com (Not Verified[10.26.11.125]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Thu, 23 Jun 2016 08:59:37 -0700 From: Jon Hunter To: Thierry Reding , David Airlie , Stephen Warren , Alexandre Courbot , Wolfram Sang , Linus Walleij , Rob Herring , Mark Rutland CC: , , , , , Jon Hunter Subject: [PATCH 05/12] drm/tegra: Prepare DPAUX for supporting generic PM domains Date: Thu, 23 Jun 2016 16:58:58 +0100 Message-ID: <1466697545-11868-6-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1466697545-11868-1-git-send-email-jonathanh@nvidia.com> References: <1466697545-11868-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org To utilise the DPAUX on Tegra, the SOR power partition must be enabled. Now that Tegra supports the generic PM domain framework we manage the SOR power partition via this framework for DPAUX. However, the sequence for gating/ungating the SOR power partition requires that the DPAUX reset is asserted/de-asserted at the time the SOR power partition is gated/ungated, respectively. Now that the reset control core assumes that resets are exclusive, the Tegra generic PM domain code and the DPAUX driver cannot request the same reset unless we mark the resets as shared. Sharing resets we will not work in this case because we cannot guarantee that the reset is asserted/de-asserted at the appropriate time. Therefore, given that the Tegra generic PM domain code will handle the DPAUX reset, do not request the reset in the DPAUX driver if the DPAUX device has a PM domain associated. Signed-off-by: Jon Hunter --- drivers/gpu/drm/tegra/dpaux.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c index 4014ec57ed31..61821f457209 100644 --- a/drivers/gpu/drm/tegra/dpaux.c +++ b/drivers/gpu/drm/tegra/dpaux.c @@ -339,11 +339,14 @@ static int tegra_dpaux_probe(struct platform_device *pdev) return -ENXIO; } - dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux"); - if (IS_ERR(dpaux->rst)) { - dev_err(&pdev->dev, "failed to get reset control: %ld\n", - PTR_ERR(dpaux->rst)); - return PTR_ERR(dpaux->rst); + if (!pdev->dev.pm_domain) { + dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux"); + if (IS_ERR(dpaux->rst)) { + dev_err(&pdev->dev, + "failed to get reset control: %ld\n", + PTR_ERR(dpaux->rst)); + return PTR_ERR(dpaux->rst); + } } dpaux->clk = devm_clk_get(&pdev->dev, NULL); @@ -360,7 +363,8 @@ static int tegra_dpaux_probe(struct platform_device *pdev) return err; } - reset_control_deassert(dpaux->rst); + if (dpaux->rst) + reset_control_deassert(dpaux->rst); dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent"); if (IS_ERR(dpaux->clk_parent)) { @@ -438,7 +442,8 @@ static int tegra_dpaux_probe(struct platform_device *pdev) disable_parent_clk: clk_disable_unprepare(dpaux->clk_parent); assert_reset: - reset_control_assert(dpaux->rst); + if (dpaux->rst) + reset_control_assert(dpaux->rst); clk_disable_unprepare(dpaux->clk); return err; @@ -460,7 +465,8 @@ static int tegra_dpaux_remove(struct platform_device *pdev) cancel_work_sync(&dpaux->work); clk_disable_unprepare(dpaux->clk_parent); - reset_control_assert(dpaux->rst); + if (dpaux->rst) + reset_control_assert(dpaux->rst); clk_disable_unprepare(dpaux->clk); return 0;