From patchwork Mon May 16 20:09:31 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 622739 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3r7s4v45S6z9s5g for ; Tue, 17 May 2016 06:09:51 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b=nrPAYeEY; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754769AbcEPUJt (ORCPT ); Mon, 16 May 2016 16:09:49 -0400 Received: from mail-pf0-f180.google.com ([209.85.192.180]:33345 "EHLO mail-pf0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754733AbcEPUJr (ORCPT ); Mon, 16 May 2016 16:09:47 -0400 Received: by mail-pf0-f180.google.com with SMTP id 206so71231926pfu.0 for ; Mon, 16 May 2016 13:09:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id; bh=p4K0PRsAB/f5soNKKPkss+2Dat/i5a15yZMZq2LUMts=; b=nrPAYeEYITxopUYyv/fGoVLtuPaukoEqktT50DTW8blJl3DbcLkErqNcQ4qzuhf+CG Y2yXHzYEkbwPXKJqJteeXuUokcPD1lBltbcqQgUySUz+HzkfssKyU2FPQsTvVU7ZtZQ0 GxWyoePwcverge9gnwwwxe0A7KglV2vunD+vk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=p4K0PRsAB/f5soNKKPkss+2Dat/i5a15yZMZq2LUMts=; b=RuVeltlkaEkLp8ziSLd/EpXPc/sS8pmkCJn/FZ0EyhyfeVZUVkQ5C3IyNUYYPEWBst xgXy/A64DoQfkJGHrXkdNWxDL2BHa7LCJqajCfSiL0KGpcuCaJy4jdov77mZdSANtV1n 3fu3yH9WvqQabl3fS3VHJMURHjIklhLlxdLV2ejrWdekAGxOi4PlxLBEtpmJuMvuXGy+ KOK+qXtDIDrpXz41G76LD3ryn0mhQbGk7vDI+XB0xIh3lqc5IbWqeT+tYjelFDMJBHqG 3DmkH8LI6iBxBI+q3uLkVvs5y02Aa9C25rPnHO/z0KH8aqCag/XpXPgGCVHPnEtcFs68 SkqA== X-Gm-Message-State: AOPr4FV65vUXSxW0N5X2OXyE6/8aVmnZs7fmtJUDTD9KlP9dwlxCFHXQtdMkYpUqok9onQ== X-Received: by 10.98.48.71 with SMTP id w68mr47735740pfw.18.1463429386711; Mon, 16 May 2016 13:09:46 -0700 (PDT) Received: from tictac.mtv.corp.google.com ([172.22.65.76]) by smtp.gmail.com with ESMTPSA id bf4sm49285503pac.4.2016.05.16.13.09.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 16 May 2016 13:09:46 -0700 (PDT) From: Douglas Anderson To: Heiko Stuebner Cc: linux-rockchip@lists.infradead.org, david.wu@rock-chips.com, jay.xu@rock-chips.com, briannorris@chromium.org, wsa@the-dreams.de, linux-i2c@vger.kernel.org, Douglas Anderson , robh+dt@kernel.org, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, catalin.marinas@arm.com, will.deacon@arm.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] arm64: dts: rockchip: add i2c nodes for rk3399 Date: Mon, 16 May 2016 13:09:31 -0700 Message-Id: <1463429371-10950-1-git-send-email-dianders@chromium.org> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: David Wu We've got 9 (count em!) i2c controllers on rk3399, some of which are in the PMU power domain and some of which are normal peripherals. Add them all to the main rk3399 dtsi file so future patches can turn them on in the board dts files. Note: by default we try to set the i2c clock rate to 200 MHz so that we can achieve good i2c functional clock rates. 200 MHz gives us the ability to make very close to 100 kHz / 400 kHz / 1 MHz rates. If boards want to tune clock rates further they can always override. Possibly boards could want to tune this if: - they wanted to save an infinitesimal amount of power and they knew their i2c bus was slow anyway. Since we gate the functional clock when the i2c bus is not active, power savings would only be while i2c transfers were happening and probably won't be very big anyway. - they wanted to eek out a bit more speed by carefully tuning the source clock to make divisions work out perfectly, accounting for the rise / fall time measured on an actual board. Note also that we still request 200 MHz for the PMU i2c busses even though we expect that we won't make that exactly (currently PPLL is 676 MHz which gives us 169 MHz). Signed-off-by: David Wu Signed-off-by: Jianqun Xu [dianders: wrote desc; put in assigned-clocks; reordered nodes] Signed-off-by: Douglas Anderson --- Note: this patch is based upon David Wu's patch series to add rk3399 support to i2c-rk3x.c and shouldn't land until at least device tree bindings land. arch/arm64/boot/dts/rockchip/rk3399.dtsi | 144 +++++++++++++++++++++++++++++++ 1 file changed, 144 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 46f325a143b0..753a91728b4c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -54,6 +54,15 @@ #size-cells = <2>; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -272,6 +281,96 @@ }; }; + i2c1: i2c@ff110000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff110000 0x0 0x1000>; + assigned-clocks = <&cru SCLK_I2C1>; + assigned-clock-rates = <200000000>; + clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@ff120000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff120000 0x0 0x1000>; + assigned-clocks = <&cru SCLK_I2C2>; + assigned-clock-rates = <200000000>; + clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@ff130000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff130000 0x0 0x1000>; + assigned-clocks = <&cru SCLK_I2C3>; + assigned-clock-rates = <200000000>; + clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@ff140000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff140000 0x0 0x1000>; + assigned-clocks = <&cru SCLK_I2C5>; + assigned-clock-rates = <200000000>; + clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@ff150000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff150000 0x0 0x1000>; + assigned-clocks = <&cru SCLK_I2C6>; + assigned-clock-rates = <200000000>; + clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@ff160000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff160000 0x0 0x1000>; + assigned-clocks = <&cru SCLK_I2C7>; + assigned-clock-rates = <200000000>; + clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + uart0: serial@ff180000 { compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; reg = <0x0 0xff180000 0x0 0x100>; @@ -420,6 +519,51 @@ status = "disabled"; }; + i2c0: i2c@ff3c0000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff3c0000 0x0 0x1000>; + assigned-clocks = <&pmucru SCLK_I2C0_PMU>; + assigned-clock-rates = <200000000>; + clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@ff3d0000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff3d0000 0x0 0x1000>; + assigned-clocks = <&pmucru SCLK_I2C4_PMU>; + assigned-clock-rates = <200000000>; + clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@ff3e0000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff3e0000 0x0 0x1000>; + assigned-clocks = <&pmucru SCLK_I2C8_PMU>; + assigned-clock-rates = <200000000>; + clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pwm0: pwm@ff420000 { compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; reg = <0x0 0xff420000 0x0 0x10>;