From patchwork Fri Aug 14 15:50:45 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sifan Naeem X-Patchwork-Id: 507482 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 8FFEB1401EF for ; Sat, 15 Aug 2015 01:48:16 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755466AbbHNPsN (ORCPT ); Fri, 14 Aug 2015 11:48:13 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:2467 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755437AbbHNPsI (ORCPT ); Fri, 14 Aug 2015 11:48:08 -0400 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 30E65F6DDF6DD; Fri, 14 Aug 2015 16:48:04 +0100 (IST) Received: from hhmail02.hh.imgtec.org (10.100.10.20) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Fri, 14 Aug 2015 16:48:06 +0100 Received: from iw-build-3.kl.imgtec.org (192.168.167.63) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.235.1; Fri, 14 Aug 2015 16:48:06 +0100 From: Sifan Naeem To: Wolfram Sang , James Hogan , , Ezequiel Garcia CC: Ionela Voinescu , Sifan Naeem Subject: [PATCH v2 4/5] i2c: img-scb: add handle for Master halt interrupt Date: Fri, 14 Aug 2015 16:50:45 +0100 Message-ID: <1439567447-8139-5-git-send-email-sifan.naeem@imgtec.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1439567447-8139-1-git-send-email-sifan.naeem@imgtec.com> References: <1439567447-8139-1-git-send-email-sifan.naeem@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.167.63] Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Master halt is issued after each byte of a transaction is processed in IP version 3.3. Master halt will stall the bus by holding the SCK line low until the halt bit in the scb_general_control is cleared. After the last byte of a transfer is processed we can use the Master Halt interrupt to facilitate a repeated start transfer without issuing a stop bit. Signed-off-by: Sifan Naeem Reviewed-by: James Hartley --- drivers/i2c/busses/i2c-img-scb.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/i2c/busses/i2c-img-scb.c b/drivers/i2c/busses/i2c-img-scb.c index 17e13ff475bb..837a73a43a6d 100644 --- a/drivers/i2c/busses/i2c-img-scb.c +++ b/drivers/i2c/busses/i2c-img-scb.c @@ -151,6 +151,7 @@ #define INT_FIFO_EMPTYING BIT(12) #define INT_TRANSACTION_DONE BIT(15) #define INT_SLAVE_EVENT BIT(16) +#define INT_MASTER_HALTED BIT(17) #define INT_TIMING BIT(18) #define INT_STOP_DETECTED BIT(19) @@ -177,6 +178,7 @@ INT_FIFO_FULL | \ INT_FIFO_FILLING | \ INT_FIFO_EMPTY | \ + INT_MASTER_HALTED | \ INT_STOP_DETECTED) #define INT_ENABLE_MASK_WAITSTOP (INT_SLAVE_EVENT | \ @@ -883,17 +885,26 @@ static unsigned int img_i2c_auto(struct img_i2c *i2c, } if (i2c->msg.flags & I2C_M_RD) { - if (int_status & INT_FIFO_FULL_FILLING) { + if (int_status & (INT_FIFO_FULL_FILLING | INT_MASTER_HALTED)) { img_i2c_read_fifo(i2c); if (i2c->msg.len == 0) return ISR_WAITSTOP; } } else { - if (int_status & INT_FIFO_EMPTY) { - if (i2c->msg.len == 0) + if (int_status & (INT_FIFO_EMPTY | INT_MASTER_HALTED)) { + if ((int_status & INT_FIFO_EMPTY) && + i2c->msg.len == 0) return ISR_WAITSTOP; img_i2c_write_fifo(i2c); } + } + if (int_status & INT_MASTER_HALTED) { + /* + * Release and then enable transaction halt, to + * allow only a single byte to proceed. + */ + img_i2c_transaction_halt(i2c, false); + img_i2c_transaction_halt(i2c, !i2c->last_msg); } return 0;