From patchwork Thu Jan 16 07:34:28 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shane Huang X-Patchwork-Id: 311604 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id EC29F2C0092 for ; Thu, 16 Jan 2014 18:35:12 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751215AbaAPHfL (ORCPT ); Thu, 16 Jan 2014 02:35:11 -0500 Received: from tx2ehsobe005.messaging.microsoft.com ([65.55.88.15]:55467 "EHLO tx2outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750910AbaAPHfK (ORCPT ); Thu, 16 Jan 2014 02:35:10 -0500 Received: from mail20-tx2-R.bigfish.com (10.9.14.237) by TX2EHSOBE003.bigfish.com (10.9.40.23) with Microsoft SMTP Server id 14.1.225.22; Thu, 16 Jan 2014 07:35:09 +0000 Received: from mail20-tx2 (localhost [127.0.0.1]) by mail20-tx2-R.bigfish.com (Postfix) with ESMTP id 51BC9A0274; Thu, 16 Jan 2014 07:35:09 +0000 (UTC) X-Forefront-Antispam-Report: CIP:165.204.84.222; KIP:(null); UIP:(null); IPV:NLI; H:atltwp02.amd.com; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VPS0(zzzz1f42h2148h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah1fc6hzz1de098h8275bh1de097hz2dh839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h14ddh1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah2222h224fh1d0ch1d2eh1d3fh1dc1h1dfeh1dffh1e1dh1e23h1fe8h1ff5h2218h2216h226dh22d0h2327h2336h2438h2461h2487h1155h) Received: from mail20-tx2 (localhost.localdomain [127.0.0.1]) by mail20-tx2 (MessageSwitch) id 1389857707789559_11482; Thu, 16 Jan 2014 07:35:07 +0000 (UTC) Received: from TX2EHSMHS037.bigfish.com (unknown [10.9.14.243]) by mail20-tx2.bigfish.com (Postfix) with ESMTP id B61C038005D; Thu, 16 Jan 2014 07:35:07 +0000 (UTC) Received: from atltwp02.amd.com (165.204.84.222) by TX2EHSMHS037.bigfish.com (10.9.99.137) with Microsoft SMTP Server id 14.16.227.3; Thu, 16 Jan 2014 07:34:58 +0000 X-WSS-ID: 0MZHH0A-08-9HV-02 X-M-MSG: Received: from satlvexedge01.amd.com (satlvexedge01.amd.com [10.177.96.28]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by atltwp02.amd.com (Axway MailGate 5.2.1) with ESMTPS id 26214D16012; Thu, 16 Jan 2014 01:33:45 -0600 (CST) Received: from SATLEXDAG05.amd.com (10.181.40.11) by satlvexedge01.amd.com (10.177.96.28) with Microsoft SMTP Server (TLS) id 14.2.328.9; Thu, 16 Jan 2014 01:35:25 -0600 Received: from SCYBEXDAG02.amd.com (10.34.11.12) by satlexdag05.amd.com (10.181.40.11) with Microsoft SMTP Server (TLS) id 14.2.328.9; Thu, 16 Jan 2014 02:32:16 -0500 Received: from shane-BANTRY.amd.com (139.95.108.50) by SCYBEXDAG02.amd.com (10.34.11.12) with Microsoft SMTP Server id 14.2.328.9; Thu, 16 Jan 2014 15:34:53 +0800 From: Shane Huang To: Jean Delvare CC: , Shane Huang Subject: [PATCH RESEND] i2c-piix4: AMD new SMBus base address location changed Date: Wed, 15 Jan 2014 23:34:28 -0800 Message-ID: <1389857668-4428-1-git-send-email-shane.huang@amd.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-OriginatorOrg: amd.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org This patch is to support AMD new SMBus with different base address location. Signed-off-by: Shane Huang --- drivers/i2c/busses/i2c-piix4.c | 39 +++++++++++++++++++++++++++------------ 1 file changed, 27 insertions(+), 12 deletions(-) diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c index a028617..44d5ebe 100644 --- a/drivers/i2c/busses/i2c-piix4.c +++ b/drivers/i2c/busses/i2c-piix4.c @@ -230,12 +230,13 @@ static int piix4_setup(struct pci_dev *PIIX4_dev, return piix4_smba; } -static int piix4_setup_sb800(struct pci_dev *PIIX4_dev, - const struct pci_device_id *id, u8 aux) +static int piix4_setup_amd(struct pci_dev *PIIX4_dev, + const struct pci_device_id *id, u8 aux) { unsigned short piix4_smba; unsigned short smba_idx = 0xcd6; - u8 smba_en_lo, smba_en_hi, i2ccfg, i2ccfg_offset = 0x10, smb_en; + u8 smba_en_lo, smba_en_hi, smb_en, smb_en_status; + u8 i2ccfg, i2ccfg_offset = 0x10; /* SB800 and later SMBus does not support forcing address */ if (force || force_addr) { @@ -245,7 +246,11 @@ static int piix4_setup_sb800(struct pci_dev *PIIX4_dev, } /* Determine the address of the SMBus areas */ - smb_en = (aux) ? 0x28 : 0x2c; + if (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD && + PIIX4_dev->revision >= 0x41) + smb_en = 0; + else + smb_en = (aux) ? 0x28 : 0x2c; if (!request_region(smba_idx, 2, "smba_idx")) { dev_err(&PIIX4_dev->dev, "SMBus base address index region " @@ -258,13 +263,23 @@ static int piix4_setup_sb800(struct pci_dev *PIIX4_dev, smba_en_hi = inb_p(smba_idx + 1); release_region(smba_idx, 2); - if ((smba_en_lo & 1) == 0) { + if (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD && + PIIX4_dev->revision >= 0x41) { + smb_en_status = smba_en_lo & 0x10; + piix4_smba = smba_en_hi << 8; + if (aux) + piix4_smba |= 0x20; + } else { + smb_en_status = smba_en_lo & 1; + piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0; + } + + if (!smb_en_status) { dev_err(&PIIX4_dev->dev, "Host SMBus controller not enabled!\n"); return -ENODEV; } - piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0; if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) return -ENODEV; @@ -277,7 +292,7 @@ static int piix4_setup_sb800(struct pci_dev *PIIX4_dev, /* Aux SMBus does not support IRQ information */ if (aux) { dev_info(&PIIX4_dev->dev, - "SMBus Host Controller at 0x%x\n", piix4_smba); + "Auxiliary SMBus controller at 0x%x\n", piix4_smba); return piix4_smba; } @@ -297,7 +312,7 @@ static int piix4_setup_sb800(struct pci_dev *PIIX4_dev, dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus.\n"); dev_info(&PIIX4_dev->dev, - "SMBus Host Controller at 0x%x, revision %d\n", + "SMBus controller at 0x%x, revision %d\n", piix4_smba, i2ccfg >> 4); return piix4_smba; @@ -605,8 +620,8 @@ static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id) dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS && dev->revision >= 0x40) || dev->vendor == PCI_VENDOR_ID_AMD) - /* base address location etc changed in SB800 */ - retval = piix4_setup_sb800(dev, id, 0); + /* base address location etc changed from SB800 */ + retval = piix4_setup_amd(dev, id, 0); else retval = piix4_setup(dev, id); @@ -628,13 +643,13 @@ static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id) retval = piix4_setup_aux(dev, id, 0x58); } else { /* SB800 added aux bus too */ - retval = piix4_setup_sb800(dev, id, 1); + retval = piix4_setup_amd(dev, id, 1); } } if (dev->vendor == PCI_VENDOR_ID_AMD && dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) { - retval = piix4_setup_sb800(dev, id, 1); + retval = piix4_setup_amd(dev, id, 1); } if (retval > 0) {