From patchwork Mon Sep 16 22:06:25 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: York Sun X-Patchwork-Id: 275294 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 8F9D22C00C0 for ; Tue, 17 Sep 2013 08:06:31 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751104Ab3IPWGa (ORCPT ); Mon, 16 Sep 2013 18:06:30 -0400 Received: from tx2ehsobe005.messaging.microsoft.com ([65.55.88.15]:27186 "EHLO tx2outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751044Ab3IPWGa (ORCPT ); Mon, 16 Sep 2013 18:06:30 -0400 Received: from mail54-tx2-R.bigfish.com (10.9.14.237) by TX2EHSOBE006.bigfish.com (10.9.40.26) with Microsoft SMTP Server id 14.1.225.22; Mon, 16 Sep 2013 22:06:29 +0000 Received: from mail54-tx2 (localhost [127.0.0.1]) by mail54-tx2-R.bigfish.com (Postfix) with ESMTP id 7B1242202C0; Mon, 16 Sep 2013 22:06:29 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: -1 X-BigFish: VS-1(zz154dIzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hzz1de098h1de097h8275bhz2dh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh1fb3h1d0ch1d2eh1d3fh1dc1h1dfeh1dffh1e23h1fe8h1ff5h1155h) Received: from mail54-tx2 (localhost.localdomain [127.0.0.1]) by mail54-tx2 (MessageSwitch) id 1379369187745888_26609; Mon, 16 Sep 2013 22:06:27 +0000 (UTC) Received: from TX2EHSMHS005.bigfish.com (unknown [10.9.14.250]) by mail54-tx2.bigfish.com (Postfix) with ESMTP id AB3EE4004D; Mon, 16 Sep 2013 22:06:27 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by TX2EHSMHS005.bigfish.com (10.9.99.105) with Microsoft SMTP Server (TLS) id 14.16.227.3; Mon, 16 Sep 2013 22:06:27 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server (TLS) id 14.3.158.2; Mon, 16 Sep 2013 22:06:26 +0000 Received: from oslab-l1.am.freescale.net ([10.214.85.196]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id r8GM6PpD007756; Mon, 16 Sep 2013 15:06:25 -0700 From: York Sun To: CC: Subject: [Patch v2] power/mpc85xx: Add delay after enabling I2C master Date: Mon, 16 Sep 2013 15:06:25 -0700 Message-ID: <1379369185-14590-1-git-send-email-yorksun@freescale.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Erratum A-006037 indicates I2C controller executes the write to I2CCR only after it sees SCL idle for 64K cycle of internal I2C controller clocks. If during this waiting period, I2C controller is disabled (I2CCR[MEN] set to 0), then the controller could end in bad state, and hang the future access to I2C register. The mpc_i2c_fixup() function tries to recover the bus from a stalled state where the 9th clock pulse wasn't generated. However, this workaround disables and enables I2C controller without meeting waiting requirement of this erratum. This erratum applies to some 85xx SoCs. It is safe to apply to all of them for mpc_i2c_fixup(). Signed-off-by: York Sun --- Change log: v2: remote reviewed-by and tested-by lines added by gerrit send to proper mailing list drivers/i2c/busses/i2c-mpc.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c index b80c768..55dce43 100644 --- a/drivers/i2c/busses/i2c-mpc.c +++ b/drivers/i2c/busses/i2c-mpc.c @@ -106,7 +106,12 @@ static irqreturn_t mpc_i2c_isr(int irq, void *dev_id) static void mpc_i2c_fixup(struct mpc_i2c *i2c) { int k; - u32 delay_val = 1000000 / i2c->real_clk + 1; + u32 delay_val; +#ifdef CONFIG_PPC_85xx + delay_val = 65536 / (fsl_get_sys_freq() / 2000000); /* 64K cycle */ +#else + delay_val = 1000000 / i2c->real_clk + 1; +#endif if (delay_val < 2) delay_val = 2; @@ -116,7 +121,11 @@ static void mpc_i2c_fixup(struct mpc_i2c *i2c) writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN); udelay(delay_val); writeccr(i2c, CCR_MEN); +#ifdef CONFIG_PPC_85xx + udelay(delay_val); +#else udelay(delay_val << 1); +#endif } }