| Message ID | d3907b56-e346-f246-694e-6088d060bd27@cogentembedded.com |
|---|---|
| State | New |
| Headers | show |
| Series | pinctrl: sh-pfc: r8a77970: add RPC pins, groups, and functions | expand |
Hi Sergei, On Thu, Jun 18, 2020 at 9:46 PM Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > Subject: pinctrl: sh-pfc: r8a77970: Add RPC pins, groups, and functions > > Add the RPC pins/groups/functions to the R8A77970 PFC driver. > They can be used if an Octal-SPI flash or HyperFlash is connected. > > Based on the patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>. > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Thanks for your patch! > --- renesas-drivers.orig/drivers/pinctrl/sh-pfc/pfc-r8a77970.c > +++ renesas-drivers/drivers/pinctrl/sh-pfc/pfc-r8a77970.c > @@ -1416,6 +1416,64 @@ static const unsigned int qspi1_data4_mu > QSPI1_IO2_MARK, QSPI1_IO3_MARK > }; > > +/* - RPC -------------------------------------------------------------------- */ > +static const unsigned int rpc_clk1_pins[] = { > + /* Octal-SPI flash: C/SCLK */ > + RCAR_GP_PIN(5, 0), > +}; > +static const unsigned int rpc_clk1_mux[] = { > + QSPI0_SPCLK_MARK, > +}; > +static const unsigned int rpc_clk2_pins[] = { > + /* HyperFlash: CK, CK# */ > + RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6), > +}; > +static const unsigned int rpc_clk2_mux[] = { > + QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK, > +}; > +static const unsigned int rpc_ctrl_pins[] = { > + /* Octal-SPI flash: S#/CS, DQS */ > + /* HyperFlash: CS#, RDS */ > + RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11), > +}; > +static const unsigned int rpc_ctrl_mux[] = { > + QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, Shouldn't the above read QSPI0_SSL_MARK, QSPI1_SSL_MARK, ? I seem to have overlooked the same issue in commit aa2165cf2ece9176 ("pinctrl: sh-pfc: r8a77980: Add RPC pins, groups, and functions") in sh-pfc-for-v5.9, which I can fix myself. With the above sorted out: Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> and will queue in sh-pfc-for-v5.9 after fixing. Gr{oetje,eeting}s, Geert
On 06/19/2020 03:58 PM, Geert Uytterhoeven wrote: >> From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> >> Subject: pinctrl: sh-pfc: r8a77970: Add RPC pins, groups, and functions >> >> Add the RPC pins/groups/functions to the R8A77970 PFC driver. >> They can be used if an Octal-SPI flash or HyperFlash is connected. >> >> Based on the patch by Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>. >> >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > > Thanks for your patch! > >> --- renesas-drivers.orig/drivers/pinctrl/sh-pfc/pfc-r8a77970.c >> +++ renesas-drivers/drivers/pinctrl/sh-pfc/pfc-r8a77970.c >> @@ -1416,6 +1416,64 @@ static const unsigned int qspi1_data4_mu >> QSPI1_IO2_MARK, QSPI1_IO3_MARK >> }; >> >> +/* - RPC -------------------------------------------------------------------- */ >> +static const unsigned int rpc_clk1_pins[] = { >> + /* Octal-SPI flash: C/SCLK */ >> + RCAR_GP_PIN(5, 0), >> +}; >> +static const unsigned int rpc_clk1_mux[] = { >> + QSPI0_SPCLK_MARK, >> +}; >> +static const unsigned int rpc_clk2_pins[] = { >> + /* HyperFlash: CK, CK# */ >> + RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6), >> +}; >> +static const unsigned int rpc_clk2_mux[] = { >> + QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK, >> +}; >> +static const unsigned int rpc_ctrl_pins[] = { >> + /* Octal-SPI flash: S#/CS, DQS */ >> + /* HyperFlash: CS#, RDS */ >> + RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11), >> +}; >> +static const unsigned int rpc_ctrl_mux[] = { >> + QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, > > Shouldn't the above read > > QSPI0_SSL_MARK, QSPI1_SSL_MARK, > > ? Indeed! Stupid copy&paste error... :-( > I seem to have overlooked the same issue in commit aa2165cf2ece9176 > ("pinctrl: sh-pfc: r8a77980: Add RPC pins, groups, and functions") in > sh-pfc-for-v5.9, which I can fix myself. > > With the above sorted out: > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > and will queue in sh-pfc-for-v5.9 after fixing. So I do need to repost? OK... > Gr{oetje,eeting}s, > > Geert MBR, Sergei
Index: renesas-drivers/drivers/pinctrl/sh-pfc/pfc-r8a77970.c =================================================================== --- renesas-drivers.orig/drivers/pinctrl/sh-pfc/pfc-r8a77970.c +++ renesas-drivers/drivers/pinctrl/sh-pfc/pfc-r8a77970.c @@ -1416,6 +1416,64 @@ static const unsigned int qspi1_data4_mu QSPI1_IO2_MARK, QSPI1_IO3_MARK }; +/* - RPC -------------------------------------------------------------------- */ +static const unsigned int rpc_clk1_pins[] = { + /* Octal-SPI flash: C/SCLK */ + RCAR_GP_PIN(5, 0), +}; +static const unsigned int rpc_clk1_mux[] = { + QSPI0_SPCLK_MARK, +}; +static const unsigned int rpc_clk2_pins[] = { + /* HyperFlash: CK, CK# */ + RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6), +}; +static const unsigned int rpc_clk2_mux[] = { + QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK, +}; +static const unsigned int rpc_ctrl_pins[] = { + /* Octal-SPI flash: S#/CS, DQS */ + /* HyperFlash: CS#, RDS */ + RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11), +}; +static const unsigned int rpc_ctrl_mux[] = { + QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, +}; +static const unsigned int rpc_data_pins[] = { + /* DQ[0:7] */ + RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), + RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), + RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), + RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), +}; +static const unsigned int rpc_data_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, + QSPI0_IO2_MARK, QSPI0_IO3_MARK, + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, + QSPI1_IO2_MARK, QSPI1_IO3_MARK, +}; +static const unsigned int rpc_reset_pins[] = { + /* RPC_RESET# */ + RCAR_GP_PIN(5, 12), +}; +static const unsigned int rpc_reset_mux[] = { + RPC_RESET_N_MARK, +}; +static const unsigned int rpc_int_pins[] = { + /* RPC_INT# */ + RCAR_GP_PIN(5, 14), +}; +static const unsigned int rpc_int_mux[] = { + RPC_INT_N_MARK, +}; +static const unsigned int rpc_wp_pins[] = { + /* RPC_WP# */ + RCAR_GP_PIN(5, 13), +}; +static const unsigned int rpc_wp_mux[] = { + RPC_WP_N_MARK, +}; + /* - SCIF Clock ------------------------------------------------------------- */ static const unsigned int scif_clk_a_pins[] = { /* SCIF_CLK */ @@ -1750,6 +1808,13 @@ static const struct sh_pfc_pin_group pin SH_PFC_PIN_GROUP(qspi1_ctrl), SH_PFC_PIN_GROUP(qspi1_data2), SH_PFC_PIN_GROUP(qspi1_data4), + SH_PFC_PIN_GROUP(rpc_clk1), + SH_PFC_PIN_GROUP(rpc_clk2), + SH_PFC_PIN_GROUP(rpc_ctrl), + SH_PFC_PIN_GROUP(rpc_data), + SH_PFC_PIN_GROUP(rpc_reset), + SH_PFC_PIN_GROUP(rpc_int), + SH_PFC_PIN_GROUP(rpc_wp), SH_PFC_PIN_GROUP(scif_clk_a), SH_PFC_PIN_GROUP(scif_clk_b), SH_PFC_PIN_GROUP(scif0_data), @@ -1954,6 +2019,16 @@ static const char * const qspi1_groups[] "qspi1_data4", }; +static const char * const rpc_groups[] = { + "rpc_clk1", + "rpc_clk2", + "rpc_ctrl", + "rpc_data", + "rpc_reset", + "rpc_int", + "rpc_wp", +}; + static const char * const scif_clk_groups[] = { "scif_clk_a", "scif_clk_b", @@ -2039,6 +2114,7 @@ static const struct sh_pfc_function pinm SH_PFC_FUNCTION(pwm4), SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(qspi1), + SH_PFC_FUNCTION(rpc), SH_PFC_FUNCTION(scif_clk), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1),