From patchwork Thu Mar 9 16:22:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julia Cartwright X-Patchwork-Id: 737065 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vfGz31rDlz9s7k for ; Fri, 10 Mar 2017 04:07:11 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932542AbdCIRG5 (ORCPT ); Thu, 9 Mar 2017 12:06:57 -0500 Received: from mx0a-00010702.pphosted.com ([148.163.156.75]:49496 "EHLO mx0b-00010702.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932767AbdCIRG4 (ORCPT ); Thu, 9 Mar 2017 12:06:56 -0500 Received: from pps.filterd (m0098781.ppops.net [127.0.0.1]) by mx0a-00010702.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v29GKpAj006320; Thu, 9 Mar 2017 10:22:15 -0600 Received: from ni.com (skprod2.natinst.com [130.164.80.23]) by mx0a-00010702.pphosted.com with ESMTP id 292xcdtfjs-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 09 Mar 2017 10:22:14 -0600 Received: from us-aus-exch2.ni.corp.natinst.com (us-aus-exch2.ni.corp.natinst.com [130.164.68.12]) by us-aus-skprod2.natinst.com (8.16.0.17/8.16.0.17) with ESMTPS id v29GMDUZ008773 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 9 Mar 2017 10:22:13 -0600 Received: from us-aus-exhub2.ni.corp.natinst.com (130.164.68.32) by us-aus-exch2.ni.corp.natinst.com (130.164.68.12) with Microsoft SMTP Server (TLS) id 15.0.1156.6; Thu, 9 Mar 2017 10:22:13 -0600 Received: from jcartwri.amer.corp.natinst.com (130.164.49.7) by us-aus-exhub2.ni.corp.natinst.com (130.164.68.32) with Microsoft SMTP Server id 15.0.1156.6 via Frontend Transport; Thu, 9 Mar 2017 10:22:13 -0600 Received: by jcartwri.amer.corp.natinst.com (Postfix, from userid 1000) id B7C6630111D; Thu, 9 Mar 2017 10:22:13 -0600 (CST) From: Julia Cartwright To: Linus Walleij , Barry Song CC: , Thomas Gleixner , , Subject: [PATCH 18/19] pinctrl: sirf: atlas7: make use of raw_spinlock variants Date: Thu, 9 Mar 2017 10:22:05 -0600 Message-ID: X-Mailer: git-send-email 2.11.1 In-Reply-To: References: MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-03-09_13:, , signatures=0 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 spamscore=0 suspectscore=2 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1702020001 definitions=main-1703090122 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-03-09_13:, , signatures=0 X-Proofpoint-Spam-Details: rule=notspam policy=default score=30 priorityscore=1501 malwarescore=0 suspectscore=8 phishscore=0 bulkscore=0 spamscore=0 clxscore=1011 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=30 reason=mlx scancount=1 engine=8.0.1-1702020001 definitions=main-1703090122 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The sirf atlas7 pinctrl drivers currently implement an irq_chip for handling interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. Signed-off-by: Julia Cartwright --- drivers/pinctrl/sirf/pinctrl-atlas7.c | 44 +++++++++++++++++------------------ 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c b/drivers/pinctrl/sirf/pinctrl-atlas7.c index 600d6427a978..1efa315a7dbe 100644 --- a/drivers/pinctrl/sirf/pinctrl-atlas7.c +++ b/drivers/pinctrl/sirf/pinctrl-atlas7.c @@ -352,7 +352,7 @@ struct atlas7_gpio_chip { void __iomem *reg; struct clk *clk; int nbank; - spinlock_t lock; + raw_spinlock_t lock; struct gpio_chip chip; struct atlas7_gpio_bank banks[0]; }; @@ -5650,13 +5650,13 @@ static void atlas7_gpio_irq_ack(struct irq_data *d) pin_in_bank = d->hwirq - bank->gpio_offset; ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank); - spin_lock_irqsave(&a7gc->lock, flags); + raw_spin_lock_irqsave(&a7gc->lock, flags); val = readl(ctrl_reg); /* clear interrupt status */ writel(val, ctrl_reg); - spin_unlock_irqrestore(&a7gc->lock, flags); + raw_spin_unlock_irqrestore(&a7gc->lock, flags); } static void __atlas7_gpio_irq_mask(struct atlas7_gpio_chip *a7gc, int idx) @@ -5681,11 +5681,11 @@ static void atlas7_gpio_irq_mask(struct irq_data *d) struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc); unsigned long flags; - spin_lock_irqsave(&a7gc->lock, flags); + raw_spin_lock_irqsave(&a7gc->lock, flags); __atlas7_gpio_irq_mask(a7gc, d->hwirq); - spin_unlock_irqrestore(&a7gc->lock, flags); + raw_spin_unlock_irqrestore(&a7gc->lock, flags); } static void atlas7_gpio_irq_unmask(struct irq_data *d) @@ -5701,14 +5701,14 @@ static void atlas7_gpio_irq_unmask(struct irq_data *d) pin_in_bank = d->hwirq - bank->gpio_offset; ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank); - spin_lock_irqsave(&a7gc->lock, flags); + raw_spin_lock_irqsave(&a7gc->lock, flags); val = readl(ctrl_reg); val &= ~ATLAS7_GPIO_CTL_INTR_STATUS_MASK; val |= ATLAS7_GPIO_CTL_INTR_EN_MASK; writel(val, ctrl_reg); - spin_unlock_irqrestore(&a7gc->lock, flags); + raw_spin_unlock_irqrestore(&a7gc->lock, flags); } static int atlas7_gpio_irq_type(struct irq_data *d, @@ -5725,7 +5725,7 @@ static int atlas7_gpio_irq_type(struct irq_data *d, pin_in_bank = d->hwirq - bank->gpio_offset; ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank); - spin_lock_irqsave(&a7gc->lock, flags); + raw_spin_lock_irqsave(&a7gc->lock, flags); val = readl(ctrl_reg); val &= ~(ATLAS7_GPIO_CTL_INTR_STATUS_MASK | @@ -5768,7 +5768,7 @@ static int atlas7_gpio_irq_type(struct irq_data *d, writel(val, ctrl_reg); - spin_unlock_irqrestore(&a7gc->lock, flags); + raw_spin_unlock_irqrestore(&a7gc->lock, flags); return 0; } @@ -5863,7 +5863,7 @@ static int atlas7_gpio_request(struct gpio_chip *chip, if (pinctrl_request_gpio(chip->base + gpio)) return -ENODEV; - spin_lock_irqsave(&a7gc->lock, flags); + raw_spin_lock_irqsave(&a7gc->lock, flags); /* * default status: @@ -5872,7 +5872,7 @@ static int atlas7_gpio_request(struct gpio_chip *chip, __atlas7_gpio_set_input(a7gc, gpio); __atlas7_gpio_irq_mask(a7gc, gpio); - spin_unlock_irqrestore(&a7gc->lock, flags); + raw_spin_unlock_irqrestore(&a7gc->lock, flags); return 0; } @@ -5883,12 +5883,12 @@ static void atlas7_gpio_free(struct gpio_chip *chip, struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip); unsigned long flags; - spin_lock_irqsave(&a7gc->lock, flags); + raw_spin_lock_irqsave(&a7gc->lock, flags); __atlas7_gpio_irq_mask(a7gc, gpio); __atlas7_gpio_set_input(a7gc, gpio); - spin_unlock_irqrestore(&a7gc->lock, flags); + raw_spin_unlock_irqrestore(&a7gc->lock, flags); pinctrl_free_gpio(chip->base + gpio); } @@ -5899,11 +5899,11 @@ static int atlas7_gpio_direction_input(struct gpio_chip *chip, struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip); unsigned long flags; - spin_lock_irqsave(&a7gc->lock, flags); + raw_spin_lock_irqsave(&a7gc->lock, flags); __atlas7_gpio_set_input(a7gc, gpio); - spin_unlock_irqrestore(&a7gc->lock, flags); + raw_spin_unlock_irqrestore(&a7gc->lock, flags); return 0; } @@ -5936,11 +5936,11 @@ static int atlas7_gpio_direction_output(struct gpio_chip *chip, struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip); unsigned long flags; - spin_lock_irqsave(&a7gc->lock, flags); + raw_spin_lock_irqsave(&a7gc->lock, flags); __atlas7_gpio_set_output(a7gc, gpio, value); - spin_unlock_irqrestore(&a7gc->lock, flags); + raw_spin_unlock_irqrestore(&a7gc->lock, flags); return 0; } @@ -5956,11 +5956,11 @@ static int atlas7_gpio_get_value(struct gpio_chip *chip, bank = atlas7_gpio_to_bank(a7gc, gpio); pin_in_bank = gpio - bank->gpio_offset; - spin_lock_irqsave(&a7gc->lock, flags); + raw_spin_lock_irqsave(&a7gc->lock, flags); val = readl(ATLAS7_GPIO_CTRL(bank, pin_in_bank)); - spin_unlock_irqrestore(&a7gc->lock, flags); + raw_spin_unlock_irqrestore(&a7gc->lock, flags); return !!(val & ATLAS7_GPIO_CTL_DATAIN_MASK); } @@ -5978,7 +5978,7 @@ static void atlas7_gpio_set_value(struct gpio_chip *chip, pin_in_bank = gpio - bank->gpio_offset; ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank); - spin_lock_irqsave(&a7gc->lock, flags); + raw_spin_lock_irqsave(&a7gc->lock, flags); ctrl = readl(ctrl_reg); if (value) @@ -5987,7 +5987,7 @@ static void atlas7_gpio_set_value(struct gpio_chip *chip, ctrl &= ~ATLAS7_GPIO_CTL_DATAOUT_MASK; writel(ctrl, ctrl_reg); - spin_unlock_irqrestore(&a7gc->lock, flags); + raw_spin_unlock_irqrestore(&a7gc->lock, flags); } static const struct of_device_id atlas7_gpio_ids[] = { @@ -6036,7 +6036,7 @@ static int atlas7_gpio_probe(struct platform_device *pdev) } a7gc->nbank = nbank; - spin_lock_init(&a7gc->lock); + raw_spin_lock_init(&a7gc->lock); /* Setup GPIO Chip */ chip = &a7gc->chip;