From patchwork Mon Jan 30 18:32:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Breathitt Gray X-Patchwork-Id: 721669 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vBygr0mc3z9t1d for ; Tue, 31 Jan 2017 05:33:12 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="pfG5i6ar"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752959AbdA3SdJ (ORCPT ); Mon, 30 Jan 2017 13:33:09 -0500 Received: from mail-yb0-f194.google.com ([209.85.213.194]:35198 "EHLO mail-yb0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753918AbdA3SdI (ORCPT ); Mon, 30 Jan 2017 13:33:08 -0500 Received: by mail-yb0-f194.google.com with SMTP id j82so21183133ybg.2; Mon, 30 Jan 2017 10:33:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CjbaWq89XUeuHWP/mSeOf/ABpCzd1xLZKV7ZkWnHtlk=; b=pfG5i6arIOyCuMbEZkC7ucensDUbazRXUepapTUX+lKcjP8Dy0c+Vyq8eXWfcKOnQG Vb0a2UzOjWLNfmmb1sFrv7HktocEQ4pBe2E1dJnd5+GLY0ZVcAaIlamWzZx8F1Utdpvl Aewr+LAEv6m8yIHMvZlCce4WJHBM6rPYnKDj/VLyIbZZMNaA7NE32XAVjk6V3LISpoNA vaQHkdIisXq3YYYpUaZv4mBTXckmEHsDDjegt4odzVT4w1wcPFEso0S//1cDwLoOhFpD wAeS4/Smc9H1SCtSHuQi2GDHn8TVtXvYNB2KMUbCC4vpPwFW/O94Xwi/lF5TvrZJybnj ZH+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CjbaWq89XUeuHWP/mSeOf/ABpCzd1xLZKV7ZkWnHtlk=; b=bwZQKVf+8A6joQ+ytmyU0Q8FCHijIhrjnY0Tc3E2CTTMncV8tOtBV0o5oZ1CJy0Qgw 118W/mk7+Aqh6jXaOZF7KfptDmFEi/iLpSPLeVHAI98cgOlta9JZ9y5c+RDIKRUqLLSJ FN0nrDQII3dhOd/Dz8CyLPVqb3e3OewPlRglUHQCsM+kRbfxoMjVQ+Py9pgLVwF0JQ0I mKnvNbWVI9FuFexl+69nMwRK3HwgX/2bbbjCqiS0g8BhwN2PQnrNj7KmZypzIcZH1Rwt n0VMEQPKtFFDZqEVzCbGOunRPZdOSQM9g5QVW44V63bzrl5D6/MsqQ7aPKEWRLdyd6rA sbvA== X-Gm-Message-State: AIkVDXKiyZtn+Kb7GcNYWxrJbuw4X5B/csdLUbiKvueWGkR/SfA/bXbbBdQLNXVsJom1RA== X-Received: by 10.13.247.71 with SMTP id h68mr17574709ywf.136.1485801187325; Mon, 30 Jan 2017 10:33:07 -0800 (PST) Received: from localhost (50-88-177-90.res.bhn.net. [50.88.177.90]) by smtp.gmail.com with ESMTPSA id z37sm7643551ywj.39.2017.01.30.10.33.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 30 Jan 2017 10:33:06 -0800 (PST) From: William Breathitt Gray To: linus.walleij@linaro.org, gnurou@gmail.com Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, William Breathitt Gray Subject: [PATCH v2 1/5] gpio: 104-dio-48e: Add support for GPIO names Date: Mon, 30 Jan 2017 13:32:58 -0500 Message-Id: X-Mailer: git-send-email 2.11.0 In-Reply-To: References: Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch sets the gpio_chip names option with an array of GPIO line names that match the manual documentation for the ACCES 104-DIO-48E. This should make it easier for users to identify which GPIO line corresponds to a respective GPIO pin on the device. Signed-off-by: William Breathitt Gray --- drivers/gpio/gpio-104-dio-48e.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-104-dio-48e.c b/drivers/gpio/gpio-104-dio-48e.c index 221243f17d4e..84e529b4f5d8 100644 --- a/drivers/gpio/gpio-104-dio-48e.c +++ b/drivers/gpio/gpio-104-dio-48e.c @@ -338,6 +338,26 @@ static irqreturn_t dio48e_irq_handler(int irq, void *dev_id) return IRQ_HANDLED; } +#define DIO48E_NGPIO 48 +static const char *dio48e_names[DIO48E_NGPIO] = { + "PPI Group 0 Port A 0", "PPI Group 0 Port A 1", "PPI Group 0 Port A 2", + "PPI Group 0 Port A 3", "PPI Group 0 Port A 4", "PPI Group 0 Port A 5", + "PPI Group 0 Port A 6", "PPI Group 0 Port A 7", "PPI Group 0 Port B 0", + "PPI Group 0 Port B 1", "PPI Group 0 Port B 2", "PPI Group 0 Port B 3", + "PPI Group 0 Port B 4", "PPI Group 0 Port B 5", "PPI Group 0 Port B 6", + "PPI Group 0 Port B 7", "PPI Group 0 Port C 0", "PPI Group 0 Port C 1", + "PPI Group 0 Port C 2", "PPI Group 0 Port C 3", "PPI Group 0 Port C 4", + "PPI Group 0 Port C 5", "PPI Group 0 Port C 6", "PPI Group 0 Port C 7", + "PPI Group 1 Port A 0", "PPI Group 1 Port A 1", "PPI Group 1 Port A 2", + "PPI Group 1 Port A 3", "PPI Group 1 Port A 4", "PPI Group 1 Port A 5", + "PPI Group 1 Port A 6", "PPI Group 1 Port A 7", "PPI Group 1 Port B 0", + "PPI Group 1 Port B 1", "PPI Group 1 Port B 2", "PPI Group 1 Port B 3", + "PPI Group 1 Port B 4", "PPI Group 1 Port B 5", "PPI Group 1 Port B 6", + "PPI Group 1 Port B 7", "PPI Group 1 Port C 0", "PPI Group 1 Port C 1", + "PPI Group 1 Port C 2", "PPI Group 1 Port C 3", "PPI Group 1 Port C 4", + "PPI Group 1 Port C 5", "PPI Group 1 Port C 6", "PPI Group 1 Port C 7" +}; + static int dio48e_probe(struct device *dev, unsigned int id) { struct dio48e_gpio *dio48egpio; @@ -358,7 +378,8 @@ static int dio48e_probe(struct device *dev, unsigned int id) dio48egpio->chip.parent = dev; dio48egpio->chip.owner = THIS_MODULE; dio48egpio->chip.base = -1; - dio48egpio->chip.ngpio = 48; + dio48egpio->chip.ngpio = DIO48E_NGPIO; + dio48egpio->chip.names = dio48e_names; dio48egpio->chip.get_direction = dio48e_gpio_get_direction; dio48egpio->chip.direction_input = dio48e_gpio_direction_input; dio48egpio->chip.direction_output = dio48e_gpio_direction_output;