From patchwork Mon Feb 16 22:33:14 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 440404 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 66AE21401DA for ; Tue, 17 Feb 2015 09:33:21 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751586AbbBPWdU (ORCPT ); Mon, 16 Feb 2015 17:33:20 -0500 Received: from mail-la0-f41.google.com ([209.85.215.41]:44778 "EHLO mail-la0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751541AbbBPWdT (ORCPT ); Mon, 16 Feb 2015 17:33:19 -0500 Received: by lams18 with SMTP id s18so32500722lam.11 for ; Mon, 16 Feb 2015 14:33:17 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:organization :user-agent:mime-version:content-transfer-encoding:content-type; bh=gGUJxPhAmkIo+Zs17lLtyQMxlCnOPXYP06ujTuxFEms=; b=T7GseCEJ+nxfzv54svEu04jonE3eBJ9daSgtwuORFyekGTPfUMQuMQLNThPkFmGb4O KBjFO4WbzrQ1Qt/tXLpHm3mkuGLQsz/eqqWgqmjOBE0EVsyjIeMFyPhkT2fUrH0sP2F2 Qz6zJtEh7JPFCSIxGdN5eSphs2goWMPjvXgEREN1YPxE5i6pKAh1D056lL6QMLX9wDtq YMm6+1W737pRqb68CXgC5HvqSlmhEmxBpAXDY/Xxv/AwzhjZs38X6Ooo5kpKH7DKwS4S CkfUjVOdBezo/tvCiluGzP9jKLFw+tj6U9Q5/oSWDO2bRed7J+xcuD0VYYKp8oIy0GRc DXZg== X-Gm-Message-State: ALoCoQlh8gFcHSP0D/R/QIE/auUxsyWRX2Dtv3rP3wnotreXvnJn+k4RgooJ/l8QfCGABPZ4vyI2 X-Received: by 10.152.178.197 with SMTP id da5mr25358488lac.87.1424125997602; Mon, 16 Feb 2015 14:33:17 -0800 (PST) Received: from wasted.cogentembedded.com (ppp83-237-56-86.pppoe.mtu-net.ru. [83.237.56.86]) by mx.google.com with ESMTPSA id zz10sm3193118lbb.13.2015.02.16.14.33.15 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Feb 2015 14:33:16 -0800 (PST) From: Sergei Shtylyov To: linus.walleij@linaro.org, linux-sh@vger.kernel.org, laurent.pinchart@ideasonboard.com, linux-gpio@vger.kernel.org Cc: shinobu.uehara.xc@renesas.com Subject: [PATCH] sh-pfc: r8a7794: add MMCIF pin groups Date: Tue, 17 Feb 2015 01:33:14 +0300 Message-ID: <2352429.FfRv9a1MoB@wasted.cogentembedded.com> Organization: Cogent Embedded Inc. User-Agent: KMail/4.14.4 (Linux/3.18.5-101.fc20.x86_64; KDE/4.14.4; x86_64; ; ) MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Shinobu Uehara Add MMCIF pin groups to R8A7794 PFC driver. Signed-off-by: Shinobu Uehara [Sergei: rebased, renamed, added changelog.] Signed-off-by: Sergei Shtylyov Acked-by: Laurent Pinchart --- The patch is against the 'devel' branch of Linus W.'s 'linux-pinctrl.git' repo plus the R8A7794 PFC support patch posted last week. drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 46 +++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Index: linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7794.c =================================================================== --- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +++ linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7794.c @@ -1900,6 +1900,40 @@ static const unsigned int intc_irq9_pins static const unsigned int intc_irq9_mux[] = { IRQ9_MARK, }; +/* - MMCIF ------------------------------------------------------------------ */ +static const unsigned int mmc_data1_pins[] = { + /* D[0] */ + RCAR_GP_PIN(6, 18), +}; +static const unsigned int mmc_data1_mux[] = { + MMC_D0_MARK, +}; +static const unsigned int mmc_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), + RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), +}; +static const unsigned int mmc_data4_mux[] = { + MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, +}; +static const unsigned int mmc_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), + RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), + RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), + RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), +}; +static const unsigned int mmc_data8_mux[] = { + MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, + MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK, +}; +static const unsigned int mmc_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17), +}; +static const unsigned int mmc_ctrl_mux[] = { + MMC_CLK_MARK, MMC_CMD_MARK, +}; /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -2664,6 +2698,10 @@ static const struct sh_pfc_pin_group pin SH_PFC_PIN_GROUP(intc_irq7), SH_PFC_PIN_GROUP(intc_irq8), SH_PFC_PIN_GROUP(intc_irq9), + SH_PFC_PIN_GROUP(mmc_data1), + SH_PFC_PIN_GROUP(mmc_data4), + SH_PFC_PIN_GROUP(mmc_data8), + SH_PFC_PIN_GROUP(mmc_ctrl), SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -2850,6 +2888,13 @@ static const char * const intc_groups[] "intc_irq9", }; +static const char * const mmc_groups[] = { + "mmc_data1", + "mmc_data4", + "mmc_data8", + "mmc_ctrl", +}; + static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -3016,6 +3061,7 @@ static const struct sh_pfc_function pinm SH_PFC_FUNCTION(i2c3), SH_PFC_FUNCTION(i2c4), SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(mmc), SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2),