| Message ID | 20240115131605.395691-3-hector.palacios@digi.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2,1/2] gpio: vf610: add support to DT 'ngpios' property | expand |
Hi Hector, thanks for the patch. Am Montag, 15. Januar 2024, 14:16:05 CET schrieb Hector Palacios: > According to NXP HRM for i.MX93, the following GPIO pins are available: > - GPIO1: 16 pins (0..15) Mh, RM Rev4 (12/2023) says: > Bit[31:17] should be Reserved for GPIO1 So GPIO1 has the range 0..16 > - GPIO2: 30 pins (0..29) > - GPIO3: 32 pins (0..31) > - GPIO4: 30 pins (0..29) RM Rev4 (12/2023) says: > Bit[31:28] should be Reserved for GPIO4 So GPIO4 would be the range 0..27 Where did you get your numbers from? Best regards, Alexander > > Signed-off-by: Hector Palacios <hector.palacios@digi.com> > --- > arch/arm64/boot/dts/freescale/imx93.dtsi | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi > b/arch/arm64/boot/dts/freescale/imx93.dtsi index 34c0540276d1..7eb2cab7c749 > 100644 > --- a/arch/arm64/boot/dts/freescale/imx93.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi > @@ -970,6 +970,7 @@ gpio2: gpio@43810000 { > <&clk IMX93_CLK_GPIO2_GATE>; > clock-names = "gpio", "port"; > gpio-ranges = <&iomuxc 0 4 30>; > + ngpios = <30>; > }; > > gpio3: gpio@43820000 { > @@ -986,6 +987,7 @@ gpio3: gpio@43820000 { > clock-names = "gpio", "port"; > gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>, > <&iomuxc 26 34 2>, <&iomuxc 28 0 4>; > + ngpios = <32>; > }; > > gpio4: gpio@43830000 { > @@ -1001,6 +1003,7 @@ gpio4: gpio@43830000 { > <&clk IMX93_CLK_GPIO4_GATE>; > clock-names = "gpio", "port"; > gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>; > + ngpios = <30>; > }; > > gpio1: gpio@47400000 { > @@ -1016,6 +1019,7 @@ gpio1: gpio@47400000 { > <&clk IMX93_CLK_GPIO1_GATE>; > clock-names = "gpio", "port"; > gpio-ranges = <&iomuxc 0 92 16>; > + ngpios = <16>; > }; > > ocotp: efuse@47510000 {
Hi Alexander, On 1/15/24 14:30, Alexander Stein wrote: > Hi Hector, > > thanks for the patch. > > Am Montag, 15. Januar 2024, 14:16:05 CET schrieb Hector Palacios: >> According to NXP HRM for i.MX93, the following GPIO pins are available: >> - GPIO1: 16 pins (0..15) > > Mh, RM Rev4 (12/2023) says: >> Bit[31:17] should be Reserved for GPIO1 > > So GPIO1 has the range 0..16 > >> - GPIO2: 30 pins (0..29) >> - GPIO3: 32 pins (0..31) >> - GPIO4: 30 pins (0..29) > > RM Rev4 (12/2023) says: >> Bit[31:28] should be Reserved for GPIO4 > > So GPIO4 would be the range 0..27 > > Where did you get your numbers from? I also saw what you point out about the HRM but when cross-checking with the IOMUXC topic (Chapter 27) to verify what pads can work as GPIO for each of the ports, I found you can configure pads for - GPIO1_IO00..GPIO1_IO15 - GPIO2_IO00..GPIO2_IO29 - GPIO3_IO00..GPIO3_IO31 - GPIO4_IO00..GPIO4_IO29 which doesn't exactly match the note about the reserved bits. I consider the IOMUXC topic more reliable but it would definitely be better if someone from NXP could clarify. Regards
> -----Original Message----- > From: Hector Palacios <hector.palacios@digi.com> > Sent: 2024年1月15日 23:42 > To: Alexander Stein <alexander.stein@ew.tq-group.com>; > linus.walleij@linaro.org; brgl@bgdev.pl; robh+dt@kernel.org > Cc: stefan@agner.ch; linux-gpio@vger.kernel.org; devicetree@vger.kernel.org; > Peng Fan <peng.fan@nxp.com>; Bough Chen <haibo.chen@nxp.com> > Subject: Re: [PATCH v2 2/2] arm64: dts: imx93: specify available 'ngpios' per > GPIO port > > Hi Alexander, > > On 1/15/24 14:30, Alexander Stein wrote: > > Hi Hector, > > > > thanks for the patch. > > > > Am Montag, 15. Januar 2024, 14:16:05 CET schrieb Hector Palacios: > >> According to NXP HRM for i.MX93, the following GPIO pins are available: > >> - GPIO1: 16 pins (0..15) > > > > Mh, RM Rev4 (12/2023) says: > >> Bit[31:17] should be Reserved for GPIO1 > > > > So GPIO1 has the range 0..16 > > > >> - GPIO2: 30 pins (0..29) > >> - GPIO3: 32 pins (0..31) > >> - GPIO4: 30 pins (0..29) > > > > RM Rev4 (12/2023) says: > >> Bit[31:28] should be Reserved for GPIO4 > > > > So GPIO4 would be the range 0..27 > > > > Where did you get your numbers from? > > I also saw what you point out about the HRM but when cross-checking with the > IOMUXC topic (Chapter 27) to verify what pads can work as GPIO for each of the > ports, I found you can configure pads for > - GPIO1_IO00..GPIO1_IO15 > - GPIO2_IO00..GPIO2_IO29 > - GPIO3_IO00..GPIO3_IO31 > - GPIO4_IO00..GPIO4_IO29 > > which doesn't exactly match the note about the reserved bits. > I consider the IOMUXC topic more reliable but it would definitely be better if > someone from NXP could clarify. Hi All, I just confirm with IP team, they use the IOMUX to implement RTL code. So IOMUX is reliable. The following are correct. - GPIO1_IO00..GPIO1_IO15 - GPIO2_IO00..GPIO2_IO29 - GPIO3_IO00..GPIO3_IO31 - GPIO4_IO00..GPIO4_IO29 I will ask the Doc team to update the reserved bits to align with the IOMUX. Best Regards Haibo Chen > > Regards > -- > Héctor Palacios > > > > >> > >> Signed-off-by: Hector Palacios <hector.palacios@digi.com> > >> --- > >> arch/arm64/boot/dts/freescale/imx93.dtsi | 4 ++++ > >> 1 file changed, 4 insertions(+) > >> > >> diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi > >> b/arch/arm64/boot/dts/freescale/imx93.dtsi index > >> 34c0540276d1..7eb2cab7c749 > >> 100644 > >> --- a/arch/arm64/boot/dts/freescale/imx93.dtsi > >> +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi > >> @@ -970,6 +970,7 @@ gpio2: gpio@43810000 { > >> <&clk IMX93_CLK_GPIO2_GATE>; > >> clock-names = "gpio", "port"; > >> gpio-ranges = <&iomuxc 0 4 30>; > >> + ngpios = <30>; > >> }; > >> > >> gpio3: gpio@43820000 { @@ -986,6 +987,7 @@ gpio3: > >> gpio@43820000 { > >> clock-names = "gpio", "port"; > >> gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 > 66 > > 18>, > >> <&iomuxc 26 34 2>, > <&iomuxc 28 0 > > 4>; > >> + ngpios = <32>; > >> }; > >> > >> gpio4: gpio@43830000 { @@ -1001,6 +1003,7 @@ > gpio4: > >> gpio@43830000 { > >> <&clk IMX93_CLK_GPIO4_GATE>; > >> clock-names = "gpio", "port"; > >> gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 > >> 36 > > 2>; > >> + ngpios = <30>; > >> }; > >> > >> gpio1: gpio@47400000 { @@ -1016,6 +1019,7 @@ > gpio1: > >> gpio@47400000 { > >> <&clk IMX93_CLK_GPIO1_GATE>; > >> clock-names = "gpio", "port"; > >> gpio-ranges = <&iomuxc 0 92 16>; > >> + ngpios = <16>; > >> }; > >> > >> ocotp: efuse@47510000 { > >
diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 34c0540276d1..7eb2cab7c749 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -970,6 +970,7 @@ gpio2: gpio@43810000 { <&clk IMX93_CLK_GPIO2_GATE>; clock-names = "gpio", "port"; gpio-ranges = <&iomuxc 0 4 30>; + ngpios = <30>; }; gpio3: gpio@43820000 { @@ -986,6 +987,7 @@ gpio3: gpio@43820000 { clock-names = "gpio", "port"; gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>, <&iomuxc 26 34 2>, <&iomuxc 28 0 4>; + ngpios = <32>; }; gpio4: gpio@43830000 { @@ -1001,6 +1003,7 @@ gpio4: gpio@43830000 { <&clk IMX93_CLK_GPIO4_GATE>; clock-names = "gpio", "port"; gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>; + ngpios = <30>; }; gpio1: gpio@47400000 { @@ -1016,6 +1019,7 @@ gpio1: gpio@47400000 { <&clk IMX93_CLK_GPIO1_GATE>; clock-names = "gpio", "port"; gpio-ranges = <&iomuxc 0 92 16>; + ngpios = <16>; }; ocotp: efuse@47510000 {
According to NXP HRM for i.MX93, the following GPIO pins are available: - GPIO1: 16 pins (0..15) - GPIO2: 30 pins (0..29) - GPIO3: 32 pins (0..31) - GPIO4: 30 pins (0..29) Signed-off-by: Hector Palacios <hector.palacios@digi.com> --- arch/arm64/boot/dts/freescale/imx93.dtsi | 4 ++++ 1 file changed, 4 insertions(+)