diff mbox series

[v3,4/4] arm64: tegra: Separate AON pinmux from main pinmux on Tegra194

Message ID 20221104142345.1562750-5-thierry.reding@gmail.com
State New
Headers show
Series pinctrl: tegra: Separate Tegra194 instances | expand

Commit Message

Thierry Reding Nov. 4, 2022, 2:23 p.m. UTC 
From: Thierry Reding <treding@nvidia.com>

The registers for the AON pinmux reside in a partition different from
the registers for the main pinmux. Instead of treating them as one and
the same device, split them up so that they are each their own devices.
Also add gpio-ranges properties to the corresponding GPIO controllers
such that the pinmux and GPIO controllers can be paired up properly.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra194.dtsi | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

Comments

Linus Walleij Nov. 8, 2022, 2:11 p.m. UTC | #1 
On Fri, Nov 4, 2022 at 3:23 PM Thierry Reding <thierry.reding@gmail.com> wrote:

> From: Thierry Reding <treding@nvidia.com>
>
> The registers for the AON pinmux reside in a partition different from
> the registers for the main pinmux. Instead of treating them as one and
> the same device, split them up so that they are each their own devices.
> Also add gpio-ranges properties to the corresponding GPIO controllers
> such that the pinmux and GPIO controllers can be paired up properly.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>

Is this one of those few cases where this patch should also be
applied to the pin control tree to keep things coherent for e.g.
git bisect?

Normally I would ask for this to be queued in the SoC tree separately.

Yours,
Linus Walleij
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 28740c014f1d..6829ee8b50ee 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -86,6 +86,7 @@  gpio: gpio@2200000 {
 			interrupt-controller;
 			#gpio-cells = <2>;
 			gpio-controller;
+			gpio-ranges = <&pinmux 0 0 169>;
 		};
 
 		cbb-noc@2300000 {
@@ -626,9 +627,7 @@  tegra_asrc: asrc@2910000 {
 
 		pinmux: pinmux@2430000 {
 			compatible = "nvidia,tegra194-pinmux";
-			reg = <0x2430000 0x17000>,
-			      <0xc300000 0x4000>;
-
+			reg = <0x2430000 0x17000>;
 			status = "okay";
 
 			pex_rst_c5_out_state: pex_rst_c5_out {
@@ -1660,6 +1659,14 @@  gpio_aon: gpio@c2f0000 {
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
+			gpio-range = <&pinmux_aon 0 0 30>;
+		};
+
+		pinmux_aon: pinmux@c300000 {
+			compatible = "nvidia,tegra194-pinmux-aon";
+			reg = <0xc300000 0x4000>;
+
+			status = "okay";
 		};
 
 		pwm4: pwm@c340000 {