| Message ID | 20220413192918.3777234-1-horatiu.vultur@microchip.com |
|---|---|
| State | New |
| Headers | show |
| Series | pinctrl: ocelot: Fix for lan966x | expand |
> For lan966x, the GPIO 35 has the wrong function for alternate mode 2. > The mode is not none but is PTP sync. > > Fixes: 531d6ab36571c2 ("pinctrl: ocelot: Extend support for lan966x") > Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> > --- > drivers/pinctrl/pinctrl-ocelot.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c > index 51261f1231cc..40f76e4144e4 100644 > --- a/drivers/pinctrl/pinctrl-ocelot.c > +++ b/drivers/pinctrl/pinctrl-ocelot.c > @@ -130,6 +130,7 @@ enum { > FUNC_PTP1, > FUNC_PTP2, > FUNC_PTP3, > + FUNC_PTPSYNC_0, > FUNC_PTPSYNC_1, > FUNC_PTPSYNC_2, > FUNC_PTPSYNC_3, > @@ -253,6 +254,7 @@ static const char *const ocelot_function_names[] = { > [FUNC_PTP1] = "ptp1", > [FUNC_PTP2] = "ptp2", > [FUNC_PTP3] = "ptp3", > + [FUNC_PTPSYNC_0] = "ptpsync_0", > [FUNC_PTPSYNC_1] = "ptpsync_1", > [FUNC_PTPSYNC_2] = "ptpsync_2", > [FUNC_PTPSYNC_3] = "ptpsync_3", > @@ -984,7 +986,7 @@ LAN966X_P(31, GPIO, FC3_c, CAN1, NONE, > OB_TRG, RECO_b, NON > LAN966X_P(32, GPIO, FC3_c, NONE, SGPIO_a, NONE, MIIM_Sa, > NONE, R); > LAN966X_P(33, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, > MIIM_b, R); > LAN966X_P(34, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, > MIIM_b, R); > -LAN966X_P(35, GPIO, FC1_b, NONE, SGPIO_a, CAN0_b, NONE, > NONE, R); > +LAN966X_P(35, GPIO, FC1_b, PTPSYNC_0, SGPIO_a, CAN0_b, NONE, > NONE, R); > LAN966X_P(36, GPIO, NONE, PTPSYNC_1, NONE, CAN0_b, NONE, > NONE, R); > LAN966X_P(37, GPIO, FC_SHRD0, PTPSYNC_2, TWI_SLC_GATE_AD, NONE, > NONE, NONE, R); > LAN966X_P(38, GPIO, NONE, PTPSYNC_3, NONE, NONE, NONE, > NONE, R); > -- > 2.33.0 Thanks, Kavya
On Wed, Apr 13, 2022 at 9:26 PM Horatiu Vultur <horatiu.vultur@microchip.com> wrote: > For lan966x, the GPIO 35 has the wrong function for alternate mode 2. > The mode is not none but is PTP sync. > > Fixes: 531d6ab36571c2 ("pinctrl: ocelot: Extend support for lan966x") > Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Patch applied for fixes. Yours, Linus Walleij
diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index 51261f1231cc..40f76e4144e4 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -130,6 +130,7 @@ enum { FUNC_PTP1, FUNC_PTP2, FUNC_PTP3, + FUNC_PTPSYNC_0, FUNC_PTPSYNC_1, FUNC_PTPSYNC_2, FUNC_PTPSYNC_3, @@ -253,6 +254,7 @@ static const char *const ocelot_function_names[] = { [FUNC_PTP1] = "ptp1", [FUNC_PTP2] = "ptp2", [FUNC_PTP3] = "ptp3", + [FUNC_PTPSYNC_0] = "ptpsync_0", [FUNC_PTPSYNC_1] = "ptpsync_1", [FUNC_PTPSYNC_2] = "ptpsync_2", [FUNC_PTPSYNC_3] = "ptpsync_3", @@ -984,7 +986,7 @@ LAN966X_P(31, GPIO, FC3_c, CAN1, NONE, OB_TRG, RECO_b, NON LAN966X_P(32, GPIO, FC3_c, NONE, SGPIO_a, NONE, MIIM_Sa, NONE, R); LAN966X_P(33, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R); LAN966X_P(34, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R); -LAN966X_P(35, GPIO, FC1_b, NONE, SGPIO_a, CAN0_b, NONE, NONE, R); +LAN966X_P(35, GPIO, FC1_b, PTPSYNC_0, SGPIO_a, CAN0_b, NONE, NONE, R); LAN966X_P(36, GPIO, NONE, PTPSYNC_1, NONE, CAN0_b, NONE, NONE, R); LAN966X_P(37, GPIO, FC_SHRD0, PTPSYNC_2, TWI_SLC_GATE_AD, NONE, NONE, NONE, R); LAN966X_P(38, GPIO, NONE, PTPSYNC_3, NONE, NONE, NONE, NONE, R);
For lan966x, the GPIO 35 has the wrong function for alternate mode 2. The mode is not none but is PTP sync. Fixes: 531d6ab36571c2 ("pinctrl: ocelot: Extend support for lan966x") Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> --- drivers/pinctrl/pinctrl-ocelot.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)