diff mbox series

[v2,12/13] ARM: dts: imx: add i.MXRT1050-EVK support

Message ID 20211102225701.98944-13-Mr.Bossman075@gmail.com
State New
Headers show
Series Add initial support for the i.MXRTxxxx SoC family starting from i.IMXRT1050 SoC. | expand

Commit Message

Jesse T Nov. 2, 2021, 10:57 p.m. UTC 
From: Giulio Benetti <giulio.benetti@benettiengineering.com>

The NXP i.MXRT1050 Evaluation Kit (EVK) provides a platform for rapid
evaluation of the i.MXRT, which features NXP's implementation of the Arm
Cortex-M7 core.

The EVK provides 32 MB SDRAM, 64 MB Quad SPI flash, Micro SD card socket,
USB 2.0 OTG.

This patch aims to support the preliminary booting up features
as follows:
GPIO
LPUART
SD/MMC

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
[Jesse: Add clock-parents, edma, usdhc, anatop, remove old pinctl]
---
V1->V2:
* dtsi: Add clock parent definitions
* dtsi: Change hex values to lowercase
* dtsi: Move anatop definition from driver
* dts: Remove unused pin controll (semc)
* dts: Use moved pin controll header
* Move aliases from dtsi to dts
* Change commit description
* Change licence to "GPL-2.0+ OR MIT"
---
 arch/arm/boot/dts/Makefile          |   2 +
 arch/arm/boot/dts/imxrt1050-evk.dts |  89 +++++++++++++
 arch/arm/boot/dts/imxrt1050.dtsi    | 187 ++++++++++++++++++++++++++++
 3 files changed, 278 insertions(+)
 create mode 100644 arch/arm/boot/dts/imxrt1050-evk.dts
 create mode 100644 arch/arm/boot/dts/imxrt1050.dtsi

Comments

Fabio Estevam Nov. 2, 2021, 11:42 p.m. UTC | #1 
On Tue, Nov 2, 2021 at 7:57 PM Jesse Taube <mr.bossman075@gmail.com> wrote:

> +/ {
> +       model = "NXP IMXRT1050-evk board";
> +       compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
> +
> +       chosen {
> +               bootargs = "root=/dev/ram";

No need to pass bootargs here.

> +               stdout-path = &lpuart1;
> +       };
> +
> +       aliases {
> +               gpio0 = &gpio1;
> +               gpio1 = &gpio2;
> +               gpio2 = &gpio3;
> +               gpio3 = &gpio4;
> +               gpio4 = &gpio5;
> +               mmc0 = &usdhc1;
> +               serial0 = &lpuart1;
> +       };
> +
> +       memory@0 {

memory@80000000

Building with W=1 should give a dtc warning due to the unit address
and reg mismatch.

> +               device_type = "memory";
> +               reg = <0x80000000 0x2000000>;
> +       };
> +

Unneeded blank line.
> +
> +&iomuxc {
> +       pinctrl-names = "default";
> +
> +       imxrt1050-evk {

No need for this imxrt1050-evk container.

> +               pinctrl_lpuart1: lpuart1grp {
> +                       fsl,pins = <
> +                               MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD
> +                                       0xf1

Put it on a single line. It helps readability. Same applies globally.
> +&usdhc1 {
> +       pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
> +       pinctrl-0 = <&pinctrl_usdhc0>;
> +       pinctrl-1 = <&pinctrl_usdhc0>;
> +       pinctrl-2 = <&pinctrl_usdhc0>;
> +       pinctrl-3 = <&pinctrl_usdhc0>;
> +       status = "okay";
> +
> +       cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;

Make 'status' to be the last property. Remove the blank line.

> +               edma1: dma-controller@400e8000 {
> +                       #dma-cells = <2>;
> +                       compatible = "fsl,imx7ulp-edma";
> +                       reg = <0x400e8000 0x4000>,
> +                               <0x400ec000 0x4000>;
> +                       dma-channels = <32>;
> +                       interrupts = <0>,
> +                               <1>,
> +                               <2>,
> +                               <3>,
> +                               <4>,
> +                               <5>,
> +                               <6>,
> +                               <7>,
> +                               <8>,
> +                               <9>,
> +                               <10>,
> +                               <11>,
> +                               <12>,
> +                               <13>,
> +                               <14>,
> +                               <15>,
> +                               <16>;

Please group more elements into the same line.

Putting one entry per line makes it extremely long.

> +               gpio5: gpio@400c0000 {
> +                       compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
> +                       reg = <0x400c0000 0x4000>;
> +                       interrupts = <88>,
> +                               <89>;

Put the interrupts into a single line.
Jesse T Nov. 2, 2021, 11:54 p.m. UTC | #2 
On 11/2/21 19:42, Fabio Estevam wrote:
> On Tue, Nov 2, 2021 at 7:57 PM Jesse Taube <mr.bossman075@gmail.com> wrote:
> 
>> +/ {
>> +       model = "NXP IMXRT1050-evk board";
>> +       compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
>> +
>> +       chosen {
>> +               bootargs = "root=/dev/ram";
> 
> No need to pass bootargs here.
> 
>> +               stdout-path = &lpuart1;
>> +       };
>> +
>> +       aliases {
>> +               gpio0 = &gpio1;
>> +               gpio1 = &gpio2;
>> +               gpio2 = &gpio3;
>> +               gpio3 = &gpio4;
>> +               gpio4 = &gpio5;
>> +               mmc0 = &usdhc1;
>> +               serial0 = &lpuart1;
>> +       };
>> +
>> +       memory@0 {
> 
> memory@80000000
> 
> Building with W=1 should give a dtc warning due to the unit address
> and reg mismatch.
Oh that makes sense.
I guess I'm going to have to figure out how to get warnings to work as I 
couldn't last time I tried.
> 
>> +               device_type = "memory";
>> +               reg = <0x80000000 0x2000000>;
>> +       };
>> +
> 
> Unneeded blank line.
>> +
>> +&iomuxc {
>> +       pinctrl-names = "default";
>> +
>> +       imxrt1050-evk {
> 
> No need for this imxrt1050-evk container.
I was wondering if that was needed, u-boot has it, good to know.
> 
>> +               pinctrl_lpuart1: lpuart1grp {
>> +                       fsl,pins = <
>> +                               MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD
>> +                                       0xf1
> 
> Put it on a single line. It helps readability. Same applies globally.
>> +&usdhc1 {
>> +       pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
>> +       pinctrl-0 = <&pinctrl_usdhc0>;
>> +       pinctrl-1 = <&pinctrl_usdhc0>;
>> +       pinctrl-2 = <&pinctrl_usdhc0>;
>> +       pinctrl-3 = <&pinctrl_usdhc0>;
>> +       status = "okay";
>> +
>> +       cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
> 
> Make 'status' to be the last property. Remove the blank line.
> 
>> +               edma1: dma-controller@400e8000 {
>> +                       #dma-cells = <2>;
>> +                       compatible = "fsl,imx7ulp-edma";
>> +                       reg = <0x400e8000 0x4000>,
>> +                               <0x400ec000 0x4000>;
>> +                       dma-channels = <32>;
>> +                       interrupts = <0>,
>> +                               <1>,
>> +                               <2>,
>> +                               <3>,
>> +                               <4>,
>> +                               <5>,
>> +                               <6>,
>> +                               <7>,
>> +                               <8>,
>> +                               <9>,
>> +                               <10>,
>> +                               <11>,
>> +                               <12>,
>> +                               <13>,
>> +                               <14>,
>> +                               <15>,
>> +                               <16>;
> 
> Please group more elements into the same line.
> 
> Putting one entry per line makes it extremely long.
> 
>> +               gpio5: gpio@400c0000 {
>> +                       compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
>> +                       reg = <0x400c0000 0x4000>;
>> +                       interrupts = <88>,
>> +                               <89>;
> 
> Put the interrupts into a single line.
> 
Ah all these make sense, will fix, sry about that.
Jesse T Nov. 3, 2021, 2:19 a.m. UTC | #3 
On 11/2/21 19:54, Jesse Taube wrote:
> 
> 
> On 11/2/21 19:42, Fabio Estevam wrote:
>> On Tue, Nov 2, 2021 at 7:57 PM Jesse Taube <mr.bossman075@gmail.com> wrote:
>>
>>> +/ {
>>> +       model = "NXP IMXRT1050-evk board";
>>> +       compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
>>> +
>>> +       chosen {
>>> +               bootargs = "root=/dev/ram";
>>
>> No need to pass bootargs here.
>>
>>> +               stdout-path = &lpuart1;
>>> +       };
>>> +
>>> +       aliases {
>>> +               gpio0 = &gpio1;
>>> +               gpio1 = &gpio2;
>>> +               gpio2 = &gpio3;
>>> +               gpio3 = &gpio4;
>>> +               gpio4 = &gpio5;
>>> +               mmc0 = &usdhc1;
>>> +               serial0 = &lpuart1;
>>> +       };
>>> +
>>> +       memory@0 {
>>
>> memory@80000000
>>
>> Building with W=1 should give a dtc warning due to the unit address
>> and reg mismatch.
> Oh that makes sense.
> I guess I'm going to have to figure out how to get warnings to work as I
> couldn't last time I tried.
Oh i got it to work I did something dumb...
I didn't give a warning for this i still changed it of course.
>>
>>> +               device_type = "memory";
>>> +               reg = <0x80000000 0x2000000>;
>>> +       };
>>> +
>>
>> Unneeded blank line.
>>> +
>>> +&iomuxc {
>>> +       pinctrl-names = "default";
>>> +
>>> +       imxrt1050-evk {
>>
>> No need for this imxrt1050-evk container.
> I was wondering if that was needed, u-boot has it, good to know.
>>
>>> +               pinctrl_lpuart1: lpuart1grp {
>>> +                       fsl,pins = <
>>> +                               MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD
>>> +                                       0xf1
>>
>> Put it on a single line. It helps readability. Same applies globally.
>>> +&usdhc1 {
>>> +       pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
>>> +       pinctrl-0 = <&pinctrl_usdhc0>;
>>> +       pinctrl-1 = <&pinctrl_usdhc0>;
>>> +       pinctrl-2 = <&pinctrl_usdhc0>;
>>> +       pinctrl-3 = <&pinctrl_usdhc0>;
>>> +       status = "okay";
>>> +
>>> +       cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
>>
>> Make 'status' to be the last property. Remove the blank line.
>>
>>> +               edma1: dma-controller@400e8000 {
>>> +                       #dma-cells = <2>;
>>> +                       compatible = "fsl,imx7ulp-edma";
>>> +                       reg = <0x400e8000 0x4000>,
>>> +                               <0x400ec000 0x4000>;
>>> +                       dma-channels = <32>;
>>> +                       interrupts = <0>,
>>> +                               <1>,
>>> +                               <2>,
>>> +                               <3>,
>>> +                               <4>,
>>> +                               <5>,
>>> +                               <6>,
>>> +                               <7>,
>>> +                               <8>,
>>> +                               <9>,
>>> +                               <10>,
>>> +                               <11>,
>>> +                               <12>,
>>> +                               <13>,
>>> +                               <14>,
>>> +                               <15>,
>>> +                               <16>;
>>
>> Please group more elements into the same line.
>>
>> Putting one entry per line makes it extremely long.
>>
>>> +               gpio5: gpio@400c0000 {
>>> +                       compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
>>> +                       reg = <0x400c0000 0x4000>;
>>> +                       interrupts = <88>,
>>> +                               <89>;
>>
>> Put the interrupts into a single line.
>>
> Ah all these make sense, will fix, sry about that.
>
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7e0934180724..f32dd34550cb 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -708,6 +708,8 @@  dtb-$(CONFIG_SOC_IMX7D) += \
 dtb-$(CONFIG_SOC_IMX7ULP) += \
 	imx7ulp-com.dtb \
 	imx7ulp-evk.dtb
+dtb-$(CONFIG_SOC_IMXRT) += \
+	imxrt1050-evk.dtb
 dtb-$(CONFIG_SOC_LS1021A) += \
 	ls1021a-moxa-uc-8410a.dtb \
 	ls1021a-qds.dtb \
diff --git a/arch/arm/boot/dts/imxrt1050-evk.dts b/arch/arm/boot/dts/imxrt1050-evk.dts
new file mode 100644
index 000000000000..e414284a1544
--- /dev/null
+++ b/arch/arm/boot/dts/imxrt1050-evk.dts
@@ -0,0 +1,89 @@ 
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+/dts-v1/;
+#include "imxrt1050.dtsi"
+#include "imxrt1050-pinfunc.h"
+
+/ {
+	model = "NXP IMXRT1050-evk board";
+	compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
+
+	chosen {
+		bootargs = "root=/dev/ram";
+		stdout-path = &lpuart1;
+	};
+
+	aliases {
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		gpio3 = &gpio4;
+		gpio4 = &gpio5;
+		mmc0 = &usdhc1;
+		serial0 = &lpuart1;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x80000000 0x2000000>;
+	};
+
+};
+
+&lpuart1 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart1>;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+
+	imxrt1050-evk {
+		pinctrl_lpuart1: lpuart1grp {
+			fsl,pins = <
+				MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD
+					0xf1
+				MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD
+					0xf1
+			>;
+		};
+
+		pinctrl_usdhc0: usdhc0grp {
+			fsl,pins = <
+				MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B
+					0x1B000
+				MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT
+					0xB069
+				MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD
+					0x17061
+				MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK
+					0x17061
+				MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3
+					0x17061
+				MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2
+					0x17061
+				MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1
+					0x17061
+				MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0
+					0x17061
+			>;
+		};
+
+	};
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+	pinctrl-0 = <&pinctrl_usdhc0>;
+	pinctrl-1 = <&pinctrl_usdhc0>;
+	pinctrl-2 = <&pinctrl_usdhc0>;
+	pinctrl-3 = <&pinctrl_usdhc0>;
+	status = "okay";
+
+	cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
+};
diff --git a/arch/arm/boot/dts/imxrt1050.dtsi b/arch/arm/boot/dts/imxrt1050.dtsi
new file mode 100644
index 000000000000..cad5d0249fea
--- /dev/null
+++ b/arch/arm/boot/dts/imxrt1050.dtsi
@@ -0,0 +1,187 @@ 
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
+ */
+
+#include "armv7-m.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/imxrt1050-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	clocks {
+		osc: osc {
+			compatible = "fsl,imx-osc", "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <24000000>;
+		};
+	};
+
+	cpus {
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+
+		cpu@0 {
+			compatible = "arm,cortex-m7";
+			device_type = "cpu";
+			reg = <0x00>;
+		};
+	};
+
+	soc {
+
+		lpuart1: serial@40184000 {
+			compatible = "fsl,imxrt-lpuart","fsl,imx8mm-uart", "fsl,imx6q-uart";
+			reg = <0x40184000 0x4000>;
+			interrupts = <20>;
+			clocks = <&clks IMXRT1050_CLK_LPUART1>;
+			clock-names = "ipg";
+			status = "disabled";
+		};
+
+		iomuxc: iomuxc@401f8000 {
+			compatible = "fsl,imxrt1050-iomuxc";
+			reg = <0x401f8000 0x4000>;
+			fsl,mux_mask = <0x7>;
+		};
+
+		anatop: anatop@400d8000 {
+			compatible = "fsl,imxrt-anatop";
+			reg = <0x400d8000 0x4000>;
+		};
+
+		clks: ccm@400fc000 {
+			compatible = "fsl,imxrt1050-ccm";
+			reg = <0x400fc000 0x4000>;
+			interrupts = <95>,
+				     <96>;
+			clocks = <&osc>;
+			clock-names = "osc";
+			#clock-cells = <1>;
+			assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>,
+				<&clks IMXRT1050_CLK_PLL1_BYPASS>,
+				<&clks IMXRT1050_CLK_PLL2_BYPASS>,
+				<&clks IMXRT1050_CLK_PLL3_BYPASS>,
+				<&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>,
+				<&clks IMXRT1050_CLK_PLL2_PFD2_396M>;
+			assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>,
+				<&clks IMXRT1050_CLK_PLL1_ARM>,
+				<&clks IMXRT1050_CLK_PLL2_SYS>,
+				<&clks IMXRT1050_CLK_PLL3_USB_OTG>,
+				<&clks IMXRT1050_CLK_PLL3_USB_OTG>,
+				<&clks IMXRT1050_CLK_PLL2_SYS>;
+		};
+
+		edma1: dma-controller@400e8000 {
+			#dma-cells = <2>;
+			compatible = "fsl,imx7ulp-edma";
+			reg = <0x400e8000 0x4000>,
+				<0x400ec000 0x4000>;
+			dma-channels = <32>;
+			interrupts = <0>,
+				<1>,
+				<2>,
+				<3>,
+				<4>,
+				<5>,
+				<6>,
+				<7>,
+				<8>,
+				<9>,
+				<10>,
+				<11>,
+				<12>,
+				<13>,
+				<14>,
+				<15>,
+				<16>;
+			clock-names = "dma", "dmamux0";
+			clocks = <&clks IMXRT1050_CLK_DMA>,
+				 <&clks IMXRT1050_CLK_DMA_MUX>;
+		};
+
+		usdhc1: mmc@402c0000 {
+			compatible ="fsl,imxrt-usdhc";
+			reg = <0x402c0000 0x4000>;
+			interrupts = <110>;
+			clocks = <&clks IMXRT1050_CLK_IPG_PDOF>,
+				<&clks IMXRT1050_CLK_OSC>,
+				<&clks IMXRT1050_CLK_USDHC1>;
+			clock-names = "ipg", "ahb", "per";
+			bus-width = <4>;
+			fsl,wp-controller;
+			no-1-8-v;
+			max-frequency = <4000000>;
+			fsl,tuning-start-tap = <20>;
+			fsl,tuning-step= <2>;
+			status = "disabled";
+		};
+
+		gpio1: gpio@401b8000 {
+			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+			reg = <0x401b8000 0x4000>;
+			interrupts = <80>,
+				     <81>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio2: gpio@401bc000 {
+			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+			reg = <0x401bc000 0x4000>;
+			interrupts = <82>,
+				<83>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio3: gpio@401c0000 {
+			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+			reg = <0x401c0000 0x4000>;
+			interrupts = <84>,
+				<85>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio4: gpio@401c4000 {
+			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+			reg = <0x401c4000 0x4000>;
+			interrupts = <86>,
+					<87>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio5: gpio@400c0000 {
+			compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
+			reg = <0x400c0000 0x4000>;
+			interrupts = <88>,
+				<89>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpt: timer@401ec000 {
+			compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
+			reg = <0x401ec000 0x4000>;
+			interrupts = <100>;
+			clocks = <&clks IMXRT1050_CLK_OSC>;
+			clock-names = "per";
+		};
+	};
+};