| Message ID | 20210716162724.26047-2-lakshmi.sowjanya.d@intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add pinctrl support for Intel Keem Bay SoC | expand |
Hi Lakshmi, sorry for slow review. Since this is one of those "Intel but Arm" things I don't know how Andy feels about picking up the patch to his Intel pinctrl tree (I think we discussed it in the past) so I need to know how to handle this. It'd be great if Andy queues "all Intel stuff" but I don't want to force unfamiliar stuff on him either. Andy? Do you pick this (when finished) or should I? On Fri, Jul 16, 2021 at 6:27 PM <lakshmi.sowjanya.d@intel.com> wrote: > + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; Did we discuss this before? Are these hierarchical or does these IRQs map to more than one GPIO line? If they are hieararchical then the driver should just pick the lines in hierarchy from the parent with no data in the driver, but if one of these IRQ lines maps to more than one GPIO line they should be like this. Yours, Linus Walleij
On Fri, Jul 16, 2021 at 6:27 PM <lakshmi.sowjanya.d@intel.com> wrote: > From: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com> > > Add Device Tree bindings documentation for Intel Keem Bay > SoC's pin controller. > Add entry for INTEL Keem Bay pinctrl driver in MAINTAINERS file > > Acked-by: Mark Gross <mgross@linux.intel.com> > Co-developed-by: Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com> > Signed-off-by: Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com> > Co-developed-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com> > Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com> > Signed-off-by: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com> (...) > + interrupts: > + description: > + Specifies the interrupt lines to be used by the controller. > + maxItems: 8 Write here that each interrupt is shared by up to 4 GPIO lines. With that: Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Yours, Linus Walleij
Thank you Linus Walleij !! I'll include the same and post the next version with 'Reviewed-by: Linus Walleij <linus.walleij@linaro.org>' tag. Thanks and Regards, Lakshmi Sowjanya > -----Original Message----- > From: Linus Walleij <linus.walleij@linaro.org> > Sent: Friday, July 30, 2021 2:45 PM > To: D, Lakshmi Sowjanya <lakshmi.sowjanya.d@intel.com> > Cc: open list:GPIO SUBSYSTEM <linux-gpio@vger.kernel.org>; linux-kernel > <linux-kernel@vger.kernel.org>; Andy Shevchenko > <andriy.shevchenko@linux.intel.com>; Raja Subramanian, Lakshmi Bai > <lakshmi.bai.raja.subramanian@intel.com>; Saha, Tamal > <tamal.saha@intel.com> > Subject: Re: [PATCH v3 1/2] dt-bindings: pinctrl: Add bindings for Intel > Keembay pinctrl driver > > On Fri, Jul 16, 2021 at 6:27 PM <lakshmi.sowjanya.d@intel.com> wrote: > > > From: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com> > > > > Add Device Tree bindings documentation for Intel Keem Bay SoC's pin > > controller. > > Add entry for INTEL Keem Bay pinctrl driver in MAINTAINERS file > > > > Acked-by: Mark Gross <mgross@linux.intel.com> > > Co-developed-by: Vineetha G. Jaya Kumaran > > <vineetha.g.jaya.kumaran@intel.com> > > Signed-off-by: Vineetha G. Jaya Kumaran > > <vineetha.g.jaya.kumaran@intel.com> > > Co-developed-by: Vijayakannan Ayyathurai > > <vijayakannan.ayyathurai@intel.com> > > Signed-off-by: Vijayakannan Ayyathurai > > <vijayakannan.ayyathurai@intel.com> > > Signed-off-by: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com> > (...) > > + interrupts: > > + description: > > + Specifies the interrupt lines to be used by the controller. > > + maxItems: 8 > > Write here that each interrupt is shared by up to 4 GPIO lines. > > With that: > Reviewed-by: Linus Walleij <linus.walleij@linaro.org> > > Yours, > Linus Walleij
On Fri, Jul 30, 2021 at 11:05:43AM +0200, Linus Walleij wrote: > Since this is one of those "Intel but Arm" things I don't know how > Andy feels about picking up the patch to his Intel pinctrl tree > (I think we discussed it in the past) so I need to know how to handle > this. It'd be great if Andy queues "all Intel stuff" but I don't want > to force unfamiliar stuff on him either. > > Andy? Do you pick this (when finished) or should I? I think it's for you. Mika and I are about Intel pin controllers on x86.
On Fri, Jul 30, 2021 at 1:30 PM Andy Shevchenko <andriy.shevchenko@linux.intel.com> wrote: > On Fri, Jul 30, 2021 at 11:05:43AM +0200, Linus Walleij wrote: > > Since this is one of those "Intel but Arm" things I don't know how > > Andy feels about picking up the patch to his Intel pinctrl tree > > (I think we discussed it in the past) so I need to know how to handle > > this. It'd be great if Andy queues "all Intel stuff" but I don't want > > to force unfamiliar stuff on him either. > > > > Andy? Do you pick this (when finished) or should I? > > I think it's for you. Mika and I are about Intel pin controllers on x86. OK I'll deal with it, I do have some experience with some other funny Intel-Arm silicon like XScale IXP4xx etc. Yours, Linus Walleij
diff --git a/Documentation/devicetree/bindings/pinctrl/intel,pinctrl-keembay.yaml b/Documentation/devicetree/bindings/pinctrl/intel,pinctrl-keembay.yaml new file mode 100644 index 000000000000..6c6f45ac75a5 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/intel,pinctrl-keembay.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-keembay.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Keem Bay pin controller Device Tree Bindings + +maintainers: + - Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com> + +description: | + Intel Keem Bay SoC integrates a pin controller which enables control + of pin directions, input/output values and configuration + for a total of 80 pins. + +properties: + compatible: + const: intel,keembay-pinctrl + + reg: + maxItems: 2 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + ngpios: + description: The number of GPIOs exposed. + const: 80 + + interrupts: + description: + Specifies the interrupt lines to be used by the controller. + maxItems: 8 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +patternProperties: + '^gpio@[0-9a-f]*$': + type: object + + description: + Child nodes can be specified to contain pin configuration information, + which can then be utilized by pinctrl client devices. + The following properties are supported. + + properties: + pins: + description: | + The name(s) of the pins to be configured in the child node. + Supported pin names are "GPIO0" up to "GPIO79". + + bias-disable: true + + bias-pull-down: true + + bias-pull-up: true + + drive-strength: + description: IO pads drive strength in milli Ampere. + enum: [2, 4, 8, 12] + + bias-bus-hold: + type: boolean + + input-schmitt-enable: + type: boolean + + slew-rate: + description: GPIO slew rate control. + 0 - Fast(~100MHz) + 1 - Slow(~50MHz) + enum: [0, 1] + +additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - ngpios + - '#gpio-cells' + - interrupts + - interrupt-controller + - '#interrupt-cells' + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + // Example 1 + gpio@0 { + compatible = "intel,keembay-pinctrl"; + reg = <0x600b0000 0x88>, + <0x600b0190 0x1ac>; + gpio-controller; + ngpios = <0x50>; + #gpio-cells = <0x2>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + // Example 2 + gpio@1 { + compatible = "intel,keembay-pinctrl"; + reg = <0x600c0000 0x88>, + <0x600c0190 0x1ac>; + gpio-controller; + ngpios = <0x50>; + #gpio-cells = <0x2>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 6c8be735cc91..f2f3fda0bf60 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14636,6 +14636,11 @@ S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel.git F: drivers/pinctrl/intel/ +PIN CONTROLLER - KEEMBAY +M: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com> +S: Supported +F: drivers/pinctrl/pinctrl-keembay* + PIN CONTROLLER - MEDIATEK M: Sean Wang <sean.wang@kernel.org> L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)