From patchwork Tue Nov 24 04:37:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 1405247 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256 header.s=dkim.wdc.com header.b=hvLj8aIK; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CgB8y1PY8z9sSf for ; Tue, 24 Nov 2020 15:38:10 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729264AbgKXEiI (ORCPT ); Mon, 23 Nov 2020 23:38:08 -0500 Received: from esa6.hgst.iphmx.com ([216.71.154.45]:49807 "EHLO esa6.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728953AbgKXEiH (ORCPT ); Mon, 23 Nov 2020 23:38:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1606192687; x=1637728687; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JdBVBZY3ULTQ3qd6MFXdWgh6JhVeGPBTXCCSTFbMJb0=; b=hvLj8aIK/4wNRyKrCJaa0OqSY52EE75fzt3DDxnPs/rt4RnsS3zN+QXO 6SkY8efXC/UyJ2cDeG92nR9af0KCZ6t3m+cV3bUs4jLSivZK+IpIZ6W+5 lazmPXjFFpgZiMUO0+840qnIt3I8+7pVKhoCMZ+IDv4QaMwpSbyOF5uyJ kVmY5QoCKyS1HoE7b74suLFf44VUCp+DBACuYfDtYowJ36E3klsnh1ERr XGFYJWTO8LZxd3BMsIAcUwwws7nETDnWPoMJFE6Y8TLPNdPrZ6VNxYV63 w2+cJrT4hwQrOSxRoeF590Unp3aUDRWkIrsfTI+AYvfaWBL6vUSjN/Gc5 Q==; IronPort-SDR: p3aMnwQf3BVmNr0kVke4ZbW3ICWGn/0muKb4KYlNRLJhJVlKXjxflnjdReKQDwqfB11FeZmopK bcJdOTOdR3T3p996qKDFYUcDF7D3UESdZim/y8ykefm62QA5d3B1puNO077IvxsUg6G8JX81r8 V0wcPJTH30XHVYi6j0Ru3RPJOHW+EGjgF4WUKE/50bJ+VchYbLPuiNSVkpwOBK4j/K1OZ/6Fyc UocZkS5mSs65WbO7U/BIsp+mTvCe7uxGmVP/7908tNYynznbensEkeKNeHICu5PoAcwm2bgOzD ZM8= X-IronPort-AV: E=Sophos;i="5.78,365,1599494400"; d="scan'208";a="154498193" Received: from h199-255-45-14.hgst.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 24 Nov 2020 12:38:03 +0800 IronPort-SDR: r9Cqo7BsYa6DVdNeT7cZkq3Z3A2n9A7MBjVv2tk2Z2WXNaz95bSUKtay51SJZUMnCWT7RjK8Dr rJ7wGcmaxqtVSKde+ON4/wJ4K6sHUdSHk= Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Nov 2020 20:23:46 -0800 IronPort-SDR: hOu3SgLc24FehT7ZJ1s/82fRqJNbIDkNbNBiT8Q1Yac1lv9kbaUZToZkOlMQBhEQe0OIVme4Ng kKgXmGDMkaeA== WDCIronportException: Internal Received: from hdrdzf2.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.163]) by uls-op-cesaip01.wdc.com with ESMTP; 23 Nov 2020 20:38:00 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , devicetree@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH v2 15/21] riscv: Add SiPeed MAIX BiT board device tree Date: Tue, 24 Nov 2020 13:37:22 +0900 Message-Id: <20201124043728.199852-16-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201124043728.199852-1-damien.lemoal@wdc.com> References: <20201124043728.199852-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add a device tree for the SiPeed MAIX BiT and MAIX BiTm boards. This device tree enables LEDs, gpio, i2c and spi/mmc SD card devices. Signed-off-by: Damien Le Moal --- arch/riscv/boot/dts/canaan/k210_maix_bit.dts | 227 +++++++++++++++++++ 1 file changed, 227 insertions(+) create mode 100644 arch/riscv/boot/dts/canaan/k210_maix_bit.dts diff --git a/arch/riscv/boot/dts/canaan/k210_maix_bit.dts b/arch/riscv/boot/dts/canaan/k210_maix_bit.dts new file mode 100644 index 000000000000..a5a40f9cf812 --- /dev/null +++ b/arch/riscv/boot/dts/canaan/k210_maix_bit.dts @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-20 Sean Anderson + * Copyright (C) 2020 Western Digital Corporation or its affiliates. + */ + +/dts-v1/; + +#include "k210.dtsi" + +#include +#include + +/ { + model = "SiPeed MAIX BiT"; + compatible = "sipeed,maix-bitm", "sipeed,maix-bit", + "canaan,kendryte-k210"; + + chosen { + bootargs = "earlycon console=ttySIF0"; + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + green { + gpios = <&gpio1_0 4 GPIO_ACTIVE_LOW>; + }; + + red { + gpios = <&gpio1_0 5 GPIO_ACTIVE_LOW>; + }; + + blue { + gpios = <&gpio1_0 6 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + boot { + label = "BOOT"; + linux,code = ; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0 0>; + }; + + simple-audio-card,codec { + sound-dai = <&mic>; + }; + }; + + mic: mic { + #sound-dai-cells = <0>; + compatible = "memsensing,msm261s4030h0"; + status = "disabled"; + }; +}; + +&fpioa { + pinctrl-names = "default"; + pinctrl-0 = <&jtag_pinctrl>; + status = "okay"; + + jtag_pinctrl: jtag-pinmux { + pinmux = , + , + , + ; + }; + + uarths_pinctrl: uarths-pinmux { + pinmux = , + ; + }; + + gpio_pinctrl: gpio-pinmux { + pinmux = , + , + , + , + , + , + , + ; + }; + + gpiohs_pinctrl: gpiohs-pinmux { + pinmux = , + , + , + , + , + , + , + , + , + , + ; + }; + + i2s0_pinctrl: i2s0-pinmux { + pinmux = , + , + ; + }; + + dvp_pinctrl: dvp-pinmux { + pinmux = , + , + , + , + , + , + , + ; + }; + + spi0_pinctrl: spi0-pinmux { + pinmux = , /* cs */ + , /* rst */ + , /* dc */ + ; /* wr */ + }; + + spi1_pinctrl: spi1-pinmux { + pinmux = , + , + , + ; /* cs */ + }; + + i2c1_pinctrl: i2c1-pinmux { + pinmux = , + ; + }; +}; + +&uarths0 { + pinctrl-0 = <&uarths_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio0 { + pinctrl-0 = <&gpiohs_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio1 { + pinctrl-0 = <&gpio_pinctrl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2s0 { + #sound-dai-cells = <1>; + pinctrl-0 = <&i2s0_pinctrl>; + pinctrl-names = "default"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pinctrl>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; +}; + +&dvp0 { + pinctrl-0 = <&dvp_pinctrl>; + pinctrl-names = "default"; +}; + +&spi0 { + pinctrl-0 = <&spi0_pinctrl>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + + panel@0 { + compatible = "sitronix,st7789v"; + reg = <0>; + reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; + spi-max-frequency = <15000000>; + spi-cs-high; + status = "disabled"; + }; +}; + +&spi1 { + pinctrl-0 = <&spi1_pinctrl>; + pinctrl-names = "default"; + num-cs = <1>; + cs-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + slot@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + voltage-ranges = <3300 3300>; + spi-max-frequency = <25000000>; + broken-cd; + }; +}; + +&spi3 { + spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + broken-flash-reset; + }; +};