From patchwork Wed Oct 28 15:16:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 1389616 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=glider.be Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CM4jL69tfz9sSP for ; Thu, 29 Oct 2020 10:36:54 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390549AbgJ1Xgx (ORCPT ); Wed, 28 Oct 2020 19:36:53 -0400 Received: from newton.telenet-ops.be ([195.130.132.45]:54828 "EHLO newton.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390546AbgJ1XfT (ORCPT ); Wed, 28 Oct 2020 19:35:19 -0400 Received: from baptiste.telenet-ops.be (baptiste.telenet-ops.be [IPv6:2a02:1800:120:4::f00:13]) by newton.telenet-ops.be (Postfix) with ESMTPS id 4CLsc85qxMzMwXV4 for ; Wed, 28 Oct 2020 16:16:40 +0100 (CET) Received: from ramsan.of.borg ([84.195.186.194]) by baptiste.telenet-ops.be with bizsmtp id lTGg2300A4C55Sk01TGgH4; Wed, 28 Oct 2020 16:16:40 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1kXnBn-000pDb-T3; Wed, 28 Oct 2020 16:16:39 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1kXnBn-007H8w-7w; Wed, 28 Oct 2020 16:16:39 +0100 From: Geert Uytterhoeven To: Linus Walleij Cc: Yoshihiro Shimoda , Ulrich Hecht , Biju Das , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 3/8] pinctrl: renesas: Reorder struct sh_pfc_pin to remove hole Date: Wed, 28 Oct 2020 16:16:32 +0100 Message-Id: <20201028151637.1734130-4-geert+renesas@glider.be> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201028151637.1734130-1-geert+renesas@glider.be> References: <20201028151637.1734130-1-geert+renesas@glider.be> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On arm64, pointer size and alignment is 64-bit, hence a 4-byte hole is present in between the enum_id and name members of the sh_pfc_pin structure. Get rid of this hole by sorting the structure's members by decreasing size. This saves up to 1.5 KiB per enabled SoC, and reduces the size of a kernel including support for all R-Car Gen3 SoCs by more than 10 KiB. This has no size impact on SH and arm32. Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/sh_pfc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index eff1bb872325ef3a..3b390dffacb4910d 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -34,10 +34,10 @@ enum { #define SH_PFC_PIN_CFG_NO_GPIO (1 << 31) struct sh_pfc_pin { - u16 pin; - u16 enum_id; const char *name; unsigned int configs; + u16 pin; + u16 enum_id; }; #define SH_PFC_PIN_GROUP_ALIAS(alias, n) \