From patchwork Wed Nov 6 15:47:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans de Goede X-Patchwork-Id: 1190525 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=redhat.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=redhat.com header.i=@redhat.com header.b="GWgWVBLz"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 477WBW6Hczz9sP3 for ; Thu, 7 Nov 2019 02:47:31 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728162AbfKFPrb (ORCPT ); Wed, 6 Nov 2019 10:47:31 -0500 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:45960 "EHLO us-smtp-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728572AbfKFPrb (ORCPT ); Wed, 6 Nov 2019 10:47:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1573055249; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2+9S/5JfhKXkKUxclVkXmBG4PflTeJsbRoedg306ync=; b=GWgWVBLz2bPWt1054msS56nh1oeRGG8gsJcW4RIqWlps334BZxc7dpttXzfhZ8G+hR0OkG K7F1dUovt6tjrJD1Wd0A+itK9gieLTSWvZ8k8XbN9ntJ85Z+/evKEOnAX2VzWEEOVctY2m 3rtoSfioXz1i/0e/siO9q5cCcv0MbXQ= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-313-ndHfNVWgOp6DoKKafQEmRA-1; Wed, 06 Nov 2019 10:47:26 -0500 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 2D828107ACC3; Wed, 6 Nov 2019 15:47:25 +0000 (UTC) Received: from shalem.localdomain.com (ovpn-116-167.ams2.redhat.com [10.36.116.167]) by smtp.corp.redhat.com (Postfix) with ESMTP id BD47A5D70E; Wed, 6 Nov 2019 15:47:23 +0000 (UTC) From: Hans de Goede To: Mika Westerberg , Andy Shevchenko , Bartosz Golaszewski , Linus Walleij Cc: Hans de Goede , linux-gpio@vger.kernel.org, linux-acpi@vger.kernel.org Subject: [PATCH v2 3/3] pinctrl: cherryview: Pass irqchip when adding gpiochip Date: Wed, 6 Nov 2019 16:47:15 +0100 Message-Id: <20191106154715.155596-4-hdegoede@redhat.com> In-Reply-To: <20191106154715.155596-1-hdegoede@redhat.com> References: <20191106154715.155596-1-hdegoede@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-MC-Unique: ndHfNVWgOp6DoKKafQEmRA-1 X-Mimecast-Spam-Score: 0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Signed-off-by: Hans de Goede --- Changes in v2: - Add kerneldoc for chv_pinctrl.irq struct member --- drivers/pinctrl/intel/pinctrl-cherryview.c | 42 +++++++++++----------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 1ded4bd8d1b4..e7c78acdcfbc 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -150,6 +150,7 @@ struct chv_pin_context { * @irqchip: IRQ chip in this pin controller * @regs: MMIO registers * @need_valid_mask: Use chip.irq.init_valid_mask ? + * @irq: Our parent irq * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO * offset (in GPIO number space) * @community: Community this pinctrl instance represents @@ -167,6 +168,7 @@ struct chv_pinctrl { struct irq_chip irqchip; void __iomem *regs; bool need_valid_mask; + unsigned int irq; unsigned intr_lines[16]; const struct chv_community *community; u32 saved_intmask; @@ -1620,16 +1622,25 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) chip->add_pin_ranges = chv_gpio_add_pin_ranges; chip->parent = pctrl->dev; chip->base = -1; - if (pctrl->need_valid_mask) - chip->irq.init_valid_mask = chv_init_irq_valid_mask; - ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); - if (ret) { - dev_err(pctrl->dev, "Failed to register gpiochip\n"); - return ret; - } + pctrl->irq = irq; + pctrl->irqchip.name = "chv-gpio"; + pctrl->irqchip.irq_startup = chv_gpio_irq_startup; + pctrl->irqchip.irq_ack = chv_gpio_irq_ack; + pctrl->irqchip.irq_mask = chv_gpio_irq_mask; + pctrl->irqchip.irq_unmask = chv_gpio_irq_unmask; + pctrl->irqchip.irq_set_type = chv_gpio_irq_type; + pctrl->irqchip.flags = IRQCHIP_SKIP_SET_WAKE; - chv_gpio_irq_init_hw(chip); + chip->irq.chip = &pctrl->irqchip; + if (pctrl->need_valid_mask) + chip->irq.init_valid_mask = chv_init_irq_valid_mask; + chip->irq.init_hw = chv_gpio_irq_init_hw; + chip->irq.parent_handler = chv_gpio_irq_handler; + chip->irq.num_parents = 1; + chip->irq.parents = &pctrl->irq; + chip->irq.default_type = IRQ_TYPE_NONE; + chip->irq.handler = handle_bad_irq; if (!pctrl->need_valid_mask) { irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0, @@ -1640,18 +1651,9 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) } } - pctrl->irqchip.name = "chv-gpio"; - pctrl->irqchip.irq_startup = chv_gpio_irq_startup; - pctrl->irqchip.irq_ack = chv_gpio_irq_ack; - pctrl->irqchip.irq_mask = chv_gpio_irq_mask; - pctrl->irqchip.irq_unmask = chv_gpio_irq_unmask; - pctrl->irqchip.irq_set_type = chv_gpio_irq_type; - pctrl->irqchip.flags = IRQCHIP_SKIP_SET_WAKE; - - ret = gpiochip_irqchip_add(chip, &pctrl->irqchip, 0, - handle_bad_irq, IRQ_TYPE_NONE); + ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); if (ret) { - dev_err(pctrl->dev, "failed to add IRQ chip\n"); + dev_err(pctrl->dev, "Failed to register gpiochip\n"); return ret; } @@ -1665,8 +1667,6 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) } } - gpiochip_set_chained_irqchip(chip, &pctrl->irqchip, irq, - chv_gpio_irq_handler); return 0; }