From patchwork Tue Jun 18 16:01:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick Williams X-Patchwork-Id: 1118094 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=amazon.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amazon.com header.i=@amazon.com header.b="YT6nFSrN"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45StB60xDyz9sNC for ; Wed, 19 Jun 2019 02:01:50 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729455AbfFRQBt (ORCPT ); Tue, 18 Jun 2019 12:01:49 -0400 Received: from smtp-fw-9101.amazon.com ([207.171.184.25]:34395 "EHLO smtp-fw-9101.amazon.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729209AbfFRQBs (ORCPT ); Tue, 18 Jun 2019 12:01:48 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1560873708; x=1592409708; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=5dxPM2jebBBl2HqfGDgN1kkUGse4zSbBuv7sLIXFwD0=; b=YT6nFSrNBaKjQ2G7yo9v4DyZ1N0WiyDEM2MNdp2VK55taAqd9c88eLv5 a7bCwgz3Y7ARU13dbxhWHMBwuobDDcDQQNgIRgB9sO6cAB/RTUc+roJ1Q +KRnE7v3zKpGgdfFWux6rOtUBnidPe4tUMhgTUwifyuGlpH3qLvYqZtn4 w=; X-IronPort-AV: E=Sophos;i="5.62,389,1554768000"; d="scan'208";a="811117649" Received: from sea3-co-svc-lb6-vlan2.sea.amazon.com (HELO email-inbound-relay-1a-715bee71.us-east-1.amazon.com) ([10.47.22.34]) by smtp-border-fw-out-9101.sea19.amazon.com with ESMTP; 18 Jun 2019 16:01:45 +0000 Received: from EX13MTAUWB001.ant.amazon.com (iad55-ws-svc-p15-lb9-vlan2.iad.amazon.com [10.40.159.162]) by email-inbound-relay-1a-715bee71.us-east-1.amazon.com (Postfix) with ESMTPS id CED09A2373; Tue, 18 Jun 2019 16:01:40 +0000 (UTC) Received: from EX13D21UWB001.ant.amazon.com (10.43.161.108) by EX13MTAUWB001.ant.amazon.com (10.43.161.207) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Tue, 18 Jun 2019 16:01:22 +0000 Received: from EX13MTAUWB001.ant.amazon.com (10.43.161.207) by EX13D21UWB001.ant.amazon.com (10.43.161.108) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Tue, 18 Jun 2019 16:01:22 +0000 Received: from 8c859006a84e.ant.amazon.com (172.26.203.28) by mail-relay.amazon.com (10.43.161.249) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Tue, 18 Jun 2019 16:01:20 +0000 From: CC: Benjamin Herrenschmidt , Patrick Williams , Jason Cooper , Andrew Lunn , Gregory Clement , "Sebastian Hesselbarth" , Linus Walleij , , , Subject: [PATCH 2/2] pinctrl: armada-37xx: fix control of pins 32 and up Date: Tue, 18 Jun 2019 11:01:05 -0500 Message-ID: <20190618160105.26343-3-alpawi@amazon.com> X-Mailer: git-send-email 2.17.2 (Apple Git-113) In-Reply-To: <20190618160105.26343-1-alpawi@amazon.com> References: <20190618160105.26343-1-alpawi@amazon.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Patrick Williams The 37xx configuration registers are only 32 bits long, so pins 32-35 spill over into the next register. The calculation for the register address was done, but the bitmask was not, so any configuration to pin 32 or above resulted in a bitmask that overflowed and performed no action. Fix the register / offset calculation to also adjust the offset. Signed-off-by: Patrick Williams --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 00598b6f5c2a..82c980c5cccd 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -221,11 +221,11 @@ static const struct armada_37xx_pin_data armada_37xx_pin_sb = { }; static inline void armada_37xx_calc_reg_offset(unsigned int *reg, - unsigned int offset) + unsigned int *offset) { /* We never have more than 2 registers */ - if (offset >= GPIO_PER_REG) { - offset -= GPIO_PER_REG; + if (*offset >= GPIO_PER_REG) { + *offset -= GPIO_PER_REG; *reg += sizeof(u32); } } @@ -376,7 +376,7 @@ static inline void armada_37xx_irq_update_reg(unsigned int *reg, { int offset = irqd_to_hwirq(d); - armada_37xx_calc_reg_offset(reg, offset); + armada_37xx_calc_reg_offset(reg, &offset); } static int armada_37xx_gpio_direction_input(struct gpio_chip *chip, @@ -386,7 +386,7 @@ static int armada_37xx_gpio_direction_input(struct gpio_chip *chip, unsigned int reg = OUTPUT_EN; unsigned int mask; - armada_37xx_calc_reg_offset(®, offset); + armada_37xx_calc_reg_offset(®, &offset); mask = BIT(offset); return regmap_update_bits(info->regmap, reg, mask, 0); @@ -399,7 +399,7 @@ static int armada_37xx_gpio_get_direction(struct gpio_chip *chip, unsigned int reg = OUTPUT_EN; unsigned int val, mask; - armada_37xx_calc_reg_offset(®, offset); + armada_37xx_calc_reg_offset(®, &offset); mask = BIT(offset); regmap_read(info->regmap, reg, &val); @@ -413,7 +413,7 @@ static int armada_37xx_gpio_direction_output(struct gpio_chip *chip, unsigned int reg = OUTPUT_EN; unsigned int mask, val, ret; - armada_37xx_calc_reg_offset(®, offset); + armada_37xx_calc_reg_offset(®, &offset); mask = BIT(offset); ret = regmap_update_bits(info->regmap, reg, mask, mask); @@ -434,7 +434,7 @@ static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset) unsigned int reg = INPUT_VAL; unsigned int val, mask; - armada_37xx_calc_reg_offset(®, offset); + armada_37xx_calc_reg_offset(®, &offset); mask = BIT(offset); regmap_read(info->regmap, reg, &val); @@ -449,7 +449,7 @@ static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset, unsigned int reg = OUTPUT_VAL; unsigned int mask, val; - armada_37xx_calc_reg_offset(®, offset); + armada_37xx_calc_reg_offset(®, &offset); mask = BIT(offset); val = value ? mask : 0;