From patchwork Sat Apr 13 16:54:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Ond=C5=99ej_Jirman?= X-Patchwork-Id: 1085193 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=reject dis=none) header.from=megous.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=megous.com header.i=@megous.com header.b="IJIRmPM0"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44hLVn6Sf3z9sBb for ; Sun, 14 Apr 2019 02:55:45 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726998AbfDMQzg (ORCPT ); Sat, 13 Apr 2019 12:55:36 -0400 Received: from vps.xff.cz ([195.181.215.36]:49062 "EHLO vps.xff.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727256AbfDMQyX (ORCPT ); Sat, 13 Apr 2019 12:54:23 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=megous.com; s=mail; t=1555174460; bh=uWFX8jAj5JCtgpScxODx75tXIzsjGiifzvL/hyBr8tU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IJIRmPM0tt4T9q3cSjY93VIrPKBqoMeDjdgvz/g98QbWQo7KPchY5dEyHkMFUI/wK 6qyNCCuuQOa+Y5qPmyj7yCJTYS7dAsA6zmWhNySwLcgp/3MNw/+4E/okI8AzoLUj3X JFGY8vy1GJ0mQAvS+PA+jH04cSnOMT+KeQ3n7fyQ= From: megous@megous.com To: linux-sunxi@googlegroups.com, Maxime Ripard , Chen-Yu Tsai , Rob Herring , Linus Walleij Cc: Ondrej Jirman , David Airlie , Daniel Vetter , Mark Rutland , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Maxime Coquelin , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-gpio@vger.kernel.org Subject: [PATCH v4 3/9] pinctrl: sunxi: Prepare for alternative bias voltage setting methods Date: Sat, 13 Apr 2019 18:54:12 +0200 Message-Id: <20190413165418.27880-4-megous@megous.com> In-Reply-To: <20190413165418.27880-1-megous@megous.com> References: <20190413165418.27880-1-megous@megous.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Ondrej Jirman H6 has a different I/O voltage bias setting method than A80. Prepare existing code for using alternative bias voltage setting methods. Signed-off-by: Ondrej Jirman Acked-by: Maxime Ripard --- drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c | 2 +- drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c | 2 +- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 47 ++++++++++++--------- drivers/pinctrl/sunxi/pinctrl-sunxi.h | 11 ++++- 4 files changed, 39 insertions(+), 23 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c index e05dd9a5551d..a191a65217ac 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c @@ -153,7 +153,7 @@ static const struct sunxi_pinctrl_desc sun9i_a80_r_pinctrl_data = { .pin_base = PL_BASE, .irq_banks = 2, .disable_strict_mode = true, - .has_io_bias_cfg = true, + .io_bias_cfg_variant = BIAS_VOLTAGE_GRP_CONFIG, }; static int sun9i_a80_r_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c index da37d594a13d..0633a03d5e13 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c @@ -722,7 +722,7 @@ static const struct sunxi_pinctrl_desc sun9i_a80_pinctrl_data = { .npins = ARRAY_SIZE(sun9i_a80_pins), .irq_banks = 5, .disable_strict_mode = true, - .has_io_bias_cfg = true, + .io_bias_cfg_variant = BIAS_VOLTAGE_GRP_CONFIG, }; static int sun9i_a80_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index be04223591d4..98c4de5f4019 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -617,7 +617,7 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, u32 val, reg; int uV; - if (!pctl->desc->has_io_bias_cfg) + if (!pctl->desc->io_bias_cfg_variant) return 0; uV = regulator_get_voltage(supply); @@ -628,25 +628,32 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, if (uV == 0) return 0; - /* Configured value must be equal or greater to actual voltage */ - if (uV <= 1800000) - val = 0x0; /* 1.8V */ - else if (uV <= 2500000) - val = 0x6; /* 2.5V */ - else if (uV <= 2800000) - val = 0x9; /* 2.8V */ - else if (uV <= 3000000) - val = 0xA; /* 3.0V */ - else - val = 0xD; /* 3.3V */ - - pin -= pctl->desc->pin_base; - - reg = readl(pctl->membase + sunxi_grp_config_reg(pin)); - reg &= ~IO_BIAS_MASK; - writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); - - return 0; + switch (pctl->desc->io_bias_cfg_variant) { + case BIAS_VOLTAGE_GRP_CONFIG: + /* + * Configured value must be equal or greater to actual + * voltage. + */ + if (uV <= 1800000) + val = 0x0; /* 1.8V */ + else if (uV <= 2500000) + val = 0x6; /* 2.5V */ + else if (uV <= 2800000) + val = 0x9; /* 2.8V */ + else if (uV <= 3000000) + val = 0xA; /* 3.0V */ + else + val = 0xD; /* 3.3V */ + + pin -= pctl->desc->pin_base; + + reg = readl(pctl->membase + sunxi_grp_config_reg(pin)); + reg &= ~IO_BIAS_MASK; + writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); + return 0; + default: + return -EINVAL; + } } static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index ee15ab067b5f..a62b81357136 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -95,6 +95,15 @@ #define PINCTRL_SUN7I_A20 BIT(7) #define PINCTRL_SUN8I_R40 BIT(8) +enum sunxi_desc_bias_voltage { + BIAS_VOLTAGE_NONE, + /* + * Bias voltage configuration is done through + * Pn_GRP_CONFIG registers, as seen on A80 SoC. + */ + BIAS_VOLTAGE_GRP_CONFIG, +}; + struct sunxi_desc_function { unsigned long variant; const char *name; @@ -117,7 +126,7 @@ struct sunxi_pinctrl_desc { const unsigned int *irq_bank_map; bool irq_read_needs_mux; bool disable_strict_mode; - bool has_io_bias_cfg; + enum sunxi_desc_bias_voltage io_bias_cfg_variant; }; struct sunxi_pinctrl_function {