From patchwork Tue Feb 26 11:50:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 1048264 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="jn+3IyUk"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 447xw03Dwkz9sBL for ; Tue, 26 Feb 2019 22:50:40 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726350AbfBZLuj (ORCPT ); Tue, 26 Feb 2019 06:50:39 -0500 Received: from mail-pl1-f195.google.com ([209.85.214.195]:37586 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726115AbfBZLuj (ORCPT ); Tue, 26 Feb 2019 06:50:39 -0500 Received: by mail-pl1-f195.google.com with SMTP id q3so6142414pll.4 for ; Tue, 26 Feb 2019 03:50:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=eSkZIpYqGQu03MiKs/ZrVx2wlOErDr8e6IcNNsqO99g=; b=jn+3IyUkPCgt6Y9fYP/1P9P6y3OtmQN1UUVR8aQBn/6/CUbfGr6eDU9bK8G1y5mH1u YH0iRITGECDfaksFLsgjc1P+xmmRm4XD5uJi2kjDW0/JxNjlLJMdQPCRyrvzR16VlfkI IpOWwSkrP8lJFHm2gBZ81fgrhiCkgEOWm2DMraGsyXxZYzUc8ipVPYCZru5yKeTuViuV 8y4iqLEe73qSgo3PGt2DxKMRdL3FpICTvKBsE5i1kWLraMJOWWPPiH5sbrF7kKxj9DCO mVUAFA9Kmp1mrdT+mS9DP/cXIrXYTA2mJA4Vm8xoeiOGdkJRdPYKdmhIJCu7DNg2Qycq W8wQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=eSkZIpYqGQu03MiKs/ZrVx2wlOErDr8e6IcNNsqO99g=; b=FOLK0ZuhN8CCtKkljdplDy8fv2qMVNrIOJMpU2EdunZDl2biIEdR+zyJ6sWkavRW3u Gf7mz5Thg4aqfnezt+6YQc6zQcs4IE8mbw7PKxyyQxL6JDpIpD+A6GXa+odBODeq0qVr 6WYQl/WH7/e/RTYm51V+l9fBcOksZzbecHGwjV9UNaPZeGYK6/dqJmyY1gUg9H4hpMJZ ka4NEDjwwvoXBKyvk+4OfP3MFJLC0X+ieCQzWvG5q9TqK2HMYA2fvHIecIayONzwp2dv 5m9SvWbBz8HtirzG/MUPKK5pX5zxsooxqsowBEiL48TrjwJZndJisH1SjtpTX0WDvR7X +c9g== X-Gm-Message-State: AHQUAuZr6adcpQ7QSQLc6M86dEkGRGJ2GryjMW+DgXKBM9sbLBSYSrKi AhcB+3yQ5CpFhYREfQWo8hxxV6Rmjg== X-Google-Smtp-Source: AHgI3IbMRmWyU2xURN7gN6VP/kb7Gu3EWjq2THo2Me64kHFXAFlyQhThTRuXcqhA3DRUAYTzCy9exg== X-Received: by 2002:a17:902:63:: with SMTP id 90mr24826573pla.122.1551181838281; Tue, 26 Feb 2019 03:50:38 -0800 (PST) Received: from localhost.localdomain ([2405:204:7288:2b3b:d5bf:2058:5f56:d25e]) by smtp.gmail.com with ESMTPSA id t10sm31639245pfa.151.2019.02.26.03.50.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 26 Feb 2019 03:50:37 -0800 (PST) From: Manivannan Sadhasivam To: linux-arm-kernel@lists.infradead.org, linus.walleij@linaro.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, haitao.suo@bitmain.com, darren.tsao@bitmain.com, amit.kucheria@linaro.org, linux-gpio@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 1/2] arm64: dts: bitmain: Add GPIO support for BM1880 SoC Date: Tue, 26 Feb 2019 17:20:21 +0530 Message-Id: <20190226115022.19022-1-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add GPIO support for Bitmain BM1880 SoC based on Designware APB GPIO controller IP. IP exposes 3 GPIO controllers with a total of 72 pins. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Linus Walleij --- arch/arm64/boot/dts/bitmain/bm1880.dtsi | 54 +++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/bitmain/bm1880.dtsi b/arch/arm64/boot/dts/bitmain/bm1880.dtsi index 55a4769e0de2..e4da4ec6a5ee 100644 --- a/arch/arm64/boot/dts/bitmain/bm1880.dtsi +++ b/arch/arm64/boot/dts/bitmain/bm1880.dtsi @@ -80,6 +80,60 @@ #interrupt-cells = <3>; }; + gpio0: gpio@50027000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x0 0x50027000 0x0 0x400>; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + }; + + gpio1: gpio@50027400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x0 0x50027400 0x0 0x400>; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + }; + + gpio2: gpio@50027800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x0 0x50027800 0x0 0x400>; + + portc: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + }; + uart0: serial@58018000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x58018000 0x0 0x2000>;