From patchwork Wed Jun 20 12:54:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mikko Perttunen X-Patchwork-Id: 932219 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 419lD843zmz9s7c for ; Wed, 20 Jun 2018 22:55:04 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753321AbeFTMzC (ORCPT ); Wed, 20 Jun 2018 08:55:02 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:8517 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752983AbeFTMzB (ORCPT ); Wed, 20 Jun 2018 08:55:01 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Wed, 20 Jun 2018 05:55:06 -0700 Received: from HQMAIL103.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 20 Jun 2018 05:55:00 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 20 Jun 2018 05:55:00 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 20 Jun 2018 12:55:00 +0000 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 20 Jun 2018 12:54:59 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Wed, 20 Jun 2018 12:54:59 +0000 Received: from mperttunen-lnx.Nvidia.com (Not Verified[10.21.26.144]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 20 Jun 2018 05:54:59 -0700 From: Mikko Perttunen To: , , , , CC: , , , , , Mikko Perttunen Subject: [PATCH 3/5] arm64: tegra: Add GPIO controller on Tegra194 Date: Wed, 20 Jun 2018 15:54:04 +0300 Message-ID: <20180620125406.11906-3-mperttunen@nvidia.com> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180620125406.11906-1-mperttunen@nvidia.com> References: <20180620125406.11906-1-mperttunen@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add the device tree node for the GPIO controller on Tegra194. Signed-off-by: Mikko Perttunen --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index d7f780b06fe2..abe2d688eb65 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -18,6 +18,23 @@ #size-cells = <1>; ranges = <0x0 0x0 0x0 0x40000000>; + gpio: gpio@2200000 { + compatible = "nvidia,tegra194-gpio"; + reg-names = "security", "gpio"; + reg = <0x2200000 0x10000>, + <0x2210000 0x10000>; + interrupts = , + , + , + , + , + ; + #interrupt-cells = <2>; + interrupt-controller; + #gpio-cells = <2>; + gpio-controller; + }; + uarta: serial@3100000 { compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; reg = <0x03100000 0x40>;