From patchwork Mon Jun 18 20:52:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 931203 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="eg01xkR1"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 418jxV0XLfz9s37 for ; Tue, 19 Jun 2018 06:53:50 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936899AbeFRUxn (ORCPT ); Mon, 18 Jun 2018 16:53:43 -0400 Received: from mail-pl0-f65.google.com ([209.85.160.65]:41566 "EHLO mail-pl0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935743AbeFRUxA (ORCPT ); Mon, 18 Jun 2018 16:53:00 -0400 Received: by mail-pl0-f65.google.com with SMTP id w8-v6so8164784ply.8 for ; Mon, 18 Jun 2018 13:53:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=meiSnBBK0ywRIXK/yaRVrlxaRWAocHhuZyzKLwIJ/aQ=; b=eg01xkR1S/aOOHhJacjxOBw57mLGnh87wAQ6JMjqNmoZGIW8lh/GHEGQOXpqkJ4atg QzbxAExUfy3oUxQUdyzxvSXAKKPvskL86PJhSdGG1CBQN8jZ9dShdnMxOqhk3mWOjQmh nvig4q3R+kN7dQ1mPu79MLs3Nq2CdwenzHSUA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=meiSnBBK0ywRIXK/yaRVrlxaRWAocHhuZyzKLwIJ/aQ=; b=ST/HUxyTtWeAdIoBSSLQIfUIXFNT2EAolAG66PQzEezesVAD576/uQXAEfSyk1egS6 UTj7OKFsezi9YZg0LpFvBg0PUQYlVueTLM6/qcBZ3kpDas7GB1IvNMXJFIGr/IQTlApZ DLUK/8aAR9pDNfQ2A4W65A3tzc3k3p9Foobf/Uc5fyOGF2yOMOgKT4SIE74QH2DTgQoU s+odArgBPNXZXIBU6DOWpIHNbK1YK9sAnU7KZ9ENcJhmEpez69z0eDU45mOGXYaYhRd2 hF1xjs9PcXk8/xdVmuNu7wDJxh1rpV/QmTg4qRimHO3JjJTo9d5D09+B8cM2L9XQUqhz NmIQ== X-Gm-Message-State: APt69E1VetqSS784115iJqBYi0hw1jrMm4BqYw2JLhPp8b5SXWo9zNYI WR8Ga4dJyz+kwY0UNB91HwDIjg== X-Google-Smtp-Source: ADUXVKJkhZ8dDNpGbbWKfOQs7+Vo31T8zaoGXI87BSuZycqhudwl8EmQAZlrZSnTdcHDns+zRH8A1Q== X-Received: by 2002:a17:902:2884:: with SMTP id f4-v6mr15735274plb.204.1529355179840; Mon, 18 Jun 2018 13:52:59 -0700 (PDT) Received: from swboyd.mtv.corp.google.com ([2620:0:1000:1511:d30e:62c6:f82c:ff40]) by smtp.gmail.com with ESMTPSA id a27-v6sm27052196pfc.18.2018.06.18.13.52.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 18 Jun 2018 13:52:59 -0700 (PDT) From: Stephen Boyd To: Linus Walleij Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-msm@vger.kernel.org, Bjorn Andersson , Doug Anderson Subject: [PATCH 2/3] pinctrl: msm: Mux out gpio function with gpio_request() Date: Mon, 18 Jun 2018 13:52:54 -0700 Message-Id: <20180618205255.246104-3-swboyd@chromium.org> X-Mailer: git-send-email 2.18.0.rc1.244.gcf134e6275-goog In-Reply-To: <20180618205255.246104-1-swboyd@chromium.org> References: <20180618205255.246104-1-swboyd@chromium.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org We rely on devices to use pinmuxing configurations in DT to select the GPIO function (function 0) if they're going to use the gpio in GPIO mode. Let's simplify things for driver authors by implementing gpio_request_enable() for this pinctrl driver to mux out the GPIO function when the gpio is use from gpiolib. Cc: Bjorn Andersson Cc: Doug Anderson Signed-off-by: Stephen Boyd Reviewed-by: Douglas Anderson Reviewed-by: Bjorn Andersson --- drivers/pinctrl/qcom/pinctrl-msm.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 3563c4394837..eacfc5b85f7f 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -176,11 +176,27 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, return 0; } +static int msm_pinmux_request_gpio(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset) +{ + struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + const struct msm_pingroup *g = &pctrl->soc->groups[offset]; + + /* No funcs? Probably ACPI so can't do anything here */ + if (!g->nfuncs) + return 0; + + /* For now assume function 0 is GPIO because it always is */ + return msm_pinmux_set_mux(pctldev, 0, offset); +} + static const struct pinmux_ops msm_pinmux_ops = { .request = msm_pinmux_request, .get_functions_count = msm_get_functions_count, .get_function_name = msm_get_function_name, .get_function_groups = msm_get_function_groups, + .gpio_request_enable = msm_pinmux_request_gpio, .set_mux = msm_pinmux_set_mux, };