From patchwork Mon Nov 13 01:25:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 837316 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yZtJ33Bz4z9sBW for ; Mon, 13 Nov 2017 12:25:55 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751389AbdKMBZy (ORCPT ); Sun, 12 Nov 2017 20:25:54 -0500 Received: from foss.arm.com ([217.140.101.70]:42078 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751095AbdKMBZy (ORCPT ); Sun, 12 Nov 2017 20:25:54 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DE488164F; Sun, 12 Nov 2017 17:25:53 -0800 (PST) Received: from slackpad.lan (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BDB3E3F58F; Sun, 12 Nov 2017 17:25:51 -0800 (PST) From: Andre Przywara To: Linus Walleij , Maxime Ripard , Chen-Yu Tsai Cc: linux-gpio@vger.kernel.org, Rob Herring , Mark Rutland , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Arnd Bergmann , Icenowy Zheng Subject: [RFC PATCH 3/3] arm64: dts: allwinner: enhance A64 .dtsi with new pinctrl binding Date: Mon, 13 Nov 2017 01:25:23 +0000 Message-Id: <20171113012523.2328-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171113012523.2328-1-andre.przywara@arm.com> References: <20171113012523.2328-1-andre.przywara@arm.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Enhance the existing pinctrl DT nodes for the Allwinner A64 SoC to include the new properties the generic, DT-based binding introduced. This allows any generic driver to support this SoC as well. The DT nodes stay fully compatible with the old binding, so existing drivers continue to work without restrictions. But on top of that new DT users can directly use the information here and can do without a hardcoded table. Signed-off-by: Andre Przywara --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 8c8db1b057df..58fdae32240a 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -269,7 +269,8 @@ }; pio: pinctrl@1c20800 { - compatible = "allwinner,sun50i-a64-pinctrl"; + compatible = "allwinner,sun50i-a64-pinctrl", + "allwinner,sunxi-pinctrl"; reg = <0x01c20800 0x400>; interrupts = , , @@ -279,16 +280,22 @@ #gpio-cells = <3>; interrupt-controller; #interrupt-cells = <3>; + allwinner,gpio-pins = <0 10 17 25 18 7 14 12>; + allwinner,irq-pin-map = <0 0 1 0 6 10>, + <1 0 6 0 6 14>, + <2 0 7 0 6 12>; i2c1_pins: i2c1_pins { pins = "PH2", "PH3"; function = "i2c1"; + pinmux = <2>; }; mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; function = "mmc0"; + pinmux = <2>; drive-strength = <30>; bias-pull-up; }; @@ -297,6 +304,7 @@ pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; function = "mmc1"; + pinmux = <2>; drive-strength = <30>; bias-pull-up; }; @@ -306,6 +314,7 @@ "PC10","PC11", "PC12", "PC13", "PC14", "PC15", "PC16"; function = "mmc2"; + pinmux = <3>; drive-strength = <30>; bias-pull-up; }; @@ -314,6 +323,7 @@ pins = "PD10", "PD11", "PD13", "PD14", "PD17", "PD18", "PD19", "PD20", "PD22", "PD23"; function = "emac"; + pinmux = <4>; drive-strength = <40>; }; @@ -322,42 +332,50 @@ "PD13", "PD15", "PD16", "PD17", "PD18", "PD19", "PD20", "PD21", "PD22", "PD23"; function = "emac"; + pinmux = <4>; drive-strength = <40>; }; uart0_pins_a: uart0@0 { pins = "PB8", "PB9"; function = "uart0"; + pinmux = <4>; }; uart1_pins: uart1_pins { pins = "PG6", "PG7"; function = "uart1"; + pinmux = <2>; }; uart1_rts_cts_pins: uart1_rts_cts_pins { pins = "PG8", "PG9"; function = "uart1"; + pinmux = <2>; }; uart2_pins: uart2-pins { pins = "PB0", "PB1"; function = "uart2"; + pinmux = <2>; }; uart3_pins: uart3-pins { pins = "PD0", "PD1"; function = "uart3"; + pinmux = <3>; }; uart4_pins: uart4-pins { pins = "PD2", "PD3"; function = "uart4"; + pinmux = <3>; }; uart4_rts_cts_pins: uart4-rts-cts-pins { pins = "PD4", "PD5"; function = "uart4"; + pinmux = <3>; }; }; @@ -487,7 +505,8 @@ }; r_pio: pinctrl@01f02c00 { - compatible = "allwinner,sun50i-a64-r-pinctrl"; + compatible = "allwinner,sun50i-a64-r-pinctrl", + "allwinner,sunxi-pinctrl"; reg = <0x01f02c00 0x400>; interrupts = ; clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; @@ -496,10 +515,14 @@ #gpio-cells = <3>; interrupt-controller; #interrupt-cells = <3>; + allwinner,gpio-pins = <13>; + allwinner,port-base = <11>; + allwinner,irq-pin-map = <0 0 11 0 6 13>; r_rsb_pins: rsb@0 { pins = "PL0", "PL1"; function = "s_rsb"; + pinmux = <2>; }; };