From patchwork Mon May 22 06:25:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 765263 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3wWTFM5Ytyz9s3s for ; Mon, 22 May 2017 16:26:15 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752102AbdEVG0K (ORCPT ); Mon, 22 May 2017 02:26:10 -0400 Received: from mirror2.csie.ntu.edu.tw ([140.112.30.76]:48704 "EHLO wens.csie.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750885AbdEVG0I (ORCPT ); Mon, 22 May 2017 02:26:08 -0400 Received: by wens.csie.org (Postfix, from userid 1000) id A01AF5FD52; Mon, 22 May 2017 14:26:05 +0800 (CST) From: Chen-Yu Tsai To: Linus Walleij , Maxime Ripard Cc: Chen-Yu Tsai , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Subject: [PATCH 1/6] clk: sunxi-ng: a83t: Fix PLL lock status register offset Date: Mon, 22 May 2017 14:25:47 +0800 Message-Id: <20170522062552.19026-2-wens@csie.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170522062552.19026-1-wens@csie.org> References: <20170522062552.19026-1-wens@csie.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The offset for the PLL lock status register was incorrectly set to 0x208, which actually points to an unused register. The correct register offset is 0x20c. Signed-off-by: Chen-Yu Tsai --- drivers/clk/sunxi-ng/ccu-sun8i-a83t.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c index 4a201a7e03b8..a9c5cc87d9d0 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c @@ -28,7 +28,7 @@ #include "ccu-sun8i-a83t.h" -#define CCU_SUN8I_A83T_LOCK_REG 0x208 +#define CCU_SUN8I_A83T_LOCK_REG 0x20c /* * The CPU PLLs are actually NP clocks, with P being /1 or /4. However