From patchwork Sat May 6 16:57:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 759346 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3wKw1w0Gq2z9s8W for ; Sun, 7 May 2017 02:58:12 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=googlemail.com header.i=@googlemail.com header.b="L004r9B/"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752027AbdEFQ6K (ORCPT ); Sat, 6 May 2017 12:58:10 -0400 Received: from mail-wm0-f67.google.com ([74.125.82.67]:33785 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751619AbdEFQ6J (ORCPT ); Sat, 6 May 2017 12:58:09 -0400 Received: by mail-wm0-f67.google.com with SMTP id y10so6959932wmh.0 for ; Sat, 06 May 2017 09:58:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rnni9A3kPiOM9oZHI3yyEUzy1OQSpqN2ZQSihuDdv6A=; b=L004r9B/EF378TiosXzx2oHJlhaOtxmNbB6dIVFCYiyjGL6pPD/AAVexSdW0cda2zc b1jRwpQoxbQ2EdJJIVaZG1+qBsRnRYLLBcu9x+zhtbl9nOKNk0O6LW474//Ykahw4p8A 1kWoloQ763fgqDFhtq7639/eKKYeaFyRn2i/hkQhMKnu5DSQVdU2OBz2lDpZf9a4E1W9 J0UG9bz2P2jha03qRmGR0UbruwPLe1Ydw4BDl6ZI+jO6Rmbd1JQG0WAG4UpONR374C4M lW+OluW49xvNpWGEJ5PZAVYWpelIf3qX45TNXjzpUo9S4+x0bK/sFLbW8RFMvDvA4buR hPPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rnni9A3kPiOM9oZHI3yyEUzy1OQSpqN2ZQSihuDdv6A=; b=Hg2ej2hkTCDWswNmMsTGWv8+2uoywYpk25oxS3u+aAwG43MakpvxV5BLpp87aj4SjI ujeIxQCmutnn+o6IeYaUaQrS+VjgrbwTwHcKBjfLBExCZmlW+tT6MVR5kryTfZXADQbK Z5sTHNj+yvVnXYkBwqqeDBxnjMbFg8jgLhXASCIUJywFu/GVWCiyo49ree6grfwYqmKD +YUZBvftUtnpt6m3rMFJUweLDzN52foIOmFnW+gJYVFdOpma9XnKmSvUc/sdYdrGVSJA DOQhibwLMK3RRMvHSSvNaGNdS00asHlU2wYWilGCGf5/UgCToYOVvfm8f+FaCvVgxuuC e2EA== X-Gm-Message-State: AODbwcA3D884zn8uexLOCBSfEC3XObGeeMCrbCrXXtS1GsgTcDYzrXvQ XXcmm6LsbSAOJQ== X-Received: by 10.28.168.3 with SMTP id r3mr4983773wme.33.1494089887769; Sat, 06 May 2017 09:58:07 -0700 (PDT) Received: from blackbox.darklights.net (p200300DCD3E78B041DCA91B6F8D469E4.dip0.t-ipconnect.de. [2003:dc:d3e7:8b04:1dca:91b6:f8d4:69e4]) by smtp.googlemail.com with ESMTPSA id 30sm6961858wrp.6.2017.05.06.09.58.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 06 May 2017 09:58:07 -0700 (PDT) From: Martin Blumenstingl To: linus.walleij@linaro.org, carlo@caione.org, khilman@baylibre.com, linux-gpio@vger.kernel.org, linux-amlogic@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, Martin Blumenstingl Subject: [PATCH v2 2/4] pinctrl: meson: meson8: add support for the I2S and SPDIF pins Date: Sat, 6 May 2017 18:57:49 +0200 Message-Id: <20170506165751.12442-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.12.2 In-Reply-To: <20170506165751.12442-1-martin.blumenstingl@googlemail.com> References: <20170504184932.5372-1-martin.blumenstingl@googlemail.com> <20170506165751.12442-1-martin.blumenstingl@googlemail.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This adds support for the I2S and SPDIF input and output pins, similar to what we have on GXBB and GXL. Signed-off-by: Martin Blumenstingl --- drivers/pinctrl/meson/pinctrl-meson8.c | 52 ++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/drivers/pinctrl/meson/pinctrl-meson8.c b/drivers/pinctrl/meson/pinctrl-meson8.c index 0ec638655a42..6e36a9602999 100644 --- a/drivers/pinctrl/meson/pinctrl-meson8.c +++ b/drivers/pinctrl/meson/pinctrl-meson8.c @@ -224,6 +224,18 @@ static const unsigned int i2c_sck_c0_pins[] = { PIN(GPIOY_1, 0) }; static const unsigned int pwm_a_y_pins[] = { PIN(GPIOY_16, 0) }; +static const unsigned int i2s_out_ch45_pins[] = { PIN(GPIOY_0, 0) }; +static const unsigned int i2s_out_ch23_pins[] = { PIN(GPIOY_1, 0) }; +static const unsigned int i2s_out_ch01_pins[] = { PIN(GPIOY_4, 0) }; +static const unsigned int i2s_in_ch01_pins[] = { PIN(GPIOY_5, 0) }; +static const unsigned int i2s_lr_clk_in_pins[] = { PIN(GPIOY_6, 0) }; +static const unsigned int i2s_ao_clk_in_pins[] = { PIN(GPIOY_7, 0) }; +static const unsigned int i2s_am_clk_pins[] = { PIN(GPIOY_8, 0) }; +static const unsigned int i2s_out_ch78_pins[] = { PIN(GPIOY_9, 0) }; + +static const unsigned int spdif_in_pins[] = { PIN(GPIOY_2, 0) }; +static const unsigned int spdif_out_pins[] = { PIN(GPIOY_3, 0) }; + /* bank DV */ static const unsigned int dvin_rgb_pins[] = { PIN(GPIODV_0, 0), PIN(GPIODV_1, 0), PIN(GPIODV_2, 0), PIN(GPIODV_3, 0), @@ -398,6 +410,11 @@ static const unsigned int i2c_mst_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) }; static const unsigned int pwm_f_ao_pins[] = { PIN(GPIO_TEST_N, AO_OFF) }; +static const unsigned int i2s_am_clk_out_ao_pins[] = { PIN(GPIOAO_8, AO_OFF) }; +static const unsigned int i2s_ao_clk_out_ao_pins[] = { PIN(GPIOAO_9, AO_OFF) }; +static const unsigned int i2s_lr_clk_out_ao_pins[] = { PIN(GPIOAO_10, AO_OFF) }; +static const unsigned int i2s_out_ch01_ao_pins[] = { PIN(GPIOAO_11, AO_OFF) }; + static struct meson_pmx_group meson8_cbus_groups[] = { GPIO_GROUP(GPIOX_0, 0), GPIO_GROUP(GPIOX_1, 0), @@ -558,6 +575,18 @@ static struct meson_pmx_group meson8_cbus_groups[] = { GROUP(pwm_a_y, 9, 14), + GROUP(i2s_out_ch45, 1, 10), + GROUP(i2s_out_ch23, 1, 19), + GROUP(i2s_out_ch01, 1, 6), + GROUP(i2s_in_ch01, 1, 5), + GROUP(i2s_lr_clk_in, 1, 4), + GROUP(i2s_ao_clk_in, 1, 2), + GROUP(i2s_am_clk, 1, 0), + GROUP(i2s_out_ch78, 1, 11), + + GROUP(spdif_in, 1, 8), + GROUP(spdif_out, 1, 7), + /* bank DV */ GROUP(dvin_rgb, 0, 6), GROUP(dvin_vs, 0, 9), @@ -733,6 +762,11 @@ static struct meson_pmx_group meson8_aobus_groups[] = { GROUP(i2c_mst_sda_ao, 0, 5), GROUP(pwm_f_ao, 0, 19), + + GROUP(i2s_am_clk_out_ao, 0, 30), + GROUP(i2s_ao_clk_out_ao, 0, 29), + GROUP(i2s_lr_clk_out_ao, 0, 28), + GROUP(i2s_out_ch01_ao, 0, 27), }; static const char * const gpio_groups[] = { @@ -860,6 +894,12 @@ static const char * const i2c_b_groups[] = { "i2c_sda_b", "i2c_sck_b" }; +static const char * const i2s_groups[] = { + "i2s_out_ch45", "i2s_out_ch23_pins", "i2s_out_ch01_pins", + "i2s_in_ch01_pins", "i2s_lr_clk_in_pins", "i2s_ao_clk_in_pins", + "i2s_am_clk_pins", "i2s_out_ch78_pins" +}; + static const char * const sd_c_groups[] = { "sd_d0_c", "sd_d1_c", "sd_d2_c", "sd_d3_c", "sd_cmd_c", "sd_clk_c" @@ -910,6 +950,10 @@ static const char * const sdxc_b_groups[] = { "sdxc_d13_b", "sdxc_d0_b", "sdxc_clk_b", "sdxc_cmd_b" }; +static const char * const spdif_groups[] = { + "spdif_in", "spdif_out" +}; + static const char * const uart_ao_groups[] = { "uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a" }; @@ -934,6 +978,11 @@ static const char * const pwm_f_ao_groups[] = { "pwm_f_ao" }; +static const char * const i2s_ao_groups[] = { + "i2s_am_clk_out_ao", "i2s_ao_clk_out_ao", "i2s_lr_clk_out_ao", + "i2s_out_ch01_ao" +}; + static struct meson_pmx_func meson8_cbus_functions[] = { FUNCTION(gpio), FUNCTION(sd_a), @@ -966,6 +1015,8 @@ static struct meson_pmx_func meson8_cbus_functions[] = { FUNCTION(pwm_c), FUNCTION(pwm_d), FUNCTION(pwm_e), + FUNCTION(i2s), + FUNCTION(spdif), }; static struct meson_pmx_func meson8_aobus_functions[] = { @@ -975,6 +1026,7 @@ static struct meson_pmx_func meson8_aobus_functions[] = { FUNCTION(uart_ao_b), FUNCTION(i2c_mst_ao), FUNCTION(pwm_f_ao), + FUNCTION(i2s_ao), }; static struct meson_bank meson8_cbus_banks[] = {