[v3] pinctrl: sh-pfc: r8a7791: add R8A7743 support

Message ID	20170413201346.358012116@cogentembedded.com
State	New
Headers	show Return-Path: <linux-gpio-owner@vger.kernel.org> From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Message-Id: <20170413201346.358012116@cogentembedded.com> User-Agent: quilt/0.64 Date: Thu, 13 Apr 2017 23:13:32 +0300 To: Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Laurent Pinchart <laurent.pinchart@ideasonboard.com>, Geert Uytterhoeven <geert+renesas@glider.be>, Linus Walleij <linus.walleij@linaro.org>, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Subject: [PATCH v3] pinctrl: sh-pfc: r8a7791: add R8A7743 support MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Disposition: inline; filename=pinctrl-sh-pfc-r8a7791-add-R8A7743-support-v3.patch Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk

Index: linux-pinctrl/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt =================================================================== --- linux-pinctrl.orig/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +++ linux-pinctrl/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt @@ -13,6 +13,7 @@ Required Properties: - "renesas,pfc-emev2": for EMEV2 (EMMA Mobile EV2) compatible pin-controller. - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller. - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller. + - "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller. - "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller. - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller. - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller. Index: linux-pinctrl/drivers/pinctrl/sh-pfc/Kconfig =================================================================== --- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/Kconfig +++ linux-pinctrl/drivers/pinctrl/sh-pfc/Kconfig @@ -34,6 +34,11 @@ config PINCTRL_PFC_R8A7740 depends on ARCH_R8A7740 select PINCTRL_SH_PFC_GPIO +config PINCTRL_PFC_R8A7743 + def_bool y + depends on ARCH_R8A7743 + select PINCTRL_SH_PFC + config PINCTRL_PFC_R8A7778 def_bool y depends on ARCH_R8A7778 Index: linux-pinctrl/drivers/pinctrl/sh-pfc/Makefile =================================================================== --- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/Makefile +++ linux-pinctrl/drivers/pinctrl/sh-pfc/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_PINCTRL_SH_PFC_GPIO) += gpi obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-emev2.o obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o +obj-$(CONFIG_PINCTRL_PFC_R8A7743) += pfc-r8a7791.o obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o Index: linux-pinctrl/drivers/pinctrl/sh-pfc/core.c =================================================================== --- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/core.c +++ linux-pinctrl/drivers/pinctrl/sh-pfc/core.c @@ -485,6 +485,12 @@ static const struct of_device_id sh_pfc_ .data = &r8a7740_pinmux_info, }, #endif +#ifdef CONFIG_PINCTRL_PFC_R8A7743 + { + .compatible = "renesas,pfc-r8a7743", + .data = &r8a7743_pinmux_info, + }, +#endif #ifdef CONFIG_PINCTRL_PFC_R8A7778 { .compatible = "renesas,pfc-r8a7778", Index: linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7791.c =================================================================== --- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -1,8 +1,8 @@ /* - * r8a7791 processor support - PFC hardware block. + * r8a7791/r8a7743 processor support - PFC hardware block. * * Copyright (C) 2013 Renesas Electronics Corporation - * Copyright (C) 2014-2015 Cogent Embedded, Inc. + * Copyright (C) 2014-2017 Cogent Embedded, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 @@ -129,11 +129,12 @@ enum { FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA, FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D, FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D, - FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D, - FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D, - FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D, - FN_A15, FN_BPFCLK_C, - FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B, + FN_A12, FN_FMCLK /* R8A779x only */, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D, + FN_A13, FN_ATAG0_N_C, FN_BPFCLK /* R8A779x only */, FN_MSIOF1_SS1_D, + FN_A14, FN_ATADIR0_N_C, FN_FMIN /* R8A779x only */, + FN_FMIN_C /* R8A779x only */, FN_MSIOF1_SYNC_D, + FN_A15, FN_BPFCLK_C /* R8A779x only */, + FN_A16, FN_DREQ2_B, FN_FMCLK_C /* R8A779x only */, FN_SCIFA1_SCK_B, FN_A17, FN_DACK2_B, FN_I2C0_SDA_C, FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, FN_SCIFB1_RXD_C, @@ -141,8 +142,9 @@ enum { FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, FN_SCIFB1_TXD_C, FN_SCIFB1_SCK_B, FN_A20, FN_SPCLK, FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, - FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD, - FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD, + FN_A22, FN_MISO_IO1, FN_FMCLK_B /* R8A779x only */, FN_TX0, + FN_SCIFA0_TXD, + FN_A23, FN_IO2, FN_BPFCLK_B /* R8A779x only */, FN_RX0, FN_SCIFA0_RXD, FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD, FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD, FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL, @@ -157,13 +159,14 @@ enum { FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B, FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, - FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D, + FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B /* R8A779x only */, FN_SCIFB0_RXD_B, + FN_DREQ1_D, FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B, FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, FN_DREQ0, FN_PWM3, FN_TPU_TO3, - FN_DACK0, FN_DRACK0, FN_REMOCON, - FN_SPEEDIN, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B, + FN_DACK0, FN_DRACK0, FN_REMOCON /* R8A779x only */, + FN_SPEEDIN /* R8A779x only */, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B, FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D, FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C, FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C, @@ -171,138 +174,164 @@ enum { /* IPSR4 */ FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C, FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B, FN_MSIOF2_SYNC_C, - FN_GLO_I0_D, - FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D, + FN_GLO_I0_D /* R8A779x only */, + FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C, + FN_GLO_I1_D /* R8A779x only */, FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C, - FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E, - FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E, - FN_GLO_Q1_D, FN_HCTS1_N_E, - FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E, + FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B /* R8A779x only */, + FN_GLO_Q0_D /* R8A779x only */, FN_HSCK1_E, + FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B /* R8A779x only */, FN_RX2_E, + FN_GLO_Q1_D /* R8A779x only */, FN_HCTS1_N_E, + FN_SSI_SDATA2, FN_GPS_MAG_B /* R8A779x only */, FN_TX2_E, FN_HRTS1_N_E, FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3, - FN_SSI_SCK4, FN_GLO_SS_D, - FN_SSI_WS4, FN_GLO_RFON_D, + FN_SSI_SCK4, FN_GLO_SS_D /* R8A779x only */, + FN_SSI_WS4, FN_GLO_RFON_D /* R8A779x only */, FN_SSI_SDATA4, FN_MSIOF2_SCK_D, - FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0, + FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, + FN_GLO_I0 /* R8A779x only */, FN_MSIOF2_SYNC_D, FN_VI1_R2_B, /* IPSR5 */ - FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1, + FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1 /* R8A779x only */, FN_MSIOF2_TXD_D, FN_VI1_R3_B, - FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0, - FN_MSIOF2_SS1_D, FN_VI1_R4_B, - FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1, - FN_MSIOF2_RXD_D, FN_VI1_R5_B, - FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B, - FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B, - FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, - FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON, - FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, - FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, - FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, - FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D, + FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, + FN_GLO_Q0 /* R8A779x only */, FN_MSIOF2_SS1_D, FN_VI1_R4_B, + FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, + FN_GLO_Q1 /* R8A779x only */, FN_MSIOF2_RXD_D, FN_VI1_R5_B, + FN_SSI_WS6, FN_GLO_SCLK /* R8A779x only */, FN_MSIOF2_SS2_D, + FN_VI1_R6_B, + FN_SSI_SDATA6, FN_STP_IVCXO27_0_B /* R8A779x only */, + FN_GLO_SDATA /* R8A779x only */, FN_VI1_R7_B, + FN_SSI_SCK78, FN_STP_ISCLK_0_B /* R8A779x only */, + FN_GLO_SS /* R8A779x only */, + FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B /* R8A779x only */, + FN_GLO_RFON /* R8A779x only */, + FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B /* R8A779x only */, + FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B /* R8A779x only */, + FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D /* R8A779x only */, + FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D /* R8A779x only */, FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D, /* IPSR6 */ - FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B, - FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E, + FN_AUDIO_CLKB, FN_STP_OPWM_0_B /* R8A779x only */, FN_MSIOF1_SCK_B, + FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E /* R8A779x only */, FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2, - FN_SCIFA2_RXD, FN_FMIN_E, + FN_SCIFA2_RXD, FN_FMIN_E /* R8A779x only */, FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD, - FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, - FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, - FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, - FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N, - FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N, + FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N /* R8A779x only */, + FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N /* R8A779x only */, + FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N /* R8A779x only */, + FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, + FN_INTC_IRQ3_N /* R8A779x only */, + FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, + FN_INTC_IRQ4_N /* R8A779x only */, FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E, FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E, - FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D, - FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D, + FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C /* R8A779x only */, + FN_GPS_CLK_D /* R8A779x only */, + FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, + FN_GPS_SIGN_C /* R8A779x only */, FN_GPS_SIGN_D /* R8A779x only */, /* IPSR7 */ - FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C, - FN_SCIF_CLK_B, FN_GPS_MAG_D, - FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B, + FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, + FN_GPS_MAG_C /* R8A779x only */, + FN_SCIF_CLK_B, FN_GPS_MAG_D /* R8A779x only */, + FN_DU1_DR0, FN_LCDOUT0 /* R8A779x only */, FN_VI1_DATA0_B, FN_TX0_B, FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B, - FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B, + FN_DU1_DR1, FN_LCDOUT1 /* R8A779x only */, FN_VI1_DATA1_B, FN_RX0_B, FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B, - FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, - FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, - FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, - FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, - FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, - FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, - FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B, + FN_DU1_DR2, FN_LCDOUT2 /* R8A779x only */, FN_SSI_SCK0129_B, + FN_DU1_DR3, FN_LCDOUT3 /* R8A779x only */, FN_SSI_WS0129_B, + FN_DU1_DR4, FN_LCDOUT4 /* R8A779x only */, FN_SSI_SDATA0_B, + FN_DU1_DR5, FN_LCDOUT5 /* R8A779x only */, FN_SSI_SCK1_B, + FN_DU1_DR6, FN_LCDOUT6 /* R8A779x only */, FN_SSI_WS1_B, + FN_DU1_DR7, FN_LCDOUT7 /* R8A779x only */, FN_SSI_SDATA1_B, + FN_DU1_DG0, FN_LCDOUT8 /* R8A779x only */, FN_VI1_DATA2_B, FN_TX1_B, FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B, - FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B, + FN_DU1_DG1, FN_LCDOUT9 /* R8A779x only */, FN_VI1_DATA3_B, FN_RX1_B, FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B, - FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B, - FN_SCIFA1_SCK, FN_SSI_SCK78_B, + FN_DU1_DG2, FN_LCDOUT10 /* R8A779x only */, FN_VI1_DATA4_B, + FN_SCIF1_SCK_B, FN_SCIFA1_SCK, FN_SSI_SCK78_B, /* IPSR8 */ - FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, FN_SSI_WS78_B, - FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B, + FN_DU1_DG3, FN_LCDOUT11 /* R8A779x only */, FN_VI1_DATA5_B, + FN_SSI_WS78_B, + FN_DU1_DG4, FN_LCDOUT12 /* R8A779x only */, FN_VI1_DATA6_B, FN_HRX0_B, FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B, - FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B, + FN_DU1_DG5, FN_LCDOUT13 /* R8A779x only */, FN_VI1_DATA7_B, + FN_HCTS0_N_B, FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B, - FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B, + FN_DU1_DG6, FN_LCDOUT14 /* R8A779x only */, FN_HRTS0_N_B, FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B, - FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B, - FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B, + FN_DU1_DG7, FN_LCDOUT15 /* R8A779x only */, FN_HTX0_B, + FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B, + FN_DU1_DB0, FN_LCDOUT16 /* R8A779x only */, FN_VI1_CLK_B, FN_TX2_B, FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B, - FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B, + FN_DU1_DB1, FN_LCDOUT17 /* R8A779x only */, FN_VI1_HSYNC_N_B, FN_RX2_B, FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B, - FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B, - FN_SCIFA2_SCK, FN_SSI_SDATA9_B, - FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, - FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX, - FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX, + FN_DU1_DB2, FN_LCDOUT18 /* R8A779x only */, FN_VI1_VSYNC_N_B, + FN_SCIF2_SCK_B, FN_SCIFA2_SCK, FN_SSI_SDATA9_B, + FN_DU1_DB3, FN_LCDOUT19 /* R8A779x only */, FN_VI1_CLKENB_B, + FN_DU1_DB4, FN_LCDOUT20 /* R8A779x only */, FN_VI1_FIELD_B, FN_CAN1_RX, + FN_DU1_DB5, FN_LCDOUT21 /* R8A779x only */, FN_TX3, FN_SCIFA3_TXD, + FN_CAN1_TX, /* IPSR9 */ - FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD, - FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C, FN_SCIF3_SCK, FN_SCIFA3_SCK, - FN_DU1_DOTCLKIN, FN_QSTVA_QVS, - FN_DU1_DOTCLKOUT0, FN_QCLK, - FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX, + FN_DU1_DB6, FN_LCDOUT22 /* R8A779x only */, FN_I2C3_SCL_C, FN_RX3, + FN_SCIFA3_RXD, + FN_DU1_DB7, FN_LCDOUT23 /* R8A779x only */, FN_I2C3_SDA_C, FN_SCIF3_SCK, + FN_SCIFA3_SCK, + FN_DU1_DOTCLKIN, FN_QSTVA_QVS /* R8A779x only */, + FN_DU1_DOTCLKOUT0, FN_QCLK /* R8A779x only */, + FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE /* R8A779x only */, FN_CAN0_TX, FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4, - FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS, - FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE, - FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE, + FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS /* R8A779x only */, + FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE /* R8A779x only */, + FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE /* R8A779x only */, FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B, - FN_DU1_DISP, FN_QPOLA, - FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, + FN_DU1_DISP, FN_QPOLA /* R8A779x only */, + FN_DU1_CDE, FN_QPOLB /* R8A779x only */, FN_PWM4_B, FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D, FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D, FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D, FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D, FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, - FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL, - FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, + FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C /* R8A779x only */, + FN_I2C4_SCL, FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, /* IPSR10 */ - FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA, + FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C /* R8A779x only */, + FN_I2C4_SDA, FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, - FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B, + FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C /* R8A779x only */, + FN_I2C3_SCL_B, FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, - FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B, + FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C /* R8A779x only */, + FN_I2C3_SDA_B, FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, - FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C, + FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C /* R8A779x only */, FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D, - FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D, + FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C /* R8A779x only */, + FN_FMCLK_D /* R8A779x only */, FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, - FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, - FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, - FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B, + FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D /* R8A779x only */, + FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D /* R8A779x only */, + FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B /* R8A779x only */, FN_TS_SDATA0_C, FN_ATACS11_N, - FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, + FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B /* R8A779x only */, FN_TS_SCK0_C, FN_ATAG1_N, - FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C, - FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C, - FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D, + FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B /* R8A779x only */, FN_TS_SDEN0_C, + FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B /* R8A779x only */, + FN_TS_SPSYNC0_C, + FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B /* R8A779x only */, FN_TX0_C, + FN_I2C1_SCL_D, /* IPSR11 */ - FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_I2C1_SDA_D, - FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B, - FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E, + FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B /* R8A779x only */, FN_RX0_C, + FN_I2C1_SDA_D, + FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B /* R8A779x only */, FN_TX1_C, + FN_I2C4_SCL_B, + FN_VI0_R7, FN_GLO_RFON_B /* R8A779x only */, FN_RX1_C, FN_CAN0_RX_E, FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D, FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B, FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B, @@ -327,31 +356,35 @@ enum { FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B, FN_CAN1_TX_C, FN_MSIOF1_TXD_E, FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B, - FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, - FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, - FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, - FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D, - FN_ADIDATA_B, FN_MSIOF0_SYNC_C, - FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D, - FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C, + FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C /* R8A779x only */, + FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C /* R8A779x only */, + FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C /* R8A779x only */, + FN_STP_IVCXO27_0 /* R8A779x only */, FN_AVB_TXD7, FN_SCIFB2_TXD_D, + FN_ADIDATA_B /* R8A779x only */, FN_MSIOF0_SYNC_C, + FN_STP_ISCLK_0 /* R8A779x only */, FN_AVB_TX_EN, FN_SCIFB2_RXD_D, + FN_ADICS_SAMP_B /* R8A779x only */, FN_MSIOF0_SCK_C, /* IPSR13 */ - FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C, - FN_ADICLK_B, FN_MSIOF0_SS1_C, - FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C, - FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C, - FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B, - FN_ADICHS2_B, FN_MSIOF0_TXD_C, + FN_STP_ISD_0 /* R8A779x only */, FN_AVB_TX_ER, FN_SCIFB2_SCK_C, + FN_ADICLK_B /* R8A779x only */, FN_MSIOF0_SS1_C, + FN_STP_ISEN_0 /* R8A779x only */, FN_AVB_TX_CLK, + FN_ADICHS0_B /* R8A779x only */, FN_MSIOF0_SS2_C, + FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B /* R8A779x only */, + FN_MSIOF0_RXD_C, + FN_STP_OPWM_0 /* R8A779x only */, FN_AVB_GTX_CLK, FN_PWM0_B, + FN_ADICHS2_B /* R8A779x only */, FN_MSIOF0_TXD_C, FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B, FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B, FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B, - FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F, + FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B /* R8A779x only */, FN_CAN0_RX_F, FN_SCIFA5_TXD_B, FN_TX3_C, - FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F, + FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B /* R8A779x only */, FN_CAN0_TX_F, FN_SCIFA5_RXD_B, FN_RX3_C, - FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B, - FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B, - FN_SD1_DATA3, FN_IERX_B, + FN_SD1_CMD, FN_REMOCON_B /* R8A779x only */, + FN_SD1_DATA0, FN_SPEEDIN_B /* R8A779x only */, + FN_SD1_DATA1, FN_IETX_B /* R8A779x only */, + FN_SD1_DATA2, FN_IECLK_B /* R8A779x only */, + FN_SD1_DATA3, FN_IERX_B /* R8A779x only */, FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C, /* IPSR14 */ @@ -361,38 +394,53 @@ enum { FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3, FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C, FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C, - FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B, - FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B, - FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B, - FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B, - FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E, + FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA /* R8A779x only */, FN_VI1_CLK_C, + FN_VI1_G0_B, + FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP /* R8A779x only */, + FN_VI1_CLKENB_C, FN_VI1_G1_B, + FN_MSIOF0_TXD, FN_ADICLK /* R8A779x only */, FN_VI1_FIELD_C, + FN_VI1_G2_B, + FN_MSIOF0_RXD, FN_ADICHS0 /* R8A779x only */, FN_VI1_DATA0_C, + FN_VI1_G3_B, + FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1 /* R8A779x only */, FN_TX0_E, FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B, - FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E, + FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2 /* R8A779x only */, FN_RX0_E, FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B, /* IPSR15 */ - FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, - FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, - FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, - FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B, + FN_SIM0_RST /* R8A779x only */, FN_IETX /* R8A779x only */, + FN_CAN1_TX_D, + FN_SIM0_CLK /* R8A779x only */, FN_IECLK /* R8A779x only */, + FN_CAN_CLK_C, + FN_SIM0_D /* R8A779x only */, FN_IERX /* R8A779x only */, FN_CAN1_RX_D, + FN_GPS_CLK /* R8A779x only */, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B, FN_PWM5_B, FN_SCIFA3_TXD_C, - FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5, + FN_GPS_SIGN /* R8A779x only */, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5, FN_VI1_G6_B, FN_SCIFA3_RXD_C, - FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6, + FN_GPS_MAG /* R8A779x only */, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6, FN_VI1_G7_B, FN_SCIFA3_SCK_C, - FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C, - FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C, - FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK, + FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C /* R8A779x only */, FN_TCLK1, + FN_VI1_DATA1_C, + FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C /* R8A779x only */, + FN_VI1_DATA2_C, + FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C /* R8A779x only */, FN_CAN_CLK, FN_TCLK2, FN_VI1_DATA3_C, - FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C, - FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C, + FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C /* R8A779x only */, FN_CAN0_RX_B, + FN_VI1_DATA4_C, + FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C /* R8A779x only */, FN_CAN0_TX_B, + FN_VI1_DATA5_C, /* IPSR16 */ - FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C, - FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C, - FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C, - FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B, - FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B, + FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C /* R8A779x only */, + FN_VI1_DATA6_C, + FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C /* R8A779x only */, + FN_VI1_DATA7_C, + FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK /* R8A779x only */, + FN_GLO_RFON_C /* R8A779x only */, + FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG /* R8A779x only */, + FN_CAN1_TX_B, + FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT /* R8A779x only */, + FN_CAN1_RX_B, /* MOD_SEL */ FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, @@ -422,12 +470,14 @@ enum { FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_ADG_0, FN_SEL_ADG_1, - FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4, + /* R8A779x only */ FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, + FN_SEL_FM_4, FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, - FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, + /* R8A779x only */ FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, + FN_SEL_GPS_3, FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, - FN_SEL_SIM_0, FN_SEL_SIM_1, + /* R8A779x only */ FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, /* MOD_SEL3 */ @@ -438,7 +488,7 @@ enum { FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2, FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, - FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, + /* R8A779x only */ FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, FN_SEL_MMC_0, FN_SEL_MMC_1, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, @@ -451,16 +501,16 @@ enum { FN_SEL_SOF1_4, FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, - FN_SEL_RAD_0, FN_SEL_RAD_1, - FN_SEL_RCN_0, FN_SEL_RCN_1, - FN_SEL_RSP_0, FN_SEL_RSP_1, + /* R8A779x only */ FN_SEL_RAD_0, FN_SEL_RAD_1, + /* R8A779x only */ FN_SEL_RCN_0, FN_SEL_RCN_1, + /* R8A779x only */ FN_SEL_RSP_0, FN_SEL_RSP_1, FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3, FN_SEL_SCIF2_4, FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3, FN_SEL_SOF2_4, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI0_0, FN_SEL_SSI0_1, - FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, + /* R8A779x only */ FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, PINMUX_FUNCTION_END, PINMUX_MARK_BEGIN, @@ -493,11 +543,15 @@ enum { A9_MARK, MSIOF1_SS2_MARK, I2C0_SDA_MARK, A10_MARK, MSIOF1_TXD_MARK, MSIOF1_TXD_D_MARK, A11_MARK, MSIOF1_RXD_MARK, I2C3_SCL_D_MARK, MSIOF1_RXD_D_MARK, - A12_MARK, FMCLK_MARK, I2C3_SDA_D_MARK, MSIOF1_SCK_D_MARK, - A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK, MSIOF1_SS1_D_MARK, - A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK, FMIN_C_MARK, MSIOF1_SYNC_D_MARK, - A15_MARK, BPFCLK_C_MARK, - A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK, SCIFA1_SCK_B_MARK, + A12_MARK, FMCLK_MARK /* R8A779x only */, I2C3_SDA_D_MARK, + MSIOF1_SCK_D_MARK, + A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK /* R8A779x only */, + MSIOF1_SS1_D_MARK, + A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK /* R8A779x only */, + FMIN_C_MARK /* R8A779x only */, MSIOF1_SYNC_D_MARK, + A15_MARK, BPFCLK_C_MARK /* R8A779x only */, + A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK /* R8A779x only */, + SCIFA1_SCK_B_MARK, A17_MARK, DACK2_B_MARK, I2C0_SDA_C_MARK, A18_MARK, DREQ1_MARK, SCIFA1_RXD_C_MARK, SCIFB1_RXD_C_MARK, @@ -506,8 +560,10 @@ enum { SCIFB1_TXD_C_MARK, SCIFB1_SCK_B_MARK, A20_MARK, SPCLK_MARK, A21_MARK, ATAWR0_N_B_MARK, MOSI_IO0_MARK, - A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK, TX0_MARK, SCIFA0_TXD_MARK, - A23_MARK, IO2_MARK, BPFCLK_B_MARK, RX0_MARK, SCIFA0_RXD_MARK, + A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK /* R8A779x only */, TX0_MARK, + SCIFA0_TXD_MARK, + A23_MARK, IO2_MARK, BPFCLK_B_MARK /* R8A779x only */, RX0_MARK, + SCIFA0_RXD_MARK, A24_MARK, DREQ2_MARK, IO3_MARK, TX1_MARK, SCIFA1_TXD_MARK, A25_MARK, DACK2_MARK, SSL_MARK, DREQ1_C_MARK, RX1_MARK, SCIFA1_RXD_MARK, @@ -524,15 +580,15 @@ enum { SCIFB1_RXD_B_MARK, PWM1_MARK, TPU_TO1_MARK, BS_N_MARK, ATACS10_N_MARK, MSIOF2_SS2_MARK, HTX1_B_MARK, SCIFB1_TXD_B_MARK, PWM2_MARK, TPU_TO2_MARK, - RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK, + RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK /* R8A779x only */, SCIFB0_RXD_B_MARK, DREQ1_D_MARK, WE0_N_MARK, HCTS2_N_B_MARK, SCIFB0_TXD_B_MARK, WE1_N_MARK, ATARD0_N_B_MARK, HTX2_B_MARK, SCIFB0_RTS_N_B_MARK, EX_WAIT0_MARK, HRTS2_N_B_MARK, SCIFB0_CTS_N_B_MARK, DREQ0_MARK, PWM3_MARK, TPU_TO3_MARK, - DACK0_MARK, DRACK0_MARK, REMOCON_MARK, - SPEEDIN_MARK, HSCK0_C_MARK, HSCK2_C_MARK, SCIFB0_SCK_B_MARK, - SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK, + DACK0_MARK, DRACK0_MARK, REMOCON_MARK /* R8A779x only */, + SPEEDIN_MARK /* R8A779x only */, HSCK0_C_MARK, HSCK2_C_MARK, + SCIFB0_SCK_B_MARK, SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK, SSI_SCK0129_MARK, HRX0_C_MARK, HRX2_C_MARK, SCIFB0_RXD_C_MARK, SCIFB2_RXD_C_MARK, SSI_WS0129_MARK, HTX0_C_MARK, HTX2_C_MARK, @@ -541,149 +597,166 @@ enum { /* IPSR4 */ SSI_SDATA0_MARK, I2C0_SCL_B_MARK, IIC0_SCL_B_MARK, MSIOF2_SCK_C_MARK, SSI_SCK1_MARK, I2C0_SDA_B_MARK, IIC0_SDA_B_MARK, - MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK, + MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK /* R8A779x only */, SSI_WS1_MARK, I2C1_SCL_B_MARK, IIC1_SCL_B_MARK, - MSIOF2_TXD_C_MARK, GLO_I1_D_MARK, + MSIOF2_TXD_C_MARK, GLO_I1_D_MARK /* R8A779x only */, SSI_SDATA1_MARK, I2C1_SDA_B_MARK, IIC1_SDA_B_MARK, MSIOF2_RXD_C_MARK, - SSI_SCK2_MARK, I2C2_SCL_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK, - HSCK1_E_MARK, - SSI_WS2_MARK, I2C2_SDA_MARK, GPS_SIGN_B_MARK, RX2_E_MARK, - GLO_Q1_D_MARK, HCTS1_N_E_MARK, - SSI_SDATA2_MARK, GPS_MAG_B_MARK, TX2_E_MARK, HRTS1_N_E_MARK, + SSI_SCK2_MARK, I2C2_SCL_MARK, GPS_CLK_B_MARK /* R8A779x only */, + GLO_Q0_D_MARK /* R8A779x only */, HSCK1_E_MARK, + SSI_WS2_MARK, I2C2_SDA_MARK, GPS_SIGN_B_MARK /* R8A779x only */, + RX2_E_MARK, GLO_Q1_D_MARK /* R8A779x only */, HCTS1_N_E_MARK, + SSI_SDATA2_MARK, GPS_MAG_B_MARK /* R8A779x only */, TX2_E_MARK, + HRTS1_N_E_MARK, SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK, - SSI_SCK4_MARK, GLO_SS_D_MARK, - SSI_WS4_MARK, GLO_RFON_D_MARK, + SSI_SCK4_MARK, GLO_SS_D_MARK /* R8A779x only */, + SSI_WS4_MARK, GLO_RFON_D_MARK /* R8A779x only */, SSI_SDATA4_MARK, MSIOF2_SCK_D_MARK, - SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK, GLO_I0_MARK, - MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK, + SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK, + GLO_I0_MARK /* R8A779x only */, MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK, /* IPSR5 */ - SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK, GLO_I1_MARK, - MSIOF2_TXD_D_MARK, VI1_R3_B_MARK, - SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK, GLO_Q0_MARK, - MSIOF2_SS1_D_MARK, VI1_R4_B_MARK, - SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK, GLO_Q1_MARK, - MSIOF2_RXD_D_MARK, VI1_R5_B_MARK, - SSI_WS6_MARK, GLO_SCLK_MARK, MSIOF2_SS2_D_MARK, VI1_R6_B_MARK, - SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK, GLO_SDATA_MARK, VI1_R7_B_MARK, - SSI_SCK78_MARK, STP_ISCLK_0_B_MARK, GLO_SS_MARK, - SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK, GLO_RFON_MARK, - SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK, - SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK, - SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK, - SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK, GLO_SDATA_D_MARK, + SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK, + GLO_I1_MARK /* R8A779x only */, MSIOF2_TXD_D_MARK, VI1_R3_B_MARK, + SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK, + GLO_Q0_MARK /* R8A779x only */, MSIOF2_SS1_D_MARK, VI1_R4_B_MARK, + SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK, + GLO_Q1_MARK /* R8A779x only */, MSIOF2_RXD_D_MARK, VI1_R5_B_MARK, + SSI_WS6_MARK, GLO_SCLK_MARK /* R8A779x only */, MSIOF2_SS2_D_MARK, + VI1_R6_B_MARK, + SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK /* R8A779x only */, + GLO_SDATA_MARK /* R8A779x only */, VI1_R7_B_MARK, + SSI_SCK78_MARK, STP_ISCLK_0_B_MARK /* R8A779x only */, + GLO_SS_MARK /* R8A779x only */, + SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK /* R8A779x only */, + GLO_RFON_MARK /* R8A779x only */, + SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK /* R8A779x only */, + SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK /* R8A779x only */, + SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK /* R8A779x only */, + SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK, + GLO_SDATA_D_MARK /* R8A779x only */, SSI_SDATA9_MARK, RX3_D_MARK, CAN0_RX_D_MARK, /* IPSR6 */ - AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK, - SCIF_CLK_MARK, DVC_MUTE_MARK, BPFCLK_E_MARK, + AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK /* R8A779x only */, + MSIOF1_SCK_B_MARK, SCIF_CLK_MARK, DVC_MUTE_MARK, + BPFCLK_E_MARK /* R8A779x only */, AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK, - SCIFA2_RXD_MARK, FMIN_E_MARK, + SCIFA2_RXD_MARK, FMIN_E_MARK /* R8A779x only */, AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK, - IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK, - IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK, - IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK, - IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK, + IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK /* R8A779x only */, + IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK /* R8A779x only */, + IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK /* R8A779x only */, + IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK, + INTC_IRQ3_N_MARK /* R8A779x only */, IRQ4_MARK, HRX1_C_MARK, I2C4_SDA_C_MARK, - MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK, + MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK /* R8A779x only */, IRQ5_MARK, HTX1_C_MARK, I2C1_SCL_E_MARK, MSIOF2_SCK_E_MARK, IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK, I2C1_SDA_E_MARK, MSIOF2_SYNC_E_MARK, IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK, - GPS_CLK_C_MARK, GPS_CLK_D_MARK, + GPS_CLK_C_MARK /* R8A779x only */, GPS_CLK_D_MARK /* R8A779x only */, IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK, - GPS_SIGN_C_MARK, GPS_SIGN_D_MARK, + GPS_SIGN_C_MARK /* R8A779x only */, GPS_SIGN_D_MARK /* R8A779x only */, /* IPSR7 */ - IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK, GPS_MAG_C_MARK, - SCIF_CLK_B_MARK, GPS_MAG_D_MARK, - DU1_DR0_MARK, LCDOUT0_MARK, VI1_DATA0_B_MARK, TX0_B_MARK, - SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK, - DU1_DR1_MARK, LCDOUT1_MARK, VI1_DATA1_B_MARK, RX0_B_MARK, - SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK, - DU1_DR2_MARK, LCDOUT2_MARK, SSI_SCK0129_B_MARK, - DU1_DR3_MARK, LCDOUT3_MARK, SSI_WS0129_B_MARK, - DU1_DR4_MARK, LCDOUT4_MARK, SSI_SDATA0_B_MARK, - DU1_DR5_MARK, LCDOUT5_MARK, SSI_SCK1_B_MARK, - DU1_DR6_MARK, LCDOUT6_MARK, SSI_WS1_B_MARK, - DU1_DR7_MARK, LCDOUT7_MARK, SSI_SDATA1_B_MARK, - DU1_DG0_MARK, LCDOUT8_MARK, VI1_DATA2_B_MARK, TX1_B_MARK, - SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK, - DU1_DG1_MARK, LCDOUT9_MARK, VI1_DATA3_B_MARK, RX1_B_MARK, - SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK, - DU1_DG2_MARK, LCDOUT10_MARK, VI1_DATA4_B_MARK, SCIF1_SCK_B_MARK, - SCIFA1_SCK_MARK, SSI_SCK78_B_MARK, + IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK, + GPS_MAG_C_MARK /* R8A779x only */, SCIF_CLK_B_MARK, + GPS_MAG_D_MARK /* R8A779x only */, + DU1_DR0_MARK, LCDOUT0_MARK /* R8A779x only */, VI1_DATA0_B_MARK, + TX0_B_MARK, SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK, + DU1_DR1_MARK, LCDOUT1_MARK /* R8A779x only */, VI1_DATA1_B_MARK, + RX0_B_MARK, SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK, + DU1_DR2_MARK, LCDOUT2_MARK /* R8A779x only */, SSI_SCK0129_B_MARK, + DU1_DR3_MARK, LCDOUT3_MARK /* R8A779x only */, SSI_WS0129_B_MARK, + DU1_DR4_MARK, LCDOUT4_MARK /* R8A779x only */, SSI_SDATA0_B_MARK, + DU1_DR5_MARK, LCDOUT5_MARK /* R8A779x only */, SSI_SCK1_B_MARK, + DU1_DR6_MARK, LCDOUT6_MARK /* R8A779x only */, SSI_WS1_B_MARK, + DU1_DR7_MARK, LCDOUT7_MARK /* R8A779x only */, SSI_SDATA1_B_MARK, + DU1_DG0_MARK, LCDOUT8_MARK /* R8A779x only */, VI1_DATA2_B_MARK, + TX1_B_MARK, SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK, + DU1_DG1_MARK, LCDOUT9_MARK /* R8A779x only */, VI1_DATA3_B_MARK, + RX1_B_MARK, SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK, + DU1_DG2_MARK, LCDOUT10_MARK /* R8A779x only */, VI1_DATA4_B_MARK, + SCIF1_SCK_B_MARK, SCIFA1_SCK_MARK, SSI_SCK78_B_MARK, /* IPSR8 */ - DU1_DG3_MARK, LCDOUT11_MARK, VI1_DATA5_B_MARK, SSI_WS78_B_MARK, - DU1_DG4_MARK, LCDOUT12_MARK, VI1_DATA6_B_MARK, HRX0_B_MARK, - SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK, - DU1_DG5_MARK, LCDOUT13_MARK, VI1_DATA7_B_MARK, HCTS0_N_B_MARK, - SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK, - DU1_DG6_MARK, LCDOUT14_MARK, HRTS0_N_B_MARK, + DU1_DG3_MARK, LCDOUT11_MARK /* R8A779x only */, VI1_DATA5_B_MARK, + SSI_WS78_B_MARK, + DU1_DG4_MARK, LCDOUT12_MARK /* R8A779x only */, VI1_DATA6_B_MARK, + HRX0_B_MARK, SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK, + DU1_DG5_MARK, LCDOUT13_MARK /* R8A779x only */, VI1_DATA7_B_MARK, + HCTS0_N_B_MARK, SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK, + DU1_DG6_MARK, LCDOUT14_MARK /* R8A779x only */, HRTS0_N_B_MARK, SCIFB2_CTS_N_B_MARK, SSI_SCK9_B_MARK, - DU1_DG7_MARK, LCDOUT15_MARK, HTX0_B_MARK, + DU1_DG7_MARK, LCDOUT15_MARK /* R8A779x only */, HTX0_B_MARK, SCIFB2_RTS_N_B_MARK, SSI_WS9_B_MARK, - DU1_DB0_MARK, LCDOUT16_MARK, VI1_CLK_B_MARK, TX2_B_MARK, - SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK, - DU1_DB1_MARK, LCDOUT17_MARK, VI1_HSYNC_N_B_MARK, RX2_B_MARK, - SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK, - DU1_DB2_MARK, LCDOUT18_MARK, VI1_VSYNC_N_B_MARK, SCIF2_SCK_B_MARK, - SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK, - DU1_DB3_MARK, LCDOUT19_MARK, VI1_CLKENB_B_MARK, - DU1_DB4_MARK, LCDOUT20_MARK, VI1_FIELD_B_MARK, CAN1_RX_MARK, - DU1_DB5_MARK, LCDOUT21_MARK, TX3_MARK, SCIFA3_TXD_MARK, CAN1_TX_MARK, + DU1_DB0_MARK, LCDOUT16_MARK /* R8A779x only */, VI1_CLK_B_MARK, + TX2_B_MARK, SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK, + DU1_DB1_MARK, LCDOUT17_MARK /* R8A779x only */, VI1_HSYNC_N_B_MARK, + RX2_B_MARK, SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK, + DU1_DB2_MARK, LCDOUT18_MARK /* R8A779x only */, VI1_VSYNC_N_B_MARK, + SCIF2_SCK_B_MARK, SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK, + DU1_DB3_MARK, LCDOUT19_MARK /* R8A779x only */, VI1_CLKENB_B_MARK, + DU1_DB4_MARK, LCDOUT20_MARK /* R8A779x only */, VI1_FIELD_B_MARK, + CAN1_RX_MARK, + DU1_DB5_MARK, LCDOUT21_MARK /* R8A779x only */, TX3_MARK, + SCIFA3_TXD_MARK, CAN1_TX_MARK, /* IPSR9 */ - DU1_DB6_MARK, LCDOUT22_MARK, I2C3_SCL_C_MARK, RX3_MARK, SCIFA3_RXD_MARK, - DU1_DB7_MARK, LCDOUT23_MARK, I2C3_SDA_C_MARK, + DU1_DB6_MARK, LCDOUT22_MARK /* R8A779x only */, I2C3_SCL_C_MARK, + RX3_MARK, SCIFA3_RXD_MARK, + DU1_DB7_MARK, LCDOUT23_MARK /* R8A779x only */, I2C3_SDA_C_MARK, SCIF3_SCK_MARK, SCIFA3_SCK_MARK, - DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK, - DU1_DOTCLKOUT0_MARK, QCLK_MARK, - DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, CAN0_TX_MARK, + DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK /* R8A779x only */, + DU1_DOTCLKOUT0_MARK, QCLK_MARK /* R8A779x only */, + DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK /* R8A779x only */, CAN0_TX_MARK, TX3_B_MARK, I2C2_SCL_B_MARK, PWM4_MARK, - DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK, - DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK, - DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, + DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK /* R8A779x only */, + DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK /* R8A779x only */, + DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK /* R8A779x only */, CAN0_RX_MARK, RX3_B_MARK, I2C2_SDA_B_MARK, - DU1_DISP_MARK, QPOLA_MARK, - DU1_CDE_MARK, QPOLB_MARK, PWM4_B_MARK, + DU1_DISP_MARK, QPOLA_MARK /* R8A779x only */, + DU1_CDE_MARK, QPOLB_MARK /* R8A779x only */, PWM4_B_MARK, VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK, VI0_FIELD_MARK, RX4_MARK, SCIFA4_RXD_MARK, TS_SCK0_D_MARK, VI0_HSYNC_N_MARK, TX5_MARK, SCIFA5_TXD_MARK, TS_SDEN0_D_MARK, VI0_VSYNC_N_MARK, RX5_MARK, SCIFA5_RXD_MARK, TS_SPSYNC0_D_MARK, VI0_DATA3_VI0_B3_MARK, SCIF3_SCK_B_MARK, SCIFA3_SCK_B_MARK, - VI0_G0_MARK, IIC1_SCL_MARK, STP_IVCXO27_0_C_MARK, I2C4_SCL_MARK, - HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK, + VI0_G0_MARK, IIC1_SCL_MARK, STP_IVCXO27_0_C_MARK /* R8A779x only */, + I2C4_SCL_MARK, HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK, /* IPSR10 */ - VI0_G1_MARK, IIC1_SDA_MARK, STP_ISCLK_0_C_MARK, I2C4_SDA_MARK, - HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK, - VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, I2C3_SCL_B_MARK, - HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK, - VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, I2C3_SDA_B_MARK, - HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK, - VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK, + VI0_G1_MARK, IIC1_SDA_MARK, STP_ISCLK_0_C_MARK /* R8A779x only */, + I2C4_SDA_MARK, HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK, + VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK /* R8A779x only */, + I2C3_SCL_B_MARK, HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK, + VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK /* R8A779x only */, + I2C3_SDA_B_MARK, HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK, + VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK /* R8A779x only */, HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK, - VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK, FMCLK_D_MARK, - CAN0_TX_E_MARK, HTX1_D_MARK, SCIFB0_TXD_D_MARK, - VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK, - VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK, - VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK, + VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK, + FMCLK_D_MARK /* R8A779x only */, CAN0_TX_E_MARK, HTX1_D_MARK, + SCIFB0_TXD_D_MARK, + VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK /* R8A779x only */, + VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK /* R8A779x only */, + VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK /* R8A779x only */, TS_SDATA0_C_MARK, ATACS11_N_MARK, - VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK, + VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK /* R8A779x only */, TS_SCK0_C_MARK, ATAG1_N_MARK, - VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK, TS_SDEN0_C_MARK, - VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK, TS_SPSYNC0_C_MARK, - VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK, - I2C1_SCL_D_MARK, + VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK /* R8A779x only */, + TS_SDEN0_C_MARK, + VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK /* R8A779x only */, + TS_SPSYNC0_C_MARK, + VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK /* R8A779x only */, + TX0_C_MARK, I2C1_SCL_D_MARK, /* IPSR11 */ - VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, - I2C1_SDA_D_MARK, - VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, I2C4_SCL_B_MARK, - VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK, - I2C4_SDA_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK, + VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK /* R8A779x only */, + RX0_C_MARK, I2C1_SDA_D_MARK, + VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK /* R8A779x only */, + TX1_C_MARK, I2C4_SCL_B_MARK, + VI0_R7_MARK, GLO_RFON_B_MARK /* R8A779x only */, RX1_C_MARK, + CAN0_RX_E_MARK, I2C4_SDA_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK, VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK, TX4_B_MARK, SCIFA4_TXD_B_MARK, VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK, @@ -710,31 +783,35 @@ enum { ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK, CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK, ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK, - ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK, - ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK, - ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK, - STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK, - ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK, - STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK, - ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK, + ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK /* R8A779x only */, + ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK /* R8A779x only */, + ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK /* R8A779x only */, + STP_IVCXO27_0_MARK /* R8A779x only */, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK, + ADIDATA_B_MARK /* R8A779x only */, MSIOF0_SYNC_C_MARK, + STP_ISCLK_0_MARK /* R8A779x only */, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK, + ADICS_SAMP_B_MARK /* R8A779x only */, MSIOF0_SCK_C_MARK, /* IPSR13 */ - STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK, - ADICLK_B_MARK, MSIOF0_SS1_C_MARK, - STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK, - STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK, - STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK, - ADICHS2_B_MARK, MSIOF0_TXD_C_MARK, + STP_ISD_0_MARK /* R8A779x only */, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK, + ADICLK_B_MARK /* R8A779x only */, MSIOF0_SS1_C_MARK, + STP_ISEN_0_MARK /* R8A779x only */, AVB_TX_CLK_MARK, + ADICHS0_B_MARK /* R8A779x only */, MSIOF0_SS2_C_MARK, + STP_ISSYNC_0_MARK /* R8A779x only */, AVB_COL_MARK, + ADICHS1_B_MARK /* R8A779x only */, MSIOF0_RXD_C_MARK, + STP_OPWM_0_MARK /* R8A779x only */, AVB_GTX_CLK_MARK, PWM0_B_MARK, + ADICHS2_B_MARK /* R8A779x only */, MSIOF0_TXD_C_MARK, SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK, SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK, SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK, - SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK, - SCIFA5_TXD_B_MARK, TX3_C_MARK, - SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK, - SCIFA5_RXD_B_MARK, RX3_C_MARK, - SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK, - SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK, - SD1_DATA3_MARK, IERX_B_MARK, + SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK /* R8A779x only */, + CAN0_RX_F_MARK, SCIFA5_TXD_B_MARK, TX3_C_MARK, + SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK /* R8A779x only */, + CAN0_TX_F_MARK, SCIFA5_RXD_B_MARK, RX3_C_MARK, + SD1_CMD_MARK, REMOCON_B_MARK /* R8A779x only */, + SD1_DATA0_MARK, SPEEDIN_B_MARK /* R8A779x only */, + SD1_DATA1_MARK, IETX_B_MARK /* R8A779x only */, + SD1_DATA2_MARK, IECLK_B_MARK /* R8A779x only */, + SD1_DATA3_MARK, IERX_B_MARK /* R8A779x only */, SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, I2C1_SCL_C_MARK, /* IPSR14 */ @@ -746,45 +823,55 @@ enum { SCIFA5_TXD_C_MARK, SD2_WP_MARK, MMC_D5_MARK, IIC1_SDA_C_MARK, RX5_B_MARK, SCIFA5_RXD_C_MARK, - MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK, + MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK /* R8A779x only */, VI1_CLK_C_MARK, VI1_G0_B_MARK, - MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK, + MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK /* R8A779x only */, VI1_CLKENB_C_MARK, VI1_G1_B_MARK, - MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK, - MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK, - MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK, - VI1_HSYNC_N_C_MARK, IIC0_SCL_C_MARK, VI1_G4_B_MARK, - MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK, - VI1_VSYNC_N_C_MARK, IIC0_SDA_C_MARK, VI1_G5_B_MARK, + MSIOF0_TXD_MARK, ADICLK_MARK /* R8A779x only */, VI1_FIELD_C_MARK, + VI1_G2_B_MARK, + MSIOF0_RXD_MARK, ADICHS0_MARK /* R8A779x only */, VI1_DATA0_C_MARK, + VI1_G3_B_MARK, + MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK /* R8A779x only */, + TX0_E_MARK, VI1_HSYNC_N_C_MARK, IIC0_SCL_C_MARK, VI1_G4_B_MARK, + MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK /* R8A779x only */, + RX0_E_MARK, VI1_VSYNC_N_C_MARK, IIC0_SDA_C_MARK, VI1_G5_B_MARK, /* IPSR15 */ - SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK, - SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK, - SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK, - GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK, + SIM0_RST_MARK /* R8A779x only */, IETX_MARK /* R8A779x only */, + CAN1_TX_D_MARK, + SIM0_CLK_MARK /* R8A779x only */, IECLK_MARK /* R8A779x only */, + CAN_CLK_C_MARK, + SIM0_D_MARK /* R8A779x only */, IERX_MARK /* R8A779x only */, + CAN1_RX_D_MARK, + GPS_CLK_MARK /* R8A779x only */, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK, PWM5_B_MARK, SCIFA3_TXD_C_MARK, - GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK, - VI1_G6_B_MARK, SCIFA3_RXD_C_MARK, - GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK, - VI1_G7_B_MARK, SCIFA3_SCK_C_MARK, - HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK, + GPS_SIGN_MARK /* R8A779x only */, TX4_C_MARK, SCIFA4_TXD_C_MARK, + PWM5_MARK, VI1_G6_B_MARK, SCIFA3_RXD_C_MARK, + GPS_MAG_MARK /* R8A779x only */, RX4_C_MARK, SCIFA4_RXD_C_MARK, + PWM6_MARK, VI1_G7_B_MARK, SCIFA3_SCK_C_MARK, + HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK /* R8A779x only */, TCLK1_MARK, VI1_DATA1_C_MARK, - HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK, - HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK, - TCLK2_MARK, VI1_DATA3_C_MARK, - HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK, + HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK /* R8A779x only */, + VI1_DATA2_C_MARK, + HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK /* R8A779x only */, + CAN_CLK_MARK, TCLK2_MARK, VI1_DATA3_C_MARK, + HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK /* R8A779x only */, CAN0_RX_B_MARK, VI1_DATA4_C_MARK, - HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK, + HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK /* R8A779x only */, CAN0_TX_B_MARK, VI1_DATA5_C_MARK, /* IPSR16 */ HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK, - GLO_SDATA_C_MARK, VI1_DATA6_C_MARK, + GLO_SDATA_C_MARK /* R8A779x only */, VI1_DATA6_C_MARK, HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK, - GLO_SS_C_MARK, VI1_DATA7_C_MARK, - HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CLK_MARK, GLO_RFON_C_MARK, - HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK, - HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK, + GLO_SS_C_MARK /* R8A779x only */, VI1_DATA7_C_MARK, + HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CLK_MARK /* R8A779x only */, + GLO_RFON_C_MARK /* R8A779x only */, + HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK /* R8A779x only */, + CAN1_TX_B_MARK, + HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK /* R8A779x only */, + CAN1_RX_B_MARK, + PINMUX_MARK_END, }; @@ -861,23 +948,23 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP1_10_8, I2C3_SCL_D, SEL_I2C3_3), PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3), PINMUX_IPSR_GPSR(IP1_13_11, A12), - PINMUX_IPSR_MSEL(IP1_13_11, FMCLK, SEL_FM_0), + PINMUX_IPSR_MSEL(IP1_13_11, FMCLK, SEL_FM_0), /* R8A779x only */ PINMUX_IPSR_MSEL(IP1_13_11, I2C3_SDA_D, SEL_I2C3_3), PINMUX_IPSR_MSEL(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3), PINMUX_IPSR_GPSR(IP1_16_14, A13), PINMUX_IPSR_MSEL(IP1_16_14, ATAG0_N_C, SEL_LBS_2), - PINMUX_IPSR_MSEL(IP1_16_14, BPFCLK, SEL_FM_0), + PINMUX_IPSR_MSEL(IP1_16_14, BPFCLK, SEL_FM_0), /* R8A779x only */ PINMUX_IPSR_MSEL(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3), PINMUX_IPSR_GPSR(IP1_19_17, A14), PINMUX_IPSR_MSEL(IP1_19_17, ATADIR0_N_C, SEL_LBS_2), - PINMUX_IPSR_MSEL(IP1_19_17, FMIN, SEL_FM_0), - PINMUX_IPSR_MSEL(IP1_19_17, FMIN_C, SEL_FM_2), + PINMUX_IPSR_MSEL(IP1_19_17, FMIN, SEL_FM_0), /* R8A779x only */ + PINMUX_IPSR_MSEL(IP1_19_17, FMIN_C, SEL_FM_2), /* R8A779x only */ PINMUX_IPSR_MSEL(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3), PINMUX_IPSR_GPSR(IP1_22_20, A15), - PINMUX_IPSR_MSEL(IP1_22_20, BPFCLK_C, SEL_FM_2), + PINMUX_IPSR_MSEL(IP1_22_20, BPFCLK_C, SEL_FM_2), /* R8A779x only */ PINMUX_IPSR_GPSR(IP1_25_23, A16), PINMUX_IPSR_MSEL(IP1_25_23, DREQ2_B, SEL_LBS_1), - PINMUX_IPSR_MSEL(IP1_25_23, FMCLK_C, SEL_FM_2), + PINMUX_IPSR_MSEL(IP1_25_23, FMCLK_C, SEL_FM_2), /* R8A779x only */ PINMUX_IPSR_MSEL(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1), PINMUX_IPSR_GPSR(IP1_28_26, A17), PINMUX_IPSR_MSEL(IP1_28_26, DACK2_B, SEL_LBS_1), @@ -900,12 +987,12 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP2_6_5, MOSI_IO0, SEL_QSP_0), PINMUX_IPSR_GPSR(IP2_9_7, A22), PINMUX_IPSR_MSEL(IP2_9_7, MISO_IO1, SEL_QSP_0), - PINMUX_IPSR_MSEL(IP2_9_7, FMCLK_B, SEL_FM_1), + PINMUX_IPSR_MSEL(IP2_9_7, FMCLK_B, SEL_FM_1), /* R8A779x only */ PINMUX_IPSR_MSEL(IP2_9_7, TX0, SEL_SCIF0_0), PINMUX_IPSR_MSEL(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0), PINMUX_IPSR_GPSR(IP2_12_10, A23), PINMUX_IPSR_MSEL(IP2_12_10, IO2, SEL_QSP_0), - PINMUX_IPSR_MSEL(IP2_12_10, BPFCLK_B, SEL_FM_1), + PINMUX_IPSR_MSEL(IP2_12_10, BPFCLK_B, SEL_FM_1), /* R8A779x only */ PINMUX_IPSR_MSEL(IP2_12_10, RX0, SEL_SCIF0_0), PINMUX_IPSR_MSEL(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0), PINMUX_IPSR_GPSR(IP2_15_13, A24), @@ -957,7 +1044,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP3_8_6, TPU_TO2), PINMUX_IPSR_GPSR(IP3_11_9, RD_WR_N), PINMUX_IPSR_MSEL(IP3_11_9, HRX2_B, SEL_HSCIF2_1), - PINMUX_IPSR_MSEL(IP3_11_9, FMIN_B, SEL_FM_1), + PINMUX_IPSR_MSEL(IP3_11_9, FMIN_B, SEL_FM_1), /* R8A779x only */ PINMUX_IPSR_MSEL(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1), PINMUX_IPSR_MSEL(IP3_11_9, DREQ1_D, SEL_LBS_1), PINMUX_IPSR_GPSR(IP3_13_12, WE0_N), @@ -975,8 +1062,8 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP3_19_18, TPU_TO3), PINMUX_IPSR_GPSR(IP3_21_20, DACK0), PINMUX_IPSR_GPSR(IP3_21_20, DRACK0), - PINMUX_IPSR_MSEL(IP3_21_20, REMOCON, SEL_RCN_0), - PINMUX_IPSR_MSEL(IP3_24_22, SPEEDIN, SEL_RSP_0), + PINMUX_IPSR_MSEL(IP3_21_20, REMOCON, SEL_RCN_0), /* R8A779x only */ + PINMUX_IPSR_MSEL(IP3_24_22, SPEEDIN, SEL_RSP_0), /* R8A779x only */ PINMUX_IPSR_MSEL(IP3_24_22, HSCK0_C, SEL_HSCIF0_2), PINMUX_IPSR_MSEL(IP3_24_22, HSCK2_C, SEL_HSCIF2_2), PINMUX_IPSR_MSEL(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1), @@ -1003,44 +1090,44 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP4_4_2, I2C0_SDA_B, SEL_I2C0_1), PINMUX_IPSR_MSEL(IP4_4_2, IIC0_SDA_B, SEL_IIC0_1), PINMUX_IPSR_MSEL(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2), - PINMUX_IPSR_MSEL(IP4_4_2, GLO_I0_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP4_4_2, GLO_I0_D, SEL_GPS_3), /* R8A779x only */ PINMUX_IPSR_MSEL(IP4_7_5, SSI_WS1, SEL_SSI1_0), PINMUX_IPSR_MSEL(IP4_7_5, I2C1_SCL_B, SEL_I2C1_1), PINMUX_IPSR_MSEL(IP4_7_5, IIC1_SCL_B, SEL_IIC1_1), PINMUX_IPSR_MSEL(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2), - PINMUX_IPSR_MSEL(IP4_7_5, GLO_I1_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP4_7_5, GLO_I1_D, SEL_GPS_3), /* R8A779x only */ PINMUX_IPSR_MSEL(IP4_9_8, SSI_SDATA1, SEL_SSI1_0), PINMUX_IPSR_MSEL(IP4_9_8, I2C1_SDA_B, SEL_I2C1_1), PINMUX_IPSR_MSEL(IP4_9_8, IIC1_SDA_B, SEL_IIC1_1), PINMUX_IPSR_MSEL(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2), PINMUX_IPSR_GPSR(IP4_12_10, SSI_SCK2), PINMUX_IPSR_MSEL(IP4_12_10, I2C2_SCL, SEL_I2C2_0), - PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1), - PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1), /* R8A779x only */ + PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3), /* R8A779x only */ PINMUX_IPSR_MSEL(IP4_12_10, HSCK1_E, SEL_HSCIF1_4), PINMUX_IPSR_GPSR(IP4_15_13, SSI_WS2), PINMUX_IPSR_MSEL(IP4_15_13, I2C2_SDA, SEL_I2C2_0), - PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1), /* R8A779x only */ PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4), - PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3), /* R8A779x only */ PINMUX_IPSR_MSEL(IP4_15_13, HCTS1_N_E, SEL_HSCIF1_4), PINMUX_IPSR_GPSR(IP4_18_16, SSI_SDATA2), - PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1), /* R8A779x only */ PINMUX_IPSR_MSEL(IP4_18_16, TX2_E, SEL_SCIF2_4), PINMUX_IPSR_MSEL(IP4_18_16, HRTS1_N_E, SEL_HSCIF1_4), PINMUX_IPSR_GPSR(IP4_19, SSI_SCK34), PINMUX_IPSR_GPSR(IP4_20, SSI_WS34), PINMUX_IPSR_GPSR(IP4_21, SSI_SDATA3), PINMUX_IPSR_GPSR(IP4_23_22, SSI_SCK4), - PINMUX_IPSR_MSEL(IP4_23_22, GLO_SS_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP4_23_22, GLO_SS_D, SEL_GPS_3), /* R8A779x only */ PINMUX_IPSR_GPSR(IP4_25_24, SSI_WS4), - PINMUX_IPSR_MSEL(IP4_25_24, GLO_RFON_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP4_25_24, GLO_RFON_D, SEL_GPS_3), /* R8A779x only */ PINMUX_IPSR_GPSR(IP4_27_26, SSI_SDATA4), PINMUX_IPSR_MSEL(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3), PINMUX_IPSR_GPSR(IP4_30_28, SSI_SCK5), PINMUX_IPSR_MSEL(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2), PINMUX_IPSR_MSEL(IP4_30_28, TS_SDATA0, SEL_TSIF0_0), - PINMUX_IPSR_MSEL(IP4_30_28, GLO_I0, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP4_30_28, GLO_I0, SEL_GPS_0), /* R8A779x only */ PINMUX_IPSR_MSEL(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3), PINMUX_IPSR_GPSR(IP4_30_28, VI1_R2_B), @@ -1048,88 +1135,88 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP5_2_0, SSI_WS5), PINMUX_IPSR_MSEL(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2), PINMUX_IPSR_MSEL(IP5_2_0, TS_SCK0, SEL_TSIF0_0), - PINMUX_IPSR_MSEL(IP5_2_0, GLO_I1, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP5_2_0, GLO_I1, SEL_GPS_0), /* R8A779x only */ PINMUX_IPSR_MSEL(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3), PINMUX_IPSR_GPSR(IP5_2_0, VI1_R3_B), PINMUX_IPSR_GPSR(IP5_5_3, SSI_SDATA5), PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2), PINMUX_IPSR_MSEL(IP5_5_3, TS_SDEN0, SEL_TSIF0_0), - PINMUX_IPSR_MSEL(IP5_5_3, GLO_Q0, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP5_5_3, GLO_Q0, SEL_GPS_0), /* R8A779x only */ PINMUX_IPSR_MSEL(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3), PINMUX_IPSR_GPSR(IP5_5_3, VI1_R4_B), PINMUX_IPSR_GPSR(IP5_8_6, SSI_SCK6), PINMUX_IPSR_MSEL(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2), PINMUX_IPSR_MSEL(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0), - PINMUX_IPSR_MSEL(IP5_8_6, GLO_Q1, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP5_8_6, GLO_Q1, SEL_GPS_0), /* R8A779x only */ PINMUX_IPSR_MSEL(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3), PINMUX_IPSR_GPSR(IP5_8_6, VI1_R5_B), PINMUX_IPSR_GPSR(IP5_11_9, SSI_WS6), - PINMUX_IPSR_MSEL(IP5_11_9, GLO_SCLK, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP5_11_9, GLO_SCLK, SEL_GPS_0), /* R8A779x only */ PINMUX_IPSR_MSEL(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3), PINMUX_IPSR_GPSR(IP5_11_9, VI1_R6_B), PINMUX_IPSR_GPSR(IP5_14_12, SSI_SDATA6), - PINMUX_IPSR_MSEL(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1), - PINMUX_IPSR_MSEL(IP5_14_12, GLO_SDATA, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1), /* R8A779x */ + PINMUX_IPSR_MSEL(IP5_14_12, GLO_SDATA, SEL_GPS_0), /* R8A779x only */ PINMUX_IPSR_GPSR(IP5_14_12, VI1_R7_B), PINMUX_IPSR_MSEL(IP5_16_15, SSI_SCK78, SEL_SSI7_0), - PINMUX_IPSR_MSEL(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1), - PINMUX_IPSR_MSEL(IP5_16_15, GLO_SS, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1), /* R8A779x */ + PINMUX_IPSR_MSEL(IP5_16_15, GLO_SS, SEL_GPS_0), /* R8A779x only */ PINMUX_IPSR_MSEL(IP5_19_17, SSI_WS78, SEL_SSI7_0), PINMUX_IPSR_MSEL(IP5_19_17, TX0_D, SEL_SCIF0_3), - PINMUX_IPSR_MSEL(IP5_19_17, STP_ISD_0_B, SEL_SSP_1), - PINMUX_IPSR_MSEL(IP5_19_17, GLO_RFON, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP5_19_17, STP_ISD_0_B, SEL_SSP_1), /* R8A779x only */ + PINMUX_IPSR_MSEL(IP5_19_17, GLO_RFON, SEL_GPS_0), /* R8A779x only */ PINMUX_IPSR_MSEL(IP5_21_20, SSI_SDATA7, SEL_SSI7_0), PINMUX_IPSR_MSEL(IP5_21_20, RX0_D, SEL_SCIF0_3), - PINMUX_IPSR_MSEL(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1), + PINMUX_IPSR_MSEL(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1), /* R8A779x only */ PINMUX_IPSR_MSEL(IP5_23_22, SSI_SDATA8, SEL_SSI8_0), PINMUX_IPSR_MSEL(IP5_23_22, TX1_D, SEL_SCIF1_3), - PINMUX_IPSR_MSEL(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1), + PINMUX_IPSR_MSEL(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1), /* R8A779x */ PINMUX_IPSR_MSEL(IP5_25_24, SSI_SCK9, SEL_SSI9_0), PINMUX_IPSR_MSEL(IP5_25_24, RX1_D, SEL_SCIF1_3), - PINMUX_IPSR_MSEL(IP5_25_24, GLO_SCLK_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP5_25_24, GLO_SCLK_D, SEL_GPS_3), /* R8A779x only */ PINMUX_IPSR_MSEL(IP5_28_26, SSI_WS9, SEL_SSI9_0), PINMUX_IPSR_MSEL(IP5_28_26, TX3_D, SEL_SCIF3_3), PINMUX_IPSR_MSEL(IP5_28_26, CAN0_TX_D, SEL_CAN0_3), - PINMUX_IPSR_MSEL(IP5_28_26, GLO_SDATA_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP5_28_26, GLO_SDATA_D, SEL_GPS_3), /* R8A779x only */ PINMUX_IPSR_MSEL(IP5_31_29, SSI_SDATA9, SEL_SSI9_0), PINMUX_IPSR_MSEL(IP5_31_29, RX3_D, SEL_SCIF3_3), PINMUX_IPSR_MSEL(IP5_31_29, CAN0_RX_D, SEL_CAN0_3), /* IPSR6 */ PINMUX_IPSR_MSEL(IP6_2_0, AUDIO_CLKB, SEL_ADG_0), - PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1), + PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1), /* R8A779x only */ PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1), PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0), PINMUX_IPSR_GPSR(IP6_2_0, DVC_MUTE), - PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4), + PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4), /* R8A779x only */ PINMUX_IPSR_GPSR(IP6_5_3, AUDIO_CLKC), PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2), PINMUX_IPSR_MSEL(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1), PINMUX_IPSR_MSEL(IP6_5_3, RX2, SEL_SCIF2_0), PINMUX_IPSR_MSEL(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0), - PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4), + PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4), /* R8A779x only */ PINMUX_IPSR_GPSR(IP6_7_6, AUDIO_CLKOUT), PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1), PINMUX_IPSR_MSEL(IP6_7_6, TX2, SEL_SCIF2_0), PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0), PINMUX_IPSR_GPSR(IP6_9_8, IRQ0), PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3), - PINMUX_IPSR_GPSR(IP6_9_8, INTC_IRQ0_N), + PINMUX_IPSR_GPSR(IP6_9_8, INTC_IRQ0_N), /* R8A779x only */ PINMUX_IPSR_GPSR(IP6_11_10, IRQ1), PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2), - PINMUX_IPSR_GPSR(IP6_11_10, INTC_IRQ1_N), + PINMUX_IPSR_GPSR(IP6_11_10, INTC_IRQ1_N), /* R8A779x only */ PINMUX_IPSR_GPSR(IP6_13_12, IRQ2), PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3), - PINMUX_IPSR_GPSR(IP6_13_12, INTC_IRQ2_N), + PINMUX_IPSR_GPSR(IP6_13_12, INTC_IRQ2_N), /* R8A779x only */ PINMUX_IPSR_GPSR(IP6_15_14, IRQ3), PINMUX_IPSR_MSEL(IP6_15_14, I2C4_SCL_C, SEL_I2C4_2), PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4), - PINMUX_IPSR_GPSR(IP6_15_14, INTC_IRQ4_N), + PINMUX_IPSR_GPSR(IP6_15_14, INTC_IRQ4_N), /* R8A779x only */ PINMUX_IPSR_GPSR(IP6_18_16, IRQ4), PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2), PINMUX_IPSR_MSEL(IP6_18_16, I2C4_SDA_C, SEL_I2C4_2), PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4), - PINMUX_IPSR_GPSR(IP6_18_16, INTC_IRQ4_N), + PINMUX_IPSR_GPSR(IP6_18_16, INTC_IRQ4_N), /* R8A779x only */ PINMUX_IPSR_GPSR(IP6_20_19, IRQ5), PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2), PINMUX_IPSR_MSEL(IP6_20_19, I2C1_SCL_E, SEL_I2C1_4), @@ -1142,65 +1229,65 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP6_26_24, IRQ7), PINMUX_IPSR_MSEL(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2), PINMUX_IPSR_MSEL(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1), - PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_C, SEL_GPS_2), - PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_C, SEL_GPS_2), /* R8A779x only */ + PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_D, SEL_GPS_3), /* R8A779x only */ PINMUX_IPSR_GPSR(IP6_29_27, IRQ8), PINMUX_IPSR_MSEL(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2), PINMUX_IPSR_MSEL(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1), - PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_C, SEL_GPS_2), - PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_C, SEL_GPS_2), /* R8A779x only */ + PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_D, SEL_GPS_3), /* R8A779x only */ /* IPSR7 */ PINMUX_IPSR_GPSR(IP7_2_0, IRQ9), PINMUX_IPSR_MSEL(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1), PINMUX_IPSR_MSEL(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3), - PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_C, SEL_GPS_2), /* R8A779x only */ PINMUX_IPSR_MSEL(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1), - PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_D, SEL_GPS_3), + PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_D, SEL_GPS_3), /* R8A779x only */ PINMUX_IPSR_GPSR(IP7_5_3, DU1_DR0), - PINMUX_IPSR_GPSR(IP7_5_3, LCDOUT0), + PINMUX_IPSR_GPSR(IP7_5_3, LCDOUT0), /* R8A779x only */ PINMUX_IPSR_MSEL(IP7_5_3, VI1_DATA0_B, SEL_VI1_1), PINMUX_IPSR_MSEL(IP7_5_3, TX0_B, SEL_SCIF0_1), PINMUX_IPSR_MSEL(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1), PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1), PINMUX_IPSR_GPSR(IP7_8_6, DU1_DR1), - PINMUX_IPSR_GPSR(IP7_8_6, LCDOUT1), + PINMUX_IPSR_GPSR(IP7_8_6, LCDOUT1), /* R8A779x only */ PINMUX_IPSR_MSEL(IP7_8_6, VI1_DATA1_B, SEL_VI1_1), PINMUX_IPSR_MSEL(IP7_8_6, RX0_B, SEL_SCIF0_1), PINMUX_IPSR_MSEL(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1), PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1), PINMUX_IPSR_GPSR(IP7_10_9, DU1_DR2), - PINMUX_IPSR_GPSR(IP7_10_9, LCDOUT2), + PINMUX_IPSR_GPSR(IP7_10_9, LCDOUT2), /* R8A779x only */ PINMUX_IPSR_MSEL(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1), PINMUX_IPSR_GPSR(IP7_12_11, DU1_DR3), - PINMUX_IPSR_GPSR(IP7_12_11, LCDOUT3), + PINMUX_IPSR_GPSR(IP7_12_11, LCDOUT3), /* R8A779x only */ PINMUX_IPSR_MSEL(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1), PINMUX_IPSR_GPSR(IP7_14_13, DU1_DR4), - PINMUX_IPSR_GPSR(IP7_14_13, LCDOUT4), + PINMUX_IPSR_GPSR(IP7_14_13, LCDOUT4), /* R8A779x only */ PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1), PINMUX_IPSR_GPSR(IP7_16_15, DU1_DR5), - PINMUX_IPSR_GPSR(IP7_16_15, LCDOUT5), + PINMUX_IPSR_GPSR(IP7_16_15, LCDOUT5), /* R8A779x only */ PINMUX_IPSR_MSEL(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1), PINMUX_IPSR_GPSR(IP7_18_17, DU1_DR6), - PINMUX_IPSR_GPSR(IP7_18_17, LCDOUT6), + PINMUX_IPSR_GPSR(IP7_18_17, LCDOUT6), /* R8A779x only */ PINMUX_IPSR_MSEL(IP7_18_17, SSI_WS1_B, SEL_SSI1_1), PINMUX_IPSR_GPSR(IP7_20_19, DU1_DR7), - PINMUX_IPSR_GPSR(IP7_20_19, LCDOUT7), + PINMUX_IPSR_GPSR(IP7_20_19, LCDOUT7), /* R8A779x only */ PINMUX_IPSR_MSEL(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1), PINMUX_IPSR_GPSR(IP7_23_21, DU1_DG0), - PINMUX_IPSR_GPSR(IP7_23_21, LCDOUT8), + PINMUX_IPSR_GPSR(IP7_23_21, LCDOUT8), /* R8A779x only */ PINMUX_IPSR_MSEL(IP7_23_21, VI1_DATA2_B, SEL_VI1_1), PINMUX_IPSR_MSEL(IP7_23_21, TX1_B, SEL_SCIF1_1), PINMUX_IPSR_MSEL(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1), PINMUX_IPSR_MSEL(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1), PINMUX_IPSR_GPSR(IP7_26_24, DU1_DG1), - PINMUX_IPSR_GPSR(IP7_26_24, LCDOUT9), + PINMUX_IPSR_GPSR(IP7_26_24, LCDOUT9), /* R8A779x only */ PINMUX_IPSR_MSEL(IP7_26_24, VI1_DATA3_B, SEL_VI1_1), PINMUX_IPSR_MSEL(IP7_26_24, RX1_B, SEL_SCIF1_1), PINMUX_IPSR_MSEL(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1), PINMUX_IPSR_MSEL(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1), PINMUX_IPSR_GPSR(IP7_29_27, DU1_DG2), - PINMUX_IPSR_GPSR(IP7_29_27, LCDOUT10), + PINMUX_IPSR_GPSR(IP7_29_27, LCDOUT10), /* R8A779x only */ PINMUX_IPSR_MSEL(IP7_29_27, VI1_DATA4_B, SEL_VI1_1), PINMUX_IPSR_GPSR(IP7_29_27, SCIF1_SCK_B), PINMUX_IPSR_MSEL(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0), @@ -1208,96 +1295,96 @@ static const u16 pinmux_data[] = { /* IPSR8 */ PINMUX_IPSR_GPSR(IP8_2_0, DU1_DG3), - PINMUX_IPSR_GPSR(IP8_2_0, LCDOUT11), + PINMUX_IPSR_GPSR(IP8_2_0, LCDOUT11), /* R8A779x only */ PINMUX_IPSR_MSEL(IP8_2_0, VI1_DATA5_B, SEL_VI1_1), PINMUX_IPSR_MSEL(IP8_2_0, SSI_WS78_B, SEL_SSI7_1), PINMUX_IPSR_GPSR(IP8_5_3, DU1_DG4), - PINMUX_IPSR_GPSR(IP8_5_3, LCDOUT12), + PINMUX_IPSR_GPSR(IP8_5_3, LCDOUT12), /* R8A779x only */ PINMUX_IPSR_MSEL(IP8_5_3, VI1_DATA6_B, SEL_VI1_1), PINMUX_IPSR_MSEL(IP8_5_3, HRX0_B, SEL_HSCIF0_1), PINMUX_IPSR_MSEL(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1), PINMUX_IPSR_MSEL(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1), PINMUX_IPSR_GPSR(IP8_8_6, DU1_DG5), - PINMUX_IPSR_GPSR(IP8_8_6, LCDOUT13), + PINMUX_IPSR_GPSR(IP8_8_6, LCDOUT13), /* R8A779x only */ PINMUX_IPSR_MSEL(IP8_8_6, VI1_DATA7_B, SEL_VI1_1), PINMUX_IPSR_MSEL(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1), PINMUX_IPSR_MSEL(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1), PINMUX_IPSR_MSEL(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1), PINMUX_IPSR_GPSR(IP8_11_9, DU1_DG6), - PINMUX_IPSR_GPSR(IP8_11_9, LCDOUT14), + PINMUX_IPSR_GPSR(IP8_11_9, LCDOUT14), /* R8A779x only */ PINMUX_IPSR_MSEL(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1), PINMUX_IPSR_MSEL(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1), PINMUX_IPSR_MSEL(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1), PINMUX_IPSR_GPSR(IP8_14_12, DU1_DG7), - PINMUX_IPSR_GPSR(IP8_14_12, LCDOUT15), + PINMUX_IPSR_GPSR(IP8_14_12, LCDOUT15), /* R8A779x only */ PINMUX_IPSR_MSEL(IP8_14_12, HTX0_B, SEL_HSCIF0_1), PINMUX_IPSR_MSEL(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1), PINMUX_IPSR_MSEL(IP8_14_12, SSI_WS9_B, SEL_SSI9_1), PINMUX_IPSR_GPSR(IP8_17_15, DU1_DB0), - PINMUX_IPSR_GPSR(IP8_17_15, LCDOUT16), + PINMUX_IPSR_GPSR(IP8_17_15, LCDOUT16), /* R8A779x only */ PINMUX_IPSR_MSEL(IP8_17_15, VI1_CLK_B, SEL_VI1_1), PINMUX_IPSR_MSEL(IP8_17_15, TX2_B, SEL_SCIF2_1), PINMUX_IPSR_MSEL(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1), PINMUX_IPSR_MSEL(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1), PINMUX_IPSR_GPSR(IP8_20_18, DU1_DB1), - PINMUX_IPSR_GPSR(IP8_20_18, LCDOUT17), + PINMUX_IPSR_GPSR(IP8_20_18, LCDOUT17), /* R8A779x only */ PINMUX_IPSR_MSEL(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1), PINMUX_IPSR_MSEL(IP8_20_18, RX2_B, SEL_SCIF2_1), PINMUX_IPSR_MSEL(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1), PINMUX_IPSR_MSEL(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1), PINMUX_IPSR_GPSR(IP8_23_21, DU1_DB2), - PINMUX_IPSR_GPSR(IP8_23_21, LCDOUT18), + PINMUX_IPSR_GPSR(IP8_23_21, LCDOUT18), /* R8A779x only */ PINMUX_IPSR_MSEL(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1), PINMUX_IPSR_GPSR(IP8_23_21, SCIF2_SCK_B), PINMUX_IPSR_MSEL(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1), PINMUX_IPSR_MSEL(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1), PINMUX_IPSR_GPSR(IP8_25_24, DU1_DB3), - PINMUX_IPSR_GPSR(IP8_25_24, LCDOUT19), + PINMUX_IPSR_GPSR(IP8_25_24, LCDOUT19), /* R8A779x only */ PINMUX_IPSR_MSEL(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1), PINMUX_IPSR_GPSR(IP8_27_26, DU1_DB4), - PINMUX_IPSR_GPSR(IP8_27_26, LCDOUT20), + PINMUX_IPSR_GPSR(IP8_27_26, LCDOUT20), /* R8A779x only */ PINMUX_IPSR_MSEL(IP8_27_26, VI1_FIELD_B, SEL_VI1_1), PINMUX_IPSR_MSEL(IP8_27_26, CAN1_RX, SEL_CAN1_0), PINMUX_IPSR_GPSR(IP8_30_28, DU1_DB5), - PINMUX_IPSR_GPSR(IP8_30_28, LCDOUT21), + PINMUX_IPSR_GPSR(IP8_30_28, LCDOUT21), /* R8A779x only */ PINMUX_IPSR_MSEL(IP8_30_28, TX3, SEL_SCIF3_0), PINMUX_IPSR_MSEL(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0), PINMUX_IPSR_MSEL(IP8_30_28, CAN1_TX, SEL_CAN1_0), /* IPSR9 */ PINMUX_IPSR_GPSR(IP9_2_0, DU1_DB6), - PINMUX_IPSR_GPSR(IP9_2_0, LCDOUT22), + PINMUX_IPSR_GPSR(IP9_2_0, LCDOUT22), /* R8A779x only */ PINMUX_IPSR_MSEL(IP9_2_0, I2C3_SCL_C, SEL_I2C3_2), PINMUX_IPSR_MSEL(IP9_2_0, RX3, SEL_SCIF3_0), PINMUX_IPSR_MSEL(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0), PINMUX_IPSR_GPSR(IP9_5_3, DU1_DB7), - PINMUX_IPSR_GPSR(IP9_5_3, LCDOUT23), + PINMUX_IPSR_GPSR(IP9_5_3, LCDOUT23), /* R8A779x only */ PINMUX_IPSR_MSEL(IP9_5_3, I2C3_SDA_C, SEL_I2C3_2), PINMUX_IPSR_MSEL(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0), PINMUX_IPSR_MSEL(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0), PINMUX_IPSR_MSEL(IP9_6, DU1_DOTCLKIN, SEL_DIS_0), - PINMUX_IPSR_GPSR(IP9_6, QSTVA_QVS), + PINMUX_IPSR_GPSR(IP9_6, QSTVA_QVS), /* R8A779x only */ PINMUX_IPSR_GPSR(IP9_7, DU1_DOTCLKOUT0), - PINMUX_IPSR_GPSR(IP9_7, QCLK), + PINMUX_IPSR_GPSR(IP9_7, QCLK), /* R8A779x only */ PINMUX_IPSR_GPSR(IP9_10_8, DU1_DOTCLKOUT1), - PINMUX_IPSR_GPSR(IP9_10_8, QSTVB_QVE), + PINMUX_IPSR_GPSR(IP9_10_8, QSTVB_QVE), /* R8A779x only */ PINMUX_IPSR_MSEL(IP9_10_8, CAN0_TX, SEL_CAN0_0), PINMUX_IPSR_MSEL(IP9_10_8, TX3_B, SEL_SCIF3_1), PINMUX_IPSR_MSEL(IP9_10_8, I2C2_SCL_B, SEL_I2C2_1), PINMUX_IPSR_GPSR(IP9_10_8, PWM4), PINMUX_IPSR_GPSR(IP9_11, DU1_EXHSYNC_DU1_HSYNC), - PINMUX_IPSR_GPSR(IP9_11, QSTH_QHS), + PINMUX_IPSR_GPSR(IP9_11, QSTH_QHS), /* R8A779x only */ PINMUX_IPSR_GPSR(IP9_12, DU1_EXVSYNC_DU1_VSYNC), - PINMUX_IPSR_GPSR(IP9_12, QSTB_QHE), + PINMUX_IPSR_GPSR(IP9_12, QSTB_QHE), /* R8A779x only */ PINMUX_IPSR_GPSR(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE), - PINMUX_IPSR_GPSR(IP9_15_13, QCPV_QDE), + PINMUX_IPSR_GPSR(IP9_15_13, QCPV_QDE), /* R8A779x only */ PINMUX_IPSR_MSEL(IP9_15_13, CAN0_RX, SEL_CAN0_0), PINMUX_IPSR_MSEL(IP9_15_13, RX3_B, SEL_SCIF3_1), PINMUX_IPSR_MSEL(IP9_15_13, I2C2_SDA_B, SEL_I2C2_1), PINMUX_IPSR_GPSR(IP9_16, DU1_DISP), - PINMUX_IPSR_GPSR(IP9_16, QPOLA), + PINMUX_IPSR_GPSR(IP9_16, QPOLA), /* R8A779x only */ PINMUX_IPSR_GPSR(IP9_18_17, DU1_CDE), - PINMUX_IPSR_GPSR(IP9_18_17, QPOLB), + PINMUX_IPSR_GPSR(IP9_18_17, QPOLB), /* R8A779x only */ PINMUX_IPSR_GPSR(IP9_18_17, PWM4_B), PINMUX_IPSR_GPSR(IP9_20_19, VI0_CLKENB), PINMUX_IPSR_MSEL(IP9_20_19, TX4, SEL_SCIF4_0), @@ -1320,7 +1407,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1), PINMUX_IPSR_GPSR(IP9_31_29, VI0_G0), PINMUX_IPSR_MSEL(IP9_31_29, IIC1_SCL, SEL_IIC1_0), - PINMUX_IPSR_MSEL(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2), + PINMUX_IPSR_MSEL(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2), /* R8A779x */ PINMUX_IPSR_MSEL(IP9_31_29, I2C4_SCL, SEL_I2C4_0), PINMUX_IPSR_MSEL(IP9_31_29, HCTS2_N, SEL_HSCIF2_0), PINMUX_IPSR_MSEL(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0), @@ -1329,81 +1416,81 @@ static const u16 pinmux_data[] = { /* IPSR10 */ PINMUX_IPSR_GPSR(IP10_2_0, VI0_G1), PINMUX_IPSR_MSEL(IP10_2_0, IIC1_SDA, SEL_IIC1_0), - PINMUX_IPSR_MSEL(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2), + PINMUX_IPSR_MSEL(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2), /* R8A779x only */ PINMUX_IPSR_MSEL(IP10_2_0, I2C4_SDA, SEL_I2C4_0), PINMUX_IPSR_MSEL(IP10_2_0, HRTS2_N, SEL_HSCIF2_0), PINMUX_IPSR_MSEL(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0), PINMUX_IPSR_GPSR(IP10_2_0, ATADIR1_N), PINMUX_IPSR_GPSR(IP10_5_3, VI0_G2), PINMUX_IPSR_GPSR(IP10_5_3, VI2_HSYNC_N), - PINMUX_IPSR_MSEL(IP10_5_3, STP_ISD_0_C, SEL_SSP_2), + PINMUX_IPSR_MSEL(IP10_5_3, STP_ISD_0_C, SEL_SSP_2), /* R8A779x only */ PINMUX_IPSR_MSEL(IP10_5_3, I2C3_SCL_B, SEL_I2C3_1), PINMUX_IPSR_MSEL(IP10_5_3, HSCK2, SEL_HSCIF2_0), PINMUX_IPSR_MSEL(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0), PINMUX_IPSR_GPSR(IP10_5_3, ATARD1_N), PINMUX_IPSR_GPSR(IP10_8_6, VI0_G3), PINMUX_IPSR_GPSR(IP10_8_6, VI2_VSYNC_N), - PINMUX_IPSR_MSEL(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2), + PINMUX_IPSR_MSEL(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2), /* R8A779x only */ PINMUX_IPSR_MSEL(IP10_8_6, I2C3_SDA_B, SEL_I2C3_1), PINMUX_IPSR_MSEL(IP10_8_6, HRX2, SEL_HSCIF2_0), PINMUX_IPSR_MSEL(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0), PINMUX_IPSR_GPSR(IP10_8_6, ATACS01_N), PINMUX_IPSR_GPSR(IP10_11_9, VI0_G4), PINMUX_IPSR_GPSR(IP10_11_9, VI2_CLKENB), - PINMUX_IPSR_MSEL(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2), + PINMUX_IPSR_MSEL(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2), /* R8A779x */ PINMUX_IPSR_MSEL(IP10_11_9, HTX2, SEL_HSCIF2_0), PINMUX_IPSR_MSEL(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0), PINMUX_IPSR_MSEL(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3), PINMUX_IPSR_GPSR(IP10_14_12, VI0_G5), PINMUX_IPSR_GPSR(IP10_14_12, VI2_FIELD), - PINMUX_IPSR_MSEL(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2), - PINMUX_IPSR_MSEL(IP10_14_12, FMCLK_D, SEL_FM_3), + PINMUX_IPSR_MSEL(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2), /* R8A779x */ + PINMUX_IPSR_MSEL(IP10_14_12, FMCLK_D, SEL_FM_3), /* R8A779x only */ PINMUX_IPSR_MSEL(IP10_14_12, CAN0_TX_E, SEL_CAN0_4), PINMUX_IPSR_MSEL(IP10_14_12, HTX1_D, SEL_HSCIF1_3), PINMUX_IPSR_MSEL(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3), PINMUX_IPSR_GPSR(IP10_16_15, VI0_G6), PINMUX_IPSR_GPSR(IP10_16_15, VI2_CLK), - PINMUX_IPSR_MSEL(IP10_16_15, BPFCLK_D, SEL_FM_3), + PINMUX_IPSR_MSEL(IP10_16_15, BPFCLK_D, SEL_FM_3), /* R8A779x only */ PINMUX_IPSR_GPSR(IP10_18_17, VI0_G7), PINMUX_IPSR_GPSR(IP10_18_17, VI2_DATA0), - PINMUX_IPSR_MSEL(IP10_18_17, FMIN_D, SEL_FM_3), + PINMUX_IPSR_MSEL(IP10_18_17, FMIN_D, SEL_FM_3), /* R8A779x only */ PINMUX_IPSR_GPSR(IP10_21_19, VI0_R0), PINMUX_IPSR_GPSR(IP10_21_19, VI2_DATA1), - PINMUX_IPSR_MSEL(IP10_21_19, GLO_I0_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP10_21_19, GLO_I0_B, SEL_GPS_1), /* R8A779x only */ PINMUX_IPSR_MSEL(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2), PINMUX_IPSR_GPSR(IP10_21_19, ATACS11_N), PINMUX_IPSR_GPSR(IP10_24_22, VI0_R1), PINMUX_IPSR_GPSR(IP10_24_22, VI2_DATA2), - PINMUX_IPSR_MSEL(IP10_24_22, GLO_I1_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP10_24_22, GLO_I1_B, SEL_GPS_1), /* R8A779x only */ PINMUX_IPSR_MSEL(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2), PINMUX_IPSR_GPSR(IP10_24_22, ATAG1_N), PINMUX_IPSR_GPSR(IP10_26_25, VI0_R2), PINMUX_IPSR_GPSR(IP10_26_25, VI2_DATA3), - PINMUX_IPSR_MSEL(IP10_26_25, GLO_Q0_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP10_26_25, GLO_Q0_B, SEL_GPS_1), /* R8A779x only */ PINMUX_IPSR_MSEL(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2), PINMUX_IPSR_GPSR(IP10_28_27, VI0_R3), PINMUX_IPSR_GPSR(IP10_28_27, VI2_DATA4), - PINMUX_IPSR_MSEL(IP10_28_27, GLO_Q1_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP10_28_27, GLO_Q1_B, SEL_GPS_1), /* R8A779x only */ PINMUX_IPSR_MSEL(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2), PINMUX_IPSR_GPSR(IP10_31_29, VI0_R4), PINMUX_IPSR_GPSR(IP10_31_29, VI2_DATA5), - PINMUX_IPSR_MSEL(IP10_31_29, GLO_SCLK_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP10_31_29, GLO_SCLK_B, SEL_GPS_1), /* R8A779x only */ PINMUX_IPSR_MSEL(IP10_31_29, TX0_C, SEL_SCIF0_2), PINMUX_IPSR_MSEL(IP10_31_29, I2C1_SCL_D, SEL_I2C1_3), /* IPSR11 */ PINMUX_IPSR_GPSR(IP11_2_0, VI0_R5), PINMUX_IPSR_GPSR(IP11_2_0, VI2_DATA6), - PINMUX_IPSR_MSEL(IP11_2_0, GLO_SDATA_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP11_2_0, GLO_SDATA_B, SEL_GPS_1), /* R8A779x only */ PINMUX_IPSR_MSEL(IP11_2_0, RX0_C, SEL_SCIF0_2), PINMUX_IPSR_MSEL(IP11_2_0, I2C1_SDA_D, SEL_I2C1_3), PINMUX_IPSR_GPSR(IP11_5_3, VI0_R6), PINMUX_IPSR_GPSR(IP11_5_3, VI2_DATA7), - PINMUX_IPSR_MSEL(IP11_5_3, GLO_SS_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP11_5_3, GLO_SS_B, SEL_GPS_1), /* R8A779x only */ PINMUX_IPSR_MSEL(IP11_5_3, TX1_C, SEL_SCIF1_2), PINMUX_IPSR_MSEL(IP11_5_3, I2C4_SCL_B, SEL_I2C4_1), PINMUX_IPSR_GPSR(IP11_8_6, VI0_R7), - PINMUX_IPSR_MSEL(IP11_8_6, GLO_RFON_B, SEL_GPS_1), + PINMUX_IPSR_MSEL(IP11_8_6, GLO_RFON_B, SEL_GPS_1), /* R8A779x only */ PINMUX_IPSR_MSEL(IP11_8_6, RX1_C, SEL_SCIF1_2), PINMUX_IPSR_MSEL(IP11_8_6, CAN0_RX_E, SEL_CAN0_4), PINMUX_IPSR_MSEL(IP11_8_6, I2C4_SDA_B, SEL_I2C4_1), @@ -1485,42 +1572,42 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1), PINMUX_IPSR_GPSR(IP12_19_18, ETH_MAGIC), PINMUX_IPSR_GPSR(IP12_19_18, AVB_TXD4), - PINMUX_IPSR_MSEL(IP12_19_18, IETX_C, SEL_IEB_2), + PINMUX_IPSR_MSEL(IP12_19_18, IETX_C, SEL_IEB_2), /* R8A779x only */ PINMUX_IPSR_GPSR(IP12_21_20, ETH_TXD0), PINMUX_IPSR_GPSR(IP12_21_20, AVB_TXD5), - PINMUX_IPSR_MSEL(IP12_21_20, IECLK_C, SEL_IEB_2), + PINMUX_IPSR_MSEL(IP12_21_20, IECLK_C, SEL_IEB_2), /* R8A779x only */ PINMUX_IPSR_GPSR(IP12_23_22, ETH_MDC), PINMUX_IPSR_GPSR(IP12_23_22, AVB_TXD6), - PINMUX_IPSR_MSEL(IP12_23_22, IERX_C, SEL_IEB_2), - PINMUX_IPSR_MSEL(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0), + PINMUX_IPSR_MSEL(IP12_23_22, IERX_C, SEL_IEB_2), /* R8A779x only */ + PINMUX_IPSR_MSEL(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0), /* R8A779x */ PINMUX_IPSR_GPSR(IP12_26_24, AVB_TXD7), PINMUX_IPSR_MSEL(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3), - PINMUX_IPSR_MSEL(IP12_26_24, ADIDATA_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP12_26_24, ADIDATA_B, SEL_RAD_1), /* R8A779x only */ PINMUX_IPSR_MSEL(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2), - PINMUX_IPSR_MSEL(IP12_29_27, STP_ISCLK_0, SEL_SSP_0), + PINMUX_IPSR_MSEL(IP12_29_27, STP_ISCLK_0, SEL_SSP_0), /* R8A779x only */ PINMUX_IPSR_GPSR(IP12_29_27, AVB_TX_EN), PINMUX_IPSR_MSEL(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3), - PINMUX_IPSR_MSEL(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1), /* R8A779x */ PINMUX_IPSR_MSEL(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2), /* IPSR13 */ - PINMUX_IPSR_MSEL(IP13_2_0, STP_ISD_0, SEL_SSP_0), + PINMUX_IPSR_MSEL(IP13_2_0, STP_ISD_0, SEL_SSP_0), /* R8A779x only */ PINMUX_IPSR_GPSR(IP13_2_0, AVB_TX_ER), PINMUX_IPSR_MSEL(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2), - PINMUX_IPSR_MSEL(IP13_2_0, ADICLK_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP13_2_0, ADICLK_B, SEL_RAD_1), /* R8A779x only */ PINMUX_IPSR_MSEL(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2), - PINMUX_IPSR_MSEL(IP13_4_3, STP_ISEN_0, SEL_SSP_0), + PINMUX_IPSR_MSEL(IP13_4_3, STP_ISEN_0, SEL_SSP_0), /* R8A779x only */ PINMUX_IPSR_GPSR(IP13_4_3, AVB_TX_CLK), - PINMUX_IPSR_MSEL(IP13_4_3, ADICHS0_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP13_4_3, ADICHS0_B, SEL_RAD_1), /* R8A779x only */ PINMUX_IPSR_MSEL(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2), - PINMUX_IPSR_MSEL(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0), + PINMUX_IPSR_MSEL(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0), /* R8A779x only */ PINMUX_IPSR_GPSR(IP13_6_5, AVB_COL), - PINMUX_IPSR_MSEL(IP13_6_5, ADICHS1_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP13_6_5, ADICHS1_B, SEL_RAD_1), /* R8A779x only */ PINMUX_IPSR_MSEL(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2), - PINMUX_IPSR_MSEL(IP13_9_7, STP_OPWM_0, SEL_SSP_0), + PINMUX_IPSR_MSEL(IP13_9_7, STP_OPWM_0, SEL_SSP_0), /* R8A779x only */ PINMUX_IPSR_GPSR(IP13_9_7, AVB_GTX_CLK), PINMUX_IPSR_GPSR(IP13_9_7, PWM0_B), - PINMUX_IPSR_MSEL(IP13_9_7, ADICHS2_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP13_9_7, ADICHS2_B, SEL_RAD_1), /* R8A779x only */ PINMUX_IPSR_MSEL(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2), PINMUX_IPSR_GPSR(IP13_10, SD0_CLK), PINMUX_IPSR_MSEL(IP13_10, SPCLK_B, SEL_QSP_1), @@ -1536,26 +1623,26 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP13_15, SSL_B, SEL_QSP_1), PINMUX_IPSR_GPSR(IP13_18_16, SD0_CD), PINMUX_IPSR_MSEL(IP13_18_16, MMC_D6_B, SEL_MMC_1), - PINMUX_IPSR_MSEL(IP13_18_16, SIM0_RST_B, SEL_SIM_1), + PINMUX_IPSR_MSEL(IP13_18_16, SIM0_RST_B, SEL_SIM_1), /* R8A779x only */ PINMUX_IPSR_MSEL(IP13_18_16, CAN0_RX_F, SEL_CAN0_5), PINMUX_IPSR_MSEL(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1), PINMUX_IPSR_MSEL(IP13_18_16, TX3_C, SEL_SCIF3_2), PINMUX_IPSR_GPSR(IP13_21_19, SD0_WP), PINMUX_IPSR_MSEL(IP13_21_19, MMC_D7_B, SEL_MMC_1), - PINMUX_IPSR_MSEL(IP13_21_19, SIM0_D_B, SEL_SIM_1), + PINMUX_IPSR_MSEL(IP13_21_19, SIM0_D_B, SEL_SIM_1), /* R8A779x only */ PINMUX_IPSR_MSEL(IP13_21_19, CAN0_TX_F, SEL_CAN0_5), PINMUX_IPSR_MSEL(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1), PINMUX_IPSR_MSEL(IP13_21_19, RX3_C, SEL_SCIF3_2), PINMUX_IPSR_GPSR(IP13_22, SD1_CMD), - PINMUX_IPSR_MSEL(IP13_22, REMOCON_B, SEL_RCN_1), + PINMUX_IPSR_MSEL(IP13_22, REMOCON_B, SEL_RCN_1), /* R8A779x only */ PINMUX_IPSR_GPSR(IP13_24_23, SD1_DATA0), - PINMUX_IPSR_MSEL(IP13_24_23, SPEEDIN_B, SEL_RSP_1), + PINMUX_IPSR_MSEL(IP13_24_23, SPEEDIN_B, SEL_RSP_1), /* R8A779x only */ PINMUX_IPSR_GPSR(IP13_25, SD1_DATA1), - PINMUX_IPSR_MSEL(IP13_25, IETX_B, SEL_IEB_1), + PINMUX_IPSR_MSEL(IP13_25, IETX_B, SEL_IEB_1), /* R8A779x only */ PINMUX_IPSR_GPSR(IP13_26, SD1_DATA2), - PINMUX_IPSR_MSEL(IP13_26, IECLK_B, SEL_IEB_1), + PINMUX_IPSR_MSEL(IP13_26, IECLK_B, SEL_IEB_1), /* R8A779x only */ PINMUX_IPSR_GPSR(IP13_27, SD1_DATA3), - PINMUX_IPSR_MSEL(IP13_27, IERX_B, SEL_IEB_1), + PINMUX_IPSR_MSEL(IP13_27, IERX_B, SEL_IEB_1), /* R8A779x only */ PINMUX_IPSR_GPSR(IP13_30_28, SD1_CD), PINMUX_IPSR_GPSR(IP13_30_28, PWM0), PINMUX_IPSR_GPSR(IP13_30_28, TPU_TO0), @@ -1589,59 +1676,59 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2), PINMUX_IPSR_MSEL(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0), PINMUX_IPSR_MSEL(IP14_16_14, RX2_C, SEL_SCIF2_2), - PINMUX_IPSR_MSEL(IP14_16_14, ADIDATA, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP14_16_14, ADIDATA, SEL_RAD_0), /* R8A779x only */ PINMUX_IPSR_MSEL(IP14_16_14, VI1_CLK_C, SEL_VI1_2), PINMUX_IPSR_GPSR(IP14_16_14, VI1_G0_B), PINMUX_IPSR_MSEL(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0), PINMUX_IPSR_MSEL(IP14_19_17, TX2_C, SEL_SCIF2_2), - PINMUX_IPSR_MSEL(IP14_19_17, ADICS_SAMP, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP14_19_17, ADICS_SAMP, SEL_RAD_0), /* R8A779x only */ PINMUX_IPSR_MSEL(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2), PINMUX_IPSR_GPSR(IP14_19_17, VI1_G1_B), PINMUX_IPSR_MSEL(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0), - PINMUX_IPSR_MSEL(IP14_22_20, ADICLK, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP14_22_20, ADICLK, SEL_RAD_0), /* R8A779x only */ PINMUX_IPSR_MSEL(IP14_22_20, VI1_FIELD_C, SEL_VI1_2), PINMUX_IPSR_GPSR(IP14_22_20, VI1_G2_B), PINMUX_IPSR_MSEL(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0), - PINMUX_IPSR_MSEL(IP14_25_23, ADICHS0, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP14_25_23, ADICHS0, SEL_RAD_0), /* R8A779x only */ PINMUX_IPSR_MSEL(IP14_25_23, VI1_DATA0_C, SEL_VI1_2), PINMUX_IPSR_GPSR(IP14_25_23, VI1_G3_B), PINMUX_IPSR_MSEL(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0), PINMUX_IPSR_MSEL(IP14_28_26, MMC_D6, SEL_MMC_0), - PINMUX_IPSR_MSEL(IP14_28_26, ADICHS1, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP14_28_26, ADICHS1, SEL_RAD_0), /* R8A779x only */ PINMUX_IPSR_MSEL(IP14_28_26, TX0_E, SEL_SCIF0_4), PINMUX_IPSR_MSEL(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2), PINMUX_IPSR_MSEL(IP14_28_26, IIC0_SCL_C, SEL_IIC0_2), PINMUX_IPSR_GPSR(IP14_28_26, VI1_G4_B), PINMUX_IPSR_MSEL(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0), PINMUX_IPSR_MSEL(IP14_31_29, MMC_D7, SEL_MMC_0), - PINMUX_IPSR_MSEL(IP14_31_29, ADICHS2, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP14_31_29, ADICHS2, SEL_RAD_0), /* R8A779x only */ PINMUX_IPSR_MSEL(IP14_31_29, RX0_E, SEL_SCIF0_4), PINMUX_IPSR_MSEL(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2), PINMUX_IPSR_MSEL(IP14_31_29, IIC0_SDA_C, SEL_IIC0_2), PINMUX_IPSR_GPSR(IP14_31_29, VI1_G5_B), /* IPSR15 */ - PINMUX_IPSR_MSEL(IP15_1_0, SIM0_RST, SEL_SIM_0), - PINMUX_IPSR_MSEL(IP15_1_0, IETX, SEL_IEB_0), + PINMUX_IPSR_MSEL(IP15_1_0, SIM0_RST, SEL_SIM_0), /* R8A779x only */ + PINMUX_IPSR_MSEL(IP15_1_0, IETX, SEL_IEB_0), /* R8A779x only */ PINMUX_IPSR_MSEL(IP15_1_0, CAN1_TX_D, SEL_CAN1_3), - PINMUX_IPSR_GPSR(IP15_3_2, SIM0_CLK), - PINMUX_IPSR_MSEL(IP15_3_2, IECLK, SEL_IEB_0), + PINMUX_IPSR_GPSR(IP15_3_2, SIM0_CLK), /* R8A779x only */ + PINMUX_IPSR_MSEL(IP15_3_2, IECLK, SEL_IEB_0), /* R8A779x only */ PINMUX_IPSR_MSEL(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2), - PINMUX_IPSR_MSEL(IP15_5_4, SIM0_D, SEL_SIM_0), - PINMUX_IPSR_MSEL(IP15_5_4, IERX, SEL_IEB_0), + PINMUX_IPSR_MSEL(IP15_5_4, SIM0_D, SEL_SIM_0), /* R8A779x only */ + PINMUX_IPSR_MSEL(IP15_5_4, IERX, SEL_IEB_0), /* R8A779x only */ PINMUX_IPSR_MSEL(IP15_5_4, CAN1_RX_D, SEL_CAN1_3), - PINMUX_IPSR_MSEL(IP15_8_6, GPS_CLK, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP15_8_6, GPS_CLK, SEL_GPS_0), /* R8A779x only */ PINMUX_IPSR_MSEL(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2), PINMUX_IPSR_MSEL(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1), PINMUX_IPSR_GPSR(IP15_8_6, PWM5_B), PINMUX_IPSR_MSEL(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2), - PINMUX_IPSR_MSEL(IP15_11_9, GPS_SIGN, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP15_11_9, GPS_SIGN, SEL_GPS_0), /* R8A779x only */ PINMUX_IPSR_MSEL(IP15_11_9, TX4_C, SEL_SCIF4_2), PINMUX_IPSR_MSEL(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2), PINMUX_IPSR_GPSR(IP15_11_9, PWM5), PINMUX_IPSR_GPSR(IP15_11_9, VI1_G6_B), PINMUX_IPSR_MSEL(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2), - PINMUX_IPSR_MSEL(IP15_14_12, GPS_MAG, SEL_GPS_0), + PINMUX_IPSR_MSEL(IP15_14_12, GPS_MAG, SEL_GPS_0), /* R8A779x only */ PINMUX_IPSR_MSEL(IP15_14_12, RX4_C, SEL_SCIF4_2), PINMUX_IPSR_MSEL(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2), PINMUX_IPSR_GPSR(IP15_14_12, PWM6), @@ -1649,27 +1736,27 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2), PINMUX_IPSR_MSEL(IP15_17_15, HCTS0_N, SEL_HSCIF0_0), PINMUX_IPSR_MSEL(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0), - PINMUX_IPSR_MSEL(IP15_17_15, GLO_I0_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP15_17_15, GLO_I0_C, SEL_GPS_2), /* R8A779x only */ PINMUX_IPSR_MSEL(IP15_17_15, TCLK1, SEL_TMU1_0), PINMUX_IPSR_MSEL(IP15_17_15, VI1_DATA1_C, SEL_VI1_2), PINMUX_IPSR_MSEL(IP15_20_18, HRTS0_N, SEL_HSCIF0_0), PINMUX_IPSR_MSEL(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0), - PINMUX_IPSR_MSEL(IP15_20_18, GLO_I1_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP15_20_18, GLO_I1_C, SEL_GPS_2), /* R8A779x only */ PINMUX_IPSR_MSEL(IP15_20_18, VI1_DATA2_C, SEL_VI1_2), PINMUX_IPSR_MSEL(IP15_23_21, HSCK0, SEL_HSCIF0_0), PINMUX_IPSR_MSEL(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0), - PINMUX_IPSR_MSEL(IP15_23_21, GLO_Q0_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP15_23_21, GLO_Q0_C, SEL_GPS_2), /* R8A779x only */ PINMUX_IPSR_MSEL(IP15_23_21, CAN_CLK, SEL_CANCLK_0), PINMUX_IPSR_GPSR(IP15_23_21, TCLK2), PINMUX_IPSR_MSEL(IP15_23_21, VI1_DATA3_C, SEL_VI1_2), PINMUX_IPSR_MSEL(IP15_26_24, HRX0, SEL_HSCIF0_0), PINMUX_IPSR_MSEL(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0), - PINMUX_IPSR_MSEL(IP15_26_24, GLO_Q1_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP15_26_24, GLO_Q1_C, SEL_GPS_2), /* R8A779x only */ PINMUX_IPSR_MSEL(IP15_26_24, CAN0_RX_B, SEL_CAN0_1), PINMUX_IPSR_MSEL(IP15_26_24, VI1_DATA4_C, SEL_VI1_2), PINMUX_IPSR_MSEL(IP15_29_27, HTX0, SEL_HSCIF0_0), PINMUX_IPSR_MSEL(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0), - PINMUX_IPSR_MSEL(IP15_29_27, GLO_SCLK_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP15_29_27, GLO_SCLK_C, SEL_GPS_2), /* R8A779x only */ PINMUX_IPSR_MSEL(IP15_29_27, CAN0_TX_B, SEL_CAN0_1), PINMUX_IPSR_MSEL(IP15_29_27, VI1_DATA5_C, SEL_VI1_2), @@ -1677,24 +1764,24 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP16_2_0, HRX1, SEL_HSCIF1_0), PINMUX_IPSR_MSEL(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0), PINMUX_IPSR_GPSR(IP16_2_0, VI1_R0_B), - PINMUX_IPSR_MSEL(IP16_2_0, GLO_SDATA_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP16_2_0, GLO_SDATA_C, SEL_GPS_2), /* R8A779x only */ PINMUX_IPSR_MSEL(IP16_2_0, VI1_DATA6_C, SEL_VI1_2), PINMUX_IPSR_MSEL(IP16_5_3, HTX1, SEL_HSCIF1_0), PINMUX_IPSR_MSEL(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0), PINMUX_IPSR_GPSR(IP16_5_3, VI1_R1_B), - PINMUX_IPSR_MSEL(IP16_5_3, GLO_SS_C, SEL_GPS_2), + PINMUX_IPSR_MSEL(IP16_5_3, GLO_SS_C, SEL_GPS_2), /* R8A779x only */ PINMUX_IPSR_MSEL(IP16_5_3, VI1_DATA7_C, SEL_VI1_2), PINMUX_IPSR_MSEL(IP16_7_6, HSCK1, SEL_HSCIF1_0), PINMUX_IPSR_MSEL(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0), - PINMUX_IPSR_GPSR(IP16_7_6, MLB_CLK), - PINMUX_IPSR_MSEL(IP16_7_6, GLO_RFON_C, SEL_GPS_2), + PINMUX_IPSR_GPSR(IP16_7_6, MLB_CLK), /* R8A779x only */ + PINMUX_IPSR_MSEL(IP16_7_6, GLO_RFON_C, SEL_GPS_2), /* R8A779x only */ PINMUX_IPSR_MSEL(IP16_9_8, HCTS1_N, SEL_HSCIF1_0), PINMUX_IPSR_GPSR(IP16_9_8, SCIFB1_CTS_N), - PINMUX_IPSR_GPSR(IP16_9_8, MLB_SIG), + PINMUX_IPSR_GPSR(IP16_9_8, MLB_SIG), /* R8A779x only */ PINMUX_IPSR_MSEL(IP16_9_8, CAN1_TX_B, SEL_CAN1_1), PINMUX_IPSR_MSEL(IP16_11_10, HRTS1_N, SEL_HSCIF1_0), PINMUX_IPSR_GPSR(IP16_11_10, SCIFB1_RTS_N), - PINMUX_IPSR_GPSR(IP16_11_10, MLB_DAT), + PINMUX_IPSR_GPSR(IP16_11_10, MLB_DAT), /* R8A779x only */ PINMUX_IPSR_MSEL(IP16_11_10, CAN1_RX_B, SEL_CAN1_1), }; @@ -1702,7 +1789,7 @@ static const struct sh_pfc_pin pinmux_pi PINMUX_GPIO_GP_ALL(), }; -/* - ADI -------------------------------------------------------------------- */ +/* - ADI (R8A779x only) ----------------------------------------------------- */ static const unsigned int adi_common_pins[] = { /* ADIDATA, ADICS/SAMP, ADICLK */ RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26), @@ -2555,7 +2642,7 @@ static const unsigned int intc_irq3_pins static const unsigned int intc_irq3_mux[] = { IRQ3_MARK, }; -/* - MLB+ ------------------------------------------------------------------- */ +/* - MLB+ (R8A779x only) ---------------------------------------------------- */ static const unsigned int mlb_3pin_pins[] = { RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9), }; @@ -4419,359 +4506,367 @@ static const unsigned int vin2_clk_mux[] VI2_CLK_MARK, }; -static const struct sh_pfc_pin_group pinmux_groups[] = { - SH_PFC_PIN_GROUP(adi_common), - SH_PFC_PIN_GROUP(adi_chsel0), - SH_PFC_PIN_GROUP(adi_chsel1), - SH_PFC_PIN_GROUP(adi_chsel2), - SH_PFC_PIN_GROUP(adi_common_b), - SH_PFC_PIN_GROUP(adi_chsel0_b), - SH_PFC_PIN_GROUP(adi_chsel1_b), - SH_PFC_PIN_GROUP(adi_chsel2_b), - SH_PFC_PIN_GROUP(audio_clk_a), - SH_PFC_PIN_GROUP(audio_clk_b), - SH_PFC_PIN_GROUP(audio_clk_b_b), - SH_PFC_PIN_GROUP(audio_clk_c), - SH_PFC_PIN_GROUP(audio_clkout), - SH_PFC_PIN_GROUP(avb_link), - SH_PFC_PIN_GROUP(avb_magic), - SH_PFC_PIN_GROUP(avb_phy_int), - SH_PFC_PIN_GROUP(avb_mdio), - SH_PFC_PIN_GROUP(avb_mii), - SH_PFC_PIN_GROUP(avb_gmii), - SH_PFC_PIN_GROUP(can0_data), - SH_PFC_PIN_GROUP(can0_data_b), - SH_PFC_PIN_GROUP(can0_data_c), - SH_PFC_PIN_GROUP(can0_data_d), - SH_PFC_PIN_GROUP(can0_data_e), - SH_PFC_PIN_GROUP(can0_data_f), - SH_PFC_PIN_GROUP(can1_data), - SH_PFC_PIN_GROUP(can1_data_b), - SH_PFC_PIN_GROUP(can1_data_c), - SH_PFC_PIN_GROUP(can1_data_d), - SH_PFC_PIN_GROUP(can_clk), - SH_PFC_PIN_GROUP(can_clk_b), - SH_PFC_PIN_GROUP(can_clk_c), - SH_PFC_PIN_GROUP(can_clk_d), - SH_PFC_PIN_GROUP(du_rgb666), - SH_PFC_PIN_GROUP(du_rgb888), - SH_PFC_PIN_GROUP(du_clk_out_0), - SH_PFC_PIN_GROUP(du_clk_out_1), - SH_PFC_PIN_GROUP(du_sync), - SH_PFC_PIN_GROUP(du_oddf), - SH_PFC_PIN_GROUP(du_cde), - SH_PFC_PIN_GROUP(du_disp), - SH_PFC_PIN_GROUP(du0_clk_in), - SH_PFC_PIN_GROUP(du1_clk_in), - SH_PFC_PIN_GROUP(du1_clk_in_b), - SH_PFC_PIN_GROUP(du1_clk_in_c), - SH_PFC_PIN_GROUP(eth_link), - SH_PFC_PIN_GROUP(eth_magic), - SH_PFC_PIN_GROUP(eth_mdio), - SH_PFC_PIN_GROUP(eth_rmii), - SH_PFC_PIN_GROUP(hscif0_data), - SH_PFC_PIN_GROUP(hscif0_clk), - SH_PFC_PIN_GROUP(hscif0_ctrl), - SH_PFC_PIN_GROUP(hscif0_data_b), - SH_PFC_PIN_GROUP(hscif0_ctrl_b), - SH_PFC_PIN_GROUP(hscif0_data_c), - SH_PFC_PIN_GROUP(hscif0_clk_c), - SH_PFC_PIN_GROUP(hscif1_data), - SH_PFC_PIN_GROUP(hscif1_clk), - SH_PFC_PIN_GROUP(hscif1_ctrl), - SH_PFC_PIN_GROUP(hscif1_data_b), - SH_PFC_PIN_GROUP(hscif1_data_c), - SH_PFC_PIN_GROUP(hscif1_clk_c), - SH_PFC_PIN_GROUP(hscif1_ctrl_c), - SH_PFC_PIN_GROUP(hscif1_data_d), - SH_PFC_PIN_GROUP(hscif1_data_e), - SH_PFC_PIN_GROUP(hscif1_clk_e), - SH_PFC_PIN_GROUP(hscif1_ctrl_e), - SH_PFC_PIN_GROUP(hscif2_data), - SH_PFC_PIN_GROUP(hscif2_clk), - SH_PFC_PIN_GROUP(hscif2_ctrl), - SH_PFC_PIN_GROUP(hscif2_data_b), - SH_PFC_PIN_GROUP(hscif2_ctrl_b), - SH_PFC_PIN_GROUP(hscif2_data_c), - SH_PFC_PIN_GROUP(hscif2_clk_c), - SH_PFC_PIN_GROUP(hscif2_data_d), - SH_PFC_PIN_GROUP(i2c0), - SH_PFC_PIN_GROUP(i2c0_b), - SH_PFC_PIN_GROUP(i2c0_c), - SH_PFC_PIN_GROUP(i2c1), - SH_PFC_PIN_GROUP(i2c1_b), - SH_PFC_PIN_GROUP(i2c1_c), - SH_PFC_PIN_GROUP(i2c1_d), - SH_PFC_PIN_GROUP(i2c1_e), - SH_PFC_PIN_GROUP(i2c2), - SH_PFC_PIN_GROUP(i2c2_b), - SH_PFC_PIN_GROUP(i2c2_c), - SH_PFC_PIN_GROUP(i2c2_d), - SH_PFC_PIN_GROUP(i2c3), - SH_PFC_PIN_GROUP(i2c3_b), - SH_PFC_PIN_GROUP(i2c3_c), - SH_PFC_PIN_GROUP(i2c3_d), - SH_PFC_PIN_GROUP(i2c4), - SH_PFC_PIN_GROUP(i2c4_b), - SH_PFC_PIN_GROUP(i2c4_c), - SH_PFC_PIN_GROUP(i2c7), - SH_PFC_PIN_GROUP(i2c7_b), - SH_PFC_PIN_GROUP(i2c7_c), - SH_PFC_PIN_GROUP(i2c8), - SH_PFC_PIN_GROUP(i2c8_b), - SH_PFC_PIN_GROUP(i2c8_c), - SH_PFC_PIN_GROUP(intc_irq0), - SH_PFC_PIN_GROUP(intc_irq1), - SH_PFC_PIN_GROUP(intc_irq2), - SH_PFC_PIN_GROUP(intc_irq3), - SH_PFC_PIN_GROUP(mlb_3pin), - SH_PFC_PIN_GROUP(mmc_data1), - SH_PFC_PIN_GROUP(mmc_data4), - SH_PFC_PIN_GROUP(mmc_data8), - SH_PFC_PIN_GROUP(mmc_ctrl), - SH_PFC_PIN_GROUP(msiof0_clk), - SH_PFC_PIN_GROUP(msiof0_sync), - SH_PFC_PIN_GROUP(msiof0_ss1), - SH_PFC_PIN_GROUP(msiof0_ss2), - SH_PFC_PIN_GROUP(msiof0_rx), - SH_PFC_PIN_GROUP(msiof0_tx), - SH_PFC_PIN_GROUP(msiof0_clk_b), - SH_PFC_PIN_GROUP(msiof0_sync_b), - SH_PFC_PIN_GROUP(msiof0_ss1_b), - SH_PFC_PIN_GROUP(msiof0_ss2_b), - SH_PFC_PIN_GROUP(msiof0_rx_b), - SH_PFC_PIN_GROUP(msiof0_tx_b), - SH_PFC_PIN_GROUP(msiof0_clk_c), - SH_PFC_PIN_GROUP(msiof0_sync_c), - SH_PFC_PIN_GROUP(msiof0_ss1_c), - SH_PFC_PIN_GROUP(msiof0_ss2_c), - SH_PFC_PIN_GROUP(msiof0_rx_c), - SH_PFC_PIN_GROUP(msiof0_tx_c), - SH_PFC_PIN_GROUP(msiof1_clk), - SH_PFC_PIN_GROUP(msiof1_sync), - SH_PFC_PIN_GROUP(msiof1_ss1), - SH_PFC_PIN_GROUP(msiof1_ss2), - SH_PFC_PIN_GROUP(msiof1_rx), - SH_PFC_PIN_GROUP(msiof1_tx), - SH_PFC_PIN_GROUP(msiof1_clk_b), - SH_PFC_PIN_GROUP(msiof1_sync_b), - SH_PFC_PIN_GROUP(msiof1_ss1_b), - SH_PFC_PIN_GROUP(msiof1_ss2_b), - SH_PFC_PIN_GROUP(msiof1_rx_b), - SH_PFC_PIN_GROUP(msiof1_tx_b), - SH_PFC_PIN_GROUP(msiof1_clk_c), - SH_PFC_PIN_GROUP(msiof1_sync_c), - SH_PFC_PIN_GROUP(msiof1_rx_c), - SH_PFC_PIN_GROUP(msiof1_tx_c), - SH_PFC_PIN_GROUP(msiof1_clk_d), - SH_PFC_PIN_GROUP(msiof1_sync_d), - SH_PFC_PIN_GROUP(msiof1_ss1_d), - SH_PFC_PIN_GROUP(msiof1_rx_d), - SH_PFC_PIN_GROUP(msiof1_tx_d), - SH_PFC_PIN_GROUP(msiof1_clk_e), - SH_PFC_PIN_GROUP(msiof1_sync_e), - SH_PFC_PIN_GROUP(msiof1_rx_e), - SH_PFC_PIN_GROUP(msiof1_tx_e), - SH_PFC_PIN_GROUP(msiof2_clk), - SH_PFC_PIN_GROUP(msiof2_sync), - SH_PFC_PIN_GROUP(msiof2_ss1), - SH_PFC_PIN_GROUP(msiof2_ss2), - SH_PFC_PIN_GROUP(msiof2_rx), - SH_PFC_PIN_GROUP(msiof2_tx), - SH_PFC_PIN_GROUP(msiof2_clk_b), - SH_PFC_PIN_GROUP(msiof2_sync_b), - SH_PFC_PIN_GROUP(msiof2_ss1_b), - SH_PFC_PIN_GROUP(msiof2_ss2_b), - SH_PFC_PIN_GROUP(msiof2_rx_b), - SH_PFC_PIN_GROUP(msiof2_tx_b), - SH_PFC_PIN_GROUP(msiof2_clk_c), - SH_PFC_PIN_GROUP(msiof2_sync_c), - SH_PFC_PIN_GROUP(msiof2_rx_c), - SH_PFC_PIN_GROUP(msiof2_tx_c), - SH_PFC_PIN_GROUP(msiof2_clk_d), - SH_PFC_PIN_GROUP(msiof2_sync_d), - SH_PFC_PIN_GROUP(msiof2_ss1_d), - SH_PFC_PIN_GROUP(msiof2_ss2_d), - SH_PFC_PIN_GROUP(msiof2_rx_d), - SH_PFC_PIN_GROUP(msiof2_tx_d), - SH_PFC_PIN_GROUP(msiof2_clk_e), - SH_PFC_PIN_GROUP(msiof2_sync_e), - SH_PFC_PIN_GROUP(msiof2_rx_e), - SH_PFC_PIN_GROUP(msiof2_tx_e), - SH_PFC_PIN_GROUP(pwm0), - SH_PFC_PIN_GROUP(pwm0_b), - SH_PFC_PIN_GROUP(pwm1), - SH_PFC_PIN_GROUP(pwm1_b), - SH_PFC_PIN_GROUP(pwm2), - SH_PFC_PIN_GROUP(pwm2_b), - SH_PFC_PIN_GROUP(pwm3), - SH_PFC_PIN_GROUP(pwm4), - SH_PFC_PIN_GROUP(pwm4_b), - SH_PFC_PIN_GROUP(pwm5), - SH_PFC_PIN_GROUP(pwm5_b), - SH_PFC_PIN_GROUP(pwm6), - SH_PFC_PIN_GROUP(qspi_ctrl), - SH_PFC_PIN_GROUP(qspi_data2), - SH_PFC_PIN_GROUP(qspi_data4), - SH_PFC_PIN_GROUP(qspi_ctrl_b), - SH_PFC_PIN_GROUP(qspi_data2_b), - SH_PFC_PIN_GROUP(qspi_data4_b), - SH_PFC_PIN_GROUP(scif0_data), - SH_PFC_PIN_GROUP(scif0_data_b), - SH_PFC_PIN_GROUP(scif0_data_c), - SH_PFC_PIN_GROUP(scif0_data_d), - SH_PFC_PIN_GROUP(scif0_data_e), - SH_PFC_PIN_GROUP(scif1_data), - SH_PFC_PIN_GROUP(scif1_data_b), - SH_PFC_PIN_GROUP(scif1_clk_b), - SH_PFC_PIN_GROUP(scif1_data_c), - SH_PFC_PIN_GROUP(scif1_data_d), - SH_PFC_PIN_GROUP(scif2_data), - SH_PFC_PIN_GROUP(scif2_data_b), - SH_PFC_PIN_GROUP(scif2_clk_b), - SH_PFC_PIN_GROUP(scif2_data_c), - SH_PFC_PIN_GROUP(scif2_data_e), - SH_PFC_PIN_GROUP(scif3_data), - SH_PFC_PIN_GROUP(scif3_clk), - SH_PFC_PIN_GROUP(scif3_data_b), - SH_PFC_PIN_GROUP(scif3_clk_b), - SH_PFC_PIN_GROUP(scif3_data_c), - SH_PFC_PIN_GROUP(scif3_data_d), - SH_PFC_PIN_GROUP(scif4_data), - SH_PFC_PIN_GROUP(scif4_data_b), - SH_PFC_PIN_GROUP(scif4_data_c), - SH_PFC_PIN_GROUP(scif5_data), - SH_PFC_PIN_GROUP(scif5_data_b), - SH_PFC_PIN_GROUP(scifa0_data), - SH_PFC_PIN_GROUP(scifa0_data_b), - SH_PFC_PIN_GROUP(scifa1_data), - SH_PFC_PIN_GROUP(scifa1_clk), - SH_PFC_PIN_GROUP(scifa1_data_b), - SH_PFC_PIN_GROUP(scifa1_clk_b), - SH_PFC_PIN_GROUP(scifa1_data_c), - SH_PFC_PIN_GROUP(scifa2_data), - SH_PFC_PIN_GROUP(scifa2_clk), - SH_PFC_PIN_GROUP(scifa2_data_b), - SH_PFC_PIN_GROUP(scifa3_data), - SH_PFC_PIN_GROUP(scifa3_clk), - SH_PFC_PIN_GROUP(scifa3_data_b), - SH_PFC_PIN_GROUP(scifa3_clk_b), - SH_PFC_PIN_GROUP(scifa3_data_c), - SH_PFC_PIN_GROUP(scifa3_clk_c), - SH_PFC_PIN_GROUP(scifa4_data), - SH_PFC_PIN_GROUP(scifa4_data_b), - SH_PFC_PIN_GROUP(scifa4_data_c), - SH_PFC_PIN_GROUP(scifa5_data), - SH_PFC_PIN_GROUP(scifa5_data_b), - SH_PFC_PIN_GROUP(scifa5_data_c), - SH_PFC_PIN_GROUP(scifb0_data), - SH_PFC_PIN_GROUP(scifb0_clk), - SH_PFC_PIN_GROUP(scifb0_ctrl), - SH_PFC_PIN_GROUP(scifb0_data_b), - SH_PFC_PIN_GROUP(scifb0_clk_b), - SH_PFC_PIN_GROUP(scifb0_ctrl_b), - SH_PFC_PIN_GROUP(scifb0_data_c), - SH_PFC_PIN_GROUP(scifb0_clk_c), - SH_PFC_PIN_GROUP(scifb0_data_d), - SH_PFC_PIN_GROUP(scifb0_clk_d), - SH_PFC_PIN_GROUP(scifb1_data), - SH_PFC_PIN_GROUP(scifb1_clk), - SH_PFC_PIN_GROUP(scifb1_ctrl), - SH_PFC_PIN_GROUP(scifb1_data_b), - SH_PFC_PIN_GROUP(scifb1_clk_b), - SH_PFC_PIN_GROUP(scifb1_data_c), - SH_PFC_PIN_GROUP(scifb1_clk_c), - SH_PFC_PIN_GROUP(scifb1_data_d), - SH_PFC_PIN_GROUP(scifb2_data), - SH_PFC_PIN_GROUP(scifb2_clk), - SH_PFC_PIN_GROUP(scifb2_ctrl), - SH_PFC_PIN_GROUP(scifb2_data_b), - SH_PFC_PIN_GROUP(scifb2_clk_b), - SH_PFC_PIN_GROUP(scifb2_ctrl_b), - SH_PFC_PIN_GROUP(scifb2_data_c), - SH_PFC_PIN_GROUP(scifb2_clk_c), - SH_PFC_PIN_GROUP(scifb2_data_d), - SH_PFC_PIN_GROUP(scif_clk), - SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), - SH_PFC_PIN_GROUP(sdhi0_ctrl), - SH_PFC_PIN_GROUP(sdhi0_cd), - SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), - SH_PFC_PIN_GROUP(sdhi1_ctrl), - SH_PFC_PIN_GROUP(sdhi1_cd), - SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), - SH_PFC_PIN_GROUP(sdhi2_ctrl), - SH_PFC_PIN_GROUP(sdhi2_cd), - SH_PFC_PIN_GROUP(sdhi2_wp), - SH_PFC_PIN_GROUP(ssi0_data), - SH_PFC_PIN_GROUP(ssi0_data_b), - SH_PFC_PIN_GROUP(ssi0129_ctrl), - SH_PFC_PIN_GROUP(ssi0129_ctrl_b), - SH_PFC_PIN_GROUP(ssi1_data), - SH_PFC_PIN_GROUP(ssi1_data_b), - SH_PFC_PIN_GROUP(ssi1_ctrl), - SH_PFC_PIN_GROUP(ssi1_ctrl_b), - SH_PFC_PIN_GROUP(ssi2_data), - SH_PFC_PIN_GROUP(ssi2_ctrl), - SH_PFC_PIN_GROUP(ssi3_data), - SH_PFC_PIN_GROUP(ssi34_ctrl), - SH_PFC_PIN_GROUP(ssi4_data), - SH_PFC_PIN_GROUP(ssi4_ctrl), - SH_PFC_PIN_GROUP(ssi5_data), - SH_PFC_PIN_GROUP(ssi5_ctrl), - SH_PFC_PIN_GROUP(ssi6_data), - SH_PFC_PIN_GROUP(ssi6_ctrl), - SH_PFC_PIN_GROUP(ssi7_data), - SH_PFC_PIN_GROUP(ssi7_data_b), - SH_PFC_PIN_GROUP(ssi78_ctrl), - SH_PFC_PIN_GROUP(ssi78_ctrl_b), - SH_PFC_PIN_GROUP(ssi8_data), - SH_PFC_PIN_GROUP(ssi8_data_b), - SH_PFC_PIN_GROUP(ssi9_data), - SH_PFC_PIN_GROUP(ssi9_data_b), - SH_PFC_PIN_GROUP(ssi9_ctrl), - SH_PFC_PIN_GROUP(ssi9_ctrl_b), - SH_PFC_PIN_GROUP(usb0), - SH_PFC_PIN_GROUP(usb1), - VIN_DATA_PIN_GROUP(vin0_data, 24), - VIN_DATA_PIN_GROUP(vin0_data, 20), - SH_PFC_PIN_GROUP(vin0_data18), - VIN_DATA_PIN_GROUP(vin0_data, 16), - VIN_DATA_PIN_GROUP(vin0_data, 12), - VIN_DATA_PIN_GROUP(vin0_data, 10), - VIN_DATA_PIN_GROUP(vin0_data, 8), - SH_PFC_PIN_GROUP(vin0_sync), - SH_PFC_PIN_GROUP(vin0_field), - SH_PFC_PIN_GROUP(vin0_clkenb), - SH_PFC_PIN_GROUP(vin0_clk), - SH_PFC_PIN_GROUP(vin1_data8), - SH_PFC_PIN_GROUP(vin1_sync), - SH_PFC_PIN_GROUP(vin1_field), - SH_PFC_PIN_GROUP(vin1_clkenb), - SH_PFC_PIN_GROUP(vin1_clk), - VIN_DATA_PIN_GROUP(vin1_b_data, 24), - VIN_DATA_PIN_GROUP(vin1_b_data, 20), - SH_PFC_PIN_GROUP(vin1_b_data18), - VIN_DATA_PIN_GROUP(vin1_b_data, 16), - VIN_DATA_PIN_GROUP(vin1_b_data, 12), - VIN_DATA_PIN_GROUP(vin1_b_data, 10), - VIN_DATA_PIN_GROUP(vin1_b_data, 8), - SH_PFC_PIN_GROUP(vin1_b_sync), - SH_PFC_PIN_GROUP(vin1_b_field), - SH_PFC_PIN_GROUP(vin1_b_clkenb), - SH_PFC_PIN_GROUP(vin1_b_clk), - SH_PFC_PIN_GROUP(vin2_data8), - SH_PFC_PIN_GROUP(vin2_sync), - SH_PFC_PIN_GROUP(vin2_field), - SH_PFC_PIN_GROUP(vin2_clkenb), - SH_PFC_PIN_GROUP(vin2_clk), +static const struct { + struct sh_pfc_pin_group common[341]; + struct sh_pfc_pin_group r8a779x[9]; +} pinmux_groups = { + .common = { + SH_PFC_PIN_GROUP(audio_clk_a), + SH_PFC_PIN_GROUP(audio_clk_b), + SH_PFC_PIN_GROUP(audio_clk_b_b), + SH_PFC_PIN_GROUP(audio_clk_c), + SH_PFC_PIN_GROUP(audio_clkout), + SH_PFC_PIN_GROUP(avb_link), + SH_PFC_PIN_GROUP(avb_magic), + SH_PFC_PIN_GROUP(avb_phy_int), + SH_PFC_PIN_GROUP(avb_mdio), + SH_PFC_PIN_GROUP(avb_mii), + SH_PFC_PIN_GROUP(avb_gmii), + SH_PFC_PIN_GROUP(can0_data), + SH_PFC_PIN_GROUP(can0_data_b), + SH_PFC_PIN_GROUP(can0_data_c), + SH_PFC_PIN_GROUP(can0_data_d), + SH_PFC_PIN_GROUP(can0_data_e), + SH_PFC_PIN_GROUP(can0_data_f), + SH_PFC_PIN_GROUP(can1_data), + SH_PFC_PIN_GROUP(can1_data_b), + SH_PFC_PIN_GROUP(can1_data_c), + SH_PFC_PIN_GROUP(can1_data_d), + SH_PFC_PIN_GROUP(can_clk), + SH_PFC_PIN_GROUP(can_clk_b), + SH_PFC_PIN_GROUP(can_clk_c), + SH_PFC_PIN_GROUP(can_clk_d), + SH_PFC_PIN_GROUP(du_rgb666), + SH_PFC_PIN_GROUP(du_rgb888), + SH_PFC_PIN_GROUP(du_clk_out_0), + SH_PFC_PIN_GROUP(du_clk_out_1), + SH_PFC_PIN_GROUP(du_sync), + SH_PFC_PIN_GROUP(du_oddf), + SH_PFC_PIN_GROUP(du_cde), + SH_PFC_PIN_GROUP(du_disp), + SH_PFC_PIN_GROUP(du0_clk_in), + SH_PFC_PIN_GROUP(du1_clk_in), + SH_PFC_PIN_GROUP(du1_clk_in_b), + SH_PFC_PIN_GROUP(du1_clk_in_c), + SH_PFC_PIN_GROUP(eth_link), + SH_PFC_PIN_GROUP(eth_magic), + SH_PFC_PIN_GROUP(eth_mdio), + SH_PFC_PIN_GROUP(eth_rmii), + SH_PFC_PIN_GROUP(hscif0_data), + SH_PFC_PIN_GROUP(hscif0_clk), + SH_PFC_PIN_GROUP(hscif0_ctrl), + SH_PFC_PIN_GROUP(hscif0_data_b), + SH_PFC_PIN_GROUP(hscif0_ctrl_b), + SH_PFC_PIN_GROUP(hscif0_data_c), + SH_PFC_PIN_GROUP(hscif0_clk_c), + SH_PFC_PIN_GROUP(hscif1_data), + SH_PFC_PIN_GROUP(hscif1_clk), + SH_PFC_PIN_GROUP(hscif1_ctrl), + SH_PFC_PIN_GROUP(hscif1_data_b), + SH_PFC_PIN_GROUP(hscif1_data_c), + SH_PFC_PIN_GROUP(hscif1_clk_c), + SH_PFC_PIN_GROUP(hscif1_ctrl_c), + SH_PFC_PIN_GROUP(hscif1_data_d), + SH_PFC_PIN_GROUP(hscif1_data_e), + SH_PFC_PIN_GROUP(hscif1_clk_e), + SH_PFC_PIN_GROUP(hscif1_ctrl_e), + SH_PFC_PIN_GROUP(hscif2_data), + SH_PFC_PIN_GROUP(hscif2_clk), + SH_PFC_PIN_GROUP(hscif2_ctrl), + SH_PFC_PIN_GROUP(hscif2_data_b), + SH_PFC_PIN_GROUP(hscif2_ctrl_b), + SH_PFC_PIN_GROUP(hscif2_data_c), + SH_PFC_PIN_GROUP(hscif2_clk_c), + SH_PFC_PIN_GROUP(hscif2_data_d), + SH_PFC_PIN_GROUP(i2c0), + SH_PFC_PIN_GROUP(i2c0_b), + SH_PFC_PIN_GROUP(i2c0_c), + SH_PFC_PIN_GROUP(i2c1), + SH_PFC_PIN_GROUP(i2c1_b), + SH_PFC_PIN_GROUP(i2c1_c), + SH_PFC_PIN_GROUP(i2c1_d), + SH_PFC_PIN_GROUP(i2c1_e), + SH_PFC_PIN_GROUP(i2c2), + SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c2_c), + SH_PFC_PIN_GROUP(i2c2_d), + SH_PFC_PIN_GROUP(i2c3), + SH_PFC_PIN_GROUP(i2c3_b), + SH_PFC_PIN_GROUP(i2c3_c), + SH_PFC_PIN_GROUP(i2c3_d), + SH_PFC_PIN_GROUP(i2c4), + SH_PFC_PIN_GROUP(i2c4_b), + SH_PFC_PIN_GROUP(i2c4_c), + SH_PFC_PIN_GROUP(i2c8), + SH_PFC_PIN_GROUP(i2c8_b), + SH_PFC_PIN_GROUP(i2c8_c), + SH_PFC_PIN_GROUP(i2c8), + SH_PFC_PIN_GROUP(i2c8_b), + SH_PFC_PIN_GROUP(i2c8_c), + SH_PFC_PIN_GROUP(intc_irq0), + SH_PFC_PIN_GROUP(intc_irq1), + SH_PFC_PIN_GROUP(intc_irq2), + SH_PFC_PIN_GROUP(intc_irq3), + SH_PFC_PIN_GROUP(mmc_data1), + SH_PFC_PIN_GROUP(mmc_data4), + SH_PFC_PIN_GROUP(mmc_data8), + SH_PFC_PIN_GROUP(mmc_ctrl), + SH_PFC_PIN_GROUP(msiof0_clk), + SH_PFC_PIN_GROUP(msiof0_sync), + SH_PFC_PIN_GROUP(msiof0_ss1), + SH_PFC_PIN_GROUP(msiof0_ss2), + SH_PFC_PIN_GROUP(msiof0_rx), + SH_PFC_PIN_GROUP(msiof0_tx), + SH_PFC_PIN_GROUP(msiof0_clk_b), + SH_PFC_PIN_GROUP(msiof0_sync_b), + SH_PFC_PIN_GROUP(msiof0_ss1_b), + SH_PFC_PIN_GROUP(msiof0_ss2_b), + SH_PFC_PIN_GROUP(msiof0_rx_b), + SH_PFC_PIN_GROUP(msiof0_tx_b), + SH_PFC_PIN_GROUP(msiof0_clk_c), + SH_PFC_PIN_GROUP(msiof0_sync_c), + SH_PFC_PIN_GROUP(msiof0_ss1_c), + SH_PFC_PIN_GROUP(msiof0_ss2_c), + SH_PFC_PIN_GROUP(msiof0_rx_c), + SH_PFC_PIN_GROUP(msiof0_tx_c), + SH_PFC_PIN_GROUP(msiof1_clk), + SH_PFC_PIN_GROUP(msiof1_sync), + SH_PFC_PIN_GROUP(msiof1_ss1), + SH_PFC_PIN_GROUP(msiof1_ss2), + SH_PFC_PIN_GROUP(msiof1_rx), + SH_PFC_PIN_GROUP(msiof1_tx), + SH_PFC_PIN_GROUP(msiof1_clk_b), + SH_PFC_PIN_GROUP(msiof1_sync_b), + SH_PFC_PIN_GROUP(msiof1_ss1_b), + SH_PFC_PIN_GROUP(msiof1_ss2_b), + SH_PFC_PIN_GROUP(msiof1_rx_b), + SH_PFC_PIN_GROUP(msiof1_tx_b), + SH_PFC_PIN_GROUP(msiof1_clk_c), + SH_PFC_PIN_GROUP(msiof1_sync_c), + SH_PFC_PIN_GROUP(msiof1_rx_c), + SH_PFC_PIN_GROUP(msiof1_tx_c), + SH_PFC_PIN_GROUP(msiof1_clk_d), + SH_PFC_PIN_GROUP(msiof1_sync_d), + SH_PFC_PIN_GROUP(msiof1_ss1_d), + SH_PFC_PIN_GROUP(msiof1_rx_d), + SH_PFC_PIN_GROUP(msiof1_tx_d), + SH_PFC_PIN_GROUP(msiof1_clk_e), + SH_PFC_PIN_GROUP(msiof1_sync_e), + SH_PFC_PIN_GROUP(msiof1_rx_e), + SH_PFC_PIN_GROUP(msiof1_tx_e), + SH_PFC_PIN_GROUP(msiof2_clk), + SH_PFC_PIN_GROUP(msiof2_sync), + SH_PFC_PIN_GROUP(msiof2_ss1), + SH_PFC_PIN_GROUP(msiof2_ss2), + SH_PFC_PIN_GROUP(msiof2_rx), + SH_PFC_PIN_GROUP(msiof2_tx), + SH_PFC_PIN_GROUP(msiof2_clk_b), + SH_PFC_PIN_GROUP(msiof2_sync_b), + SH_PFC_PIN_GROUP(msiof2_ss1_b), + SH_PFC_PIN_GROUP(msiof2_ss2_b), + SH_PFC_PIN_GROUP(msiof2_rx_b), + SH_PFC_PIN_GROUP(msiof2_tx_b), + SH_PFC_PIN_GROUP(msiof2_clk_c), + SH_PFC_PIN_GROUP(msiof2_sync_c), + SH_PFC_PIN_GROUP(msiof2_rx_c), + SH_PFC_PIN_GROUP(msiof2_tx_c), + SH_PFC_PIN_GROUP(msiof2_clk_d), + SH_PFC_PIN_GROUP(msiof2_sync_d), + SH_PFC_PIN_GROUP(msiof2_ss1_d), + SH_PFC_PIN_GROUP(msiof2_ss2_d), + SH_PFC_PIN_GROUP(msiof2_rx_d), + SH_PFC_PIN_GROUP(msiof2_tx_d), + SH_PFC_PIN_GROUP(msiof2_clk_e), + SH_PFC_PIN_GROUP(msiof2_sync_e), + SH_PFC_PIN_GROUP(msiof2_rx_e), + SH_PFC_PIN_GROUP(msiof2_tx_e), + SH_PFC_PIN_GROUP(pwm0), + SH_PFC_PIN_GROUP(pwm0_b), + SH_PFC_PIN_GROUP(pwm1), + SH_PFC_PIN_GROUP(pwm1_b), + SH_PFC_PIN_GROUP(pwm2), + SH_PFC_PIN_GROUP(pwm2_b), + SH_PFC_PIN_GROUP(pwm3), + SH_PFC_PIN_GROUP(pwm4), + SH_PFC_PIN_GROUP(pwm4_b), + SH_PFC_PIN_GROUP(pwm5), + SH_PFC_PIN_GROUP(pwm5_b), + SH_PFC_PIN_GROUP(pwm6), + SH_PFC_PIN_GROUP(qspi_ctrl), + SH_PFC_PIN_GROUP(qspi_data2), + SH_PFC_PIN_GROUP(qspi_data4), + SH_PFC_PIN_GROUP(qspi_ctrl_b), + SH_PFC_PIN_GROUP(qspi_data2_b), + SH_PFC_PIN_GROUP(qspi_data4_b), + SH_PFC_PIN_GROUP(scif0_data), + SH_PFC_PIN_GROUP(scif0_data_b), + SH_PFC_PIN_GROUP(scif0_data_c), + SH_PFC_PIN_GROUP(scif0_data_d), + SH_PFC_PIN_GROUP(scif0_data_e), + SH_PFC_PIN_GROUP(scif1_data), + SH_PFC_PIN_GROUP(scif1_data_b), + SH_PFC_PIN_GROUP(scif1_clk_b), + SH_PFC_PIN_GROUP(scif1_data_c), + SH_PFC_PIN_GROUP(scif1_data_d), + SH_PFC_PIN_GROUP(scif2_data), + SH_PFC_PIN_GROUP(scif2_data_b), + SH_PFC_PIN_GROUP(scif2_clk_b), + SH_PFC_PIN_GROUP(scif2_data_c), + SH_PFC_PIN_GROUP(scif2_data_e), + SH_PFC_PIN_GROUP(scif3_data), + SH_PFC_PIN_GROUP(scif3_clk), + SH_PFC_PIN_GROUP(scif3_data_b), + SH_PFC_PIN_GROUP(scif3_clk_b), + SH_PFC_PIN_GROUP(scif3_data_c), + SH_PFC_PIN_GROUP(scif3_data_d), + SH_PFC_PIN_GROUP(scif4_data), + SH_PFC_PIN_GROUP(scif4_data_b), + SH_PFC_PIN_GROUP(scif4_data_c), + SH_PFC_PIN_GROUP(scif5_data), + SH_PFC_PIN_GROUP(scif5_data_b), + SH_PFC_PIN_GROUP(scifa0_data), + SH_PFC_PIN_GROUP(scifa0_data_b), + SH_PFC_PIN_GROUP(scifa1_data), + SH_PFC_PIN_GROUP(scifa1_clk), + SH_PFC_PIN_GROUP(scifa1_data_b), + SH_PFC_PIN_GROUP(scifa1_clk_b), + SH_PFC_PIN_GROUP(scifa1_data_c), + SH_PFC_PIN_GROUP(scifa2_data), + SH_PFC_PIN_GROUP(scifa2_clk), + SH_PFC_PIN_GROUP(scifa2_data_b), + SH_PFC_PIN_GROUP(scifa3_data), + SH_PFC_PIN_GROUP(scifa3_clk), + SH_PFC_PIN_GROUP(scifa3_data_b), + SH_PFC_PIN_GROUP(scifa3_clk_b), + SH_PFC_PIN_GROUP(scifa3_data_c), + SH_PFC_PIN_GROUP(scifa3_clk_c), + SH_PFC_PIN_GROUP(scifa4_data), + SH_PFC_PIN_GROUP(scifa4_data_b), + SH_PFC_PIN_GROUP(scifa4_data_c), + SH_PFC_PIN_GROUP(scifa5_data), + SH_PFC_PIN_GROUP(scifa5_data_b), + SH_PFC_PIN_GROUP(scifa5_data_c), + SH_PFC_PIN_GROUP(scifb0_data), + SH_PFC_PIN_GROUP(scifb0_clk), + SH_PFC_PIN_GROUP(scifb0_ctrl), + SH_PFC_PIN_GROUP(scifb0_data_b), + SH_PFC_PIN_GROUP(scifb0_clk_b), + SH_PFC_PIN_GROUP(scifb0_ctrl_b), + SH_PFC_PIN_GROUP(scifb0_data_c), + SH_PFC_PIN_GROUP(scifb0_clk_c), + SH_PFC_PIN_GROUP(scifb0_data_d), + SH_PFC_PIN_GROUP(scifb0_clk_d), + SH_PFC_PIN_GROUP(scifb1_data), + SH_PFC_PIN_GROUP(scifb1_clk), + SH_PFC_PIN_GROUP(scifb1_ctrl), + SH_PFC_PIN_GROUP(scifb1_data_b), + SH_PFC_PIN_GROUP(scifb1_clk_b), + SH_PFC_PIN_GROUP(scifb1_data_c), + SH_PFC_PIN_GROUP(scifb1_clk_c), + SH_PFC_PIN_GROUP(scifb1_data_d), + SH_PFC_PIN_GROUP(scifb2_data), + SH_PFC_PIN_GROUP(scifb2_clk), + SH_PFC_PIN_GROUP(scifb2_ctrl), + SH_PFC_PIN_GROUP(scifb2_data_b), + SH_PFC_PIN_GROUP(scifb2_clk_b), + SH_PFC_PIN_GROUP(scifb2_ctrl_b), + SH_PFC_PIN_GROUP(scifb2_data_c), + SH_PFC_PIN_GROUP(scifb2_clk_c), + SH_PFC_PIN_GROUP(scifb2_data_d), + SH_PFC_PIN_GROUP(scif_clk), + SH_PFC_PIN_GROUP(scif_clk_b), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi1_cd), + SH_PFC_PIN_GROUP(sdhi1_wp), + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(sdhi2_cd), + SH_PFC_PIN_GROUP(sdhi2_wp), + SH_PFC_PIN_GROUP(ssi0_data), + SH_PFC_PIN_GROUP(ssi0_data_b), + SH_PFC_PIN_GROUP(ssi0129_ctrl), + SH_PFC_PIN_GROUP(ssi0129_ctrl_b), + SH_PFC_PIN_GROUP(ssi1_data), + SH_PFC_PIN_GROUP(ssi1_data_b), + SH_PFC_PIN_GROUP(ssi1_ctrl), + SH_PFC_PIN_GROUP(ssi1_ctrl_b), + SH_PFC_PIN_GROUP(ssi2_data), + SH_PFC_PIN_GROUP(ssi2_ctrl), + SH_PFC_PIN_GROUP(ssi3_data), + SH_PFC_PIN_GROUP(ssi34_ctrl), + SH_PFC_PIN_GROUP(ssi4_data), + SH_PFC_PIN_GROUP(ssi4_ctrl), + SH_PFC_PIN_GROUP(ssi5_data), + SH_PFC_PIN_GROUP(ssi5_ctrl), + SH_PFC_PIN_GROUP(ssi6_data), + SH_PFC_PIN_GROUP(ssi6_ctrl), + SH_PFC_PIN_GROUP(ssi7_data), + SH_PFC_PIN_GROUP(ssi7_data_b), + SH_PFC_PIN_GROUP(ssi78_ctrl), + SH_PFC_PIN_GROUP(ssi78_ctrl_b), + SH_PFC_PIN_GROUP(ssi8_data), + SH_PFC_PIN_GROUP(ssi8_data_b), + SH_PFC_PIN_GROUP(ssi9_data), + SH_PFC_PIN_GROUP(ssi9_data_b), + SH_PFC_PIN_GROUP(ssi9_ctrl), + SH_PFC_PIN_GROUP(ssi9_ctrl_b), + SH_PFC_PIN_GROUP(usb0), + SH_PFC_PIN_GROUP(usb1), + VIN_DATA_PIN_GROUP(vin0_data, 24), + VIN_DATA_PIN_GROUP(vin0_data, 20), + SH_PFC_PIN_GROUP(vin0_data18), + VIN_DATA_PIN_GROUP(vin0_data, 16), + VIN_DATA_PIN_GROUP(vin0_data, 12), + VIN_DATA_PIN_GROUP(vin0_data, 10), + VIN_DATA_PIN_GROUP(vin0_data, 8), + SH_PFC_PIN_GROUP(vin0_sync), + SH_PFC_PIN_GROUP(vin0_field), + SH_PFC_PIN_GROUP(vin0_clkenb), + SH_PFC_PIN_GROUP(vin0_clk), + SH_PFC_PIN_GROUP(vin1_data8), + SH_PFC_PIN_GROUP(vin1_sync), + SH_PFC_PIN_GROUP(vin1_field), + SH_PFC_PIN_GROUP(vin1_clkenb), + SH_PFC_PIN_GROUP(vin1_clk), + VIN_DATA_PIN_GROUP(vin1_b_data, 24), + VIN_DATA_PIN_GROUP(vin1_b_data, 20), + SH_PFC_PIN_GROUP(vin1_b_data18), + VIN_DATA_PIN_GROUP(vin1_b_data, 16), + VIN_DATA_PIN_GROUP(vin1_b_data, 12), + VIN_DATA_PIN_GROUP(vin1_b_data, 10), + VIN_DATA_PIN_GROUP(vin1_b_data, 8), + SH_PFC_PIN_GROUP(vin1_b_sync), + SH_PFC_PIN_GROUP(vin1_b_field), + SH_PFC_PIN_GROUP(vin1_b_clkenb), + SH_PFC_PIN_GROUP(vin1_b_clk), + SH_PFC_PIN_GROUP(vin2_data8), + SH_PFC_PIN_GROUP(vin2_sync), + SH_PFC_PIN_GROUP(vin2_field), + SH_PFC_PIN_GROUP(vin2_clkenb), + SH_PFC_PIN_GROUP(vin2_clk), + }, + .r8a779x = { + SH_PFC_PIN_GROUP(adi_common), + SH_PFC_PIN_GROUP(adi_chsel0), + SH_PFC_PIN_GROUP(adi_chsel1), + SH_PFC_PIN_GROUP(adi_chsel2), + SH_PFC_PIN_GROUP(adi_common_b), + SH_PFC_PIN_GROUP(adi_chsel0_b), + SH_PFC_PIN_GROUP(adi_chsel1_b), + SH_PFC_PIN_GROUP(adi_chsel2_b), + SH_PFC_PIN_GROUP(mlb_3pin), + } }; +/* R8A779x only */ static const char * const adi_groups[] = { "adi_common", "adi_chsel0", @@ -4940,6 +5035,7 @@ static const char * const intc_groups[] "intc_irq3", }; +/* R8A779x only */ static const char * const mlb_groups[] = { "mlb_3pin", }; @@ -5287,65 +5383,72 @@ static const char * const vin2_groups[] "vin2_clk", }; -static const struct sh_pfc_function pinmux_functions[] = { - SH_PFC_FUNCTION(adi), - SH_PFC_FUNCTION(audio_clk), - SH_PFC_FUNCTION(avb), - SH_PFC_FUNCTION(can0), - SH_PFC_FUNCTION(can1), - SH_PFC_FUNCTION(du), - SH_PFC_FUNCTION(du0), - SH_PFC_FUNCTION(du1), - SH_PFC_FUNCTION(eth), - SH_PFC_FUNCTION(hscif0), - SH_PFC_FUNCTION(hscif1), - SH_PFC_FUNCTION(hscif2), - SH_PFC_FUNCTION(i2c0), - SH_PFC_FUNCTION(i2c1), - SH_PFC_FUNCTION(i2c2), - SH_PFC_FUNCTION(i2c3), - SH_PFC_FUNCTION(i2c4), - SH_PFC_FUNCTION(i2c7), - SH_PFC_FUNCTION(i2c8), - SH_PFC_FUNCTION(intc), - SH_PFC_FUNCTION(mlb), - SH_PFC_FUNCTION(mmc), - SH_PFC_FUNCTION(msiof0), - SH_PFC_FUNCTION(msiof1), - SH_PFC_FUNCTION(msiof2), - SH_PFC_FUNCTION(pwm0), - SH_PFC_FUNCTION(pwm1), - SH_PFC_FUNCTION(pwm2), - SH_PFC_FUNCTION(pwm3), - SH_PFC_FUNCTION(pwm4), - SH_PFC_FUNCTION(pwm5), - SH_PFC_FUNCTION(pwm6), - SH_PFC_FUNCTION(qspi), - SH_PFC_FUNCTION(scif0), - SH_PFC_FUNCTION(scif1), - SH_PFC_FUNCTION(scif2), - SH_PFC_FUNCTION(scif3), - SH_PFC_FUNCTION(scif4), - SH_PFC_FUNCTION(scif5), - SH_PFC_FUNCTION(scifa0), - SH_PFC_FUNCTION(scifa1), - SH_PFC_FUNCTION(scifa2), - SH_PFC_FUNCTION(scifa3), - SH_PFC_FUNCTION(scifa4), - SH_PFC_FUNCTION(scifa5), - SH_PFC_FUNCTION(scifb0), - SH_PFC_FUNCTION(scifb1), - SH_PFC_FUNCTION(scifb2), - SH_PFC_FUNCTION(scif_clk), - SH_PFC_FUNCTION(sdhi0), - SH_PFC_FUNCTION(sdhi1), - SH_PFC_FUNCTION(sdhi2), - SH_PFC_FUNCTION(ssi), - SH_PFC_FUNCTION(usb0), - SH_PFC_FUNCTION(usb1), - SH_PFC_FUNCTION(vin0), - SH_PFC_FUNCTION(vin1), - SH_PFC_FUNCTION(vin2), +static const struct { + struct sh_pfc_function common[56]; + struct sh_pfc_function r8a779x[2]; +} pinmux_functions = { + .common = { + SH_PFC_FUNCTION(audio_clk), + SH_PFC_FUNCTION(avb), + SH_PFC_FUNCTION(can0), + SH_PFC_FUNCTION(can1), + SH_PFC_FUNCTION(du), + SH_PFC_FUNCTION(du0), + SH_PFC_FUNCTION(du1), + SH_PFC_FUNCTION(eth), + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), + SH_PFC_FUNCTION(hscif2), + SH_PFC_FUNCTION(i2c0), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(i2c4), + SH_PFC_FUNCTION(i2c7), + SH_PFC_FUNCTION(i2c8), + SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(mmc), + SH_PFC_FUNCTION(msiof0), + SH_PFC_FUNCTION(msiof1), + SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(pwm0), + SH_PFC_FUNCTION(pwm1), + SH_PFC_FUNCTION(pwm2), + SH_PFC_FUNCTION(pwm3), + SH_PFC_FUNCTION(pwm4), + SH_PFC_FUNCTION(pwm5), + SH_PFC_FUNCTION(pwm6), + SH_PFC_FUNCTION(qspi), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scif2), + SH_PFC_FUNCTION(scif3), + SH_PFC_FUNCTION(scif4), + SH_PFC_FUNCTION(scif5), + SH_PFC_FUNCTION(scifa0), + SH_PFC_FUNCTION(scifa1), + SH_PFC_FUNCTION(scifa2), + SH_PFC_FUNCTION(scifa3), + SH_PFC_FUNCTION(scifa4), + SH_PFC_FUNCTION(scifa5), + SH_PFC_FUNCTION(scifb0), + SH_PFC_FUNCTION(scifb1), + SH_PFC_FUNCTION(scifb2), + SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(ssi), + SH_PFC_FUNCTION(usb0), + SH_PFC_FUNCTION(usb1), + SH_PFC_FUNCTION(vin0), + SH_PFC_FUNCTION(vin1), + SH_PFC_FUNCTION(vin2), + }, + .r8a779x = { + SH_PFC_FUNCTION(adi), + SH_PFC_FUNCTION(mlb), + } }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { @@ -6401,7 +6504,7 @@ static const struct pinmux_cfg_reg pinmu 0, 0, 0, 0, /* SEL_ADG [1] */ FN_SEL_ADG_0, FN_SEL_ADG_1, - /* SEL_FM [3] */ + /* SEL_FM [3] (R8A779x only) */ FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4, 0, 0, 0, @@ -6409,13 +6512,13 @@ static const struct pinmux_cfg_reg pinmu FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0, /* RESERVED [1] */ 0, 0, - /* SEL_GPS [2] */ + /* SEL_GPS [2] (R8A779x only) */ FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, /* SEL_SCIFA4 [2] */ FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0, /* SEL_SCIFA3 [2] */ FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0, - /* SEL_SIM [1] */ + /* SEL_SIM [1] (R8A779x only) */ FN_SEL_SIM_0, FN_SEL_SIM_1, /* RESERVED [1] */ 0, 0, @@ -6441,7 +6544,7 @@ static const struct pinmux_cfg_reg pinmu FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3, /* SEL_SCIF3 [2] */ FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, - /* SEL_IEB [2] */ + /* SEL_IEB [2] (R8A779x only) */ FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, /* SEL_MMC [1] */ FN_SEL_MMC_0, FN_SEL_MMC_1, @@ -6477,11 +6580,11 @@ static const struct pinmux_cfg_reg pinmu FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0, /* RESERVED [1] */ 0, 0, - /* SEL_RAD [1] */ + /* SEL_RAD [1] (R8A779x only) */ FN_SEL_RAD_0, FN_SEL_RAD_1, - /* SEL_RCN [1] */ + /* SEL_RCN [1] (R8A779x only) */ FN_SEL_RCN_0, FN_SEL_RCN_1, - /* SEL_RSP [1] */ + /* SEL_RSP [1] (R8A779x only) */ FN_SEL_RSP_0, FN_SEL_RSP_1, /* SEL_SCIF2 [3] */ FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, @@ -6501,7 +6604,7 @@ static const struct pinmux_cfg_reg pinmu FN_SEL_SSI1_0, FN_SEL_SSI1_1, /* SEL_SSI0 [1] */ FN_SEL_SSI0_0, FN_SEL_SSI0_1, - /* SEL_SSP [2] */ + /* SEL_SSP [2] (R8A779x only) */ FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0, /* RESERVED [2] */ 0, 0, 0, 0, @@ -6527,6 +6630,28 @@ static const struct sh_pfc_soc_operation .pin_to_pocctrl = r8a7791_pin_to_pocctrl, }; +#ifdef CONFIG_PINCTRL_PFC_R8A7743 +const struct sh_pfc_soc_info r8a7743_pinmux_info = { + .name = "r8a77430_pfc", + .ops = &r8a7791_pinmux_ops, + .unlock_reg = 0xe6060000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups.common, + .nr_groups = ARRAY_SIZE(pinmux_groups.common), + .functions = pinmux_functions.common, + .nr_functions = ARRAY_SIZE(pinmux_functions.common), + + .cfg_regs = pinmux_config_regs, + + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), +}; +#endif + #ifdef CONFIG_PINCTRL_PFC_R8A7791 const struct sh_pfc_soc_info r8a7791_pinmux_info = { .name = "r8a77910_pfc", @@ -6537,10 +6662,12 @@ const struct sh_pfc_soc_info r8a7791_pin .pins = pinmux_pins, .nr_pins = ARRAY_SIZE(pinmux_pins), - .groups = pinmux_groups, - .nr_groups = ARRAY_SIZE(pinmux_groups), - .functions = pinmux_functions, - .nr_functions = ARRAY_SIZE(pinmux_functions), + .groups = pinmux_groups.common, + .nr_groups = ARRAY_SIZE(pinmux_groups.common) + + ARRAY_SIZE(pinmux_groups.r8a779x), + .functions = pinmux_functions.common, + .nr_functions = ARRAY_SIZE(pinmux_functions.common) + + ARRAY_SIZE(pinmux_functions.r8a779x), .cfg_regs = pinmux_config_regs, @@ -6559,10 +6686,12 @@ const struct sh_pfc_soc_info r8a7793_pin .pins = pinmux_pins, .nr_pins = ARRAY_SIZE(pinmux_pins), - .groups = pinmux_groups, - .nr_groups = ARRAY_SIZE(pinmux_groups), - .functions = pinmux_functions, - .nr_functions = ARRAY_SIZE(pinmux_functions), + .groups = pinmux_groups.common, + .nr_groups = ARRAY_SIZE(pinmux_groups.common) + + ARRAY_SIZE(pinmux_groups.r8a779x), + .functions = pinmux_functions.common, + .nr_functions = ARRAY_SIZE(pinmux_functions.common) + + ARRAY_SIZE(pinmux_functions.r8a779x), .cfg_regs = pinmux_config_regs, Index: linux-pinctrl/drivers/pinctrl/sh-pfc/sh_pfc.h =================================================================== --- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/sh_pfc.h +++ linux-pinctrl/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -259,6 +259,7 @@ struct sh_pfc_soc_info { extern const struct sh_pfc_soc_info emev2_pinmux_info; extern const struct sh_pfc_soc_info r8a73a4_pinmux_info; extern const struct sh_pfc_soc_info r8a7740_pinmux_info; +extern const struct sh_pfc_soc_info r8a7743_pinmux_info; extern const struct sh_pfc_soc_info r8a7778_pinmux_info; extern const struct sh_pfc_soc_info r8a7779_pinmux_info; extern const struct sh_pfc_soc_info r8a7790_pinmux_info;

[v3] pinctrl: sh-pfc: r8a7791: add R8A7743 support

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