From patchwork Thu Mar 23 10:41:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 742597 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vpjls4XF7z9s3w for ; Thu, 23 Mar 2017 21:41:45 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="tKrJvX/R"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933747AbdCWKlc (ORCPT ); Thu, 23 Mar 2017 06:41:32 -0400 Received: from mail-wm0-f45.google.com ([74.125.82.45]:33999 "EHLO mail-wm0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933734AbdCWKl3 (ORCPT ); Thu, 23 Mar 2017 06:41:29 -0400 Received: by mail-wm0-f45.google.com with SMTP id w204so1149272wmd.1 for ; Thu, 23 Mar 2017 03:41:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tCvwLdRg9cGMRB9rtG4kgkVRcYA7QFhgQL0MJBPwuJs=; b=tKrJvX/RUsc+EMEQL6AOn+QHtEdwX1goGgudMJqCGuGGfCbjDSWibESAJXn05q4D2p hegEyH6Mx6Or36WhBTei2mConBsSE5sZGXg1+48alsyF5DmnkuiFpUqlA5Istc7cHZZj Xn0q/kLqAJQC0hh7zi9wq7MuRLMXA+EGGGcLEPg9IeBdV3rTaZ3SjJj6czpkpQjHnhQB yRB1Ho5oT5PHWmoKty1SkOL56x7K4HzrKBwAezBWJkT8ULUME/PVM0ghYn2l0HqQEeeL ggFZXkn2YdoxjClBUeLUImi8A1JOzeJAjfRYfQDATqQxW5hr2LshFirDbtJ0gMYFS/QV jaeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tCvwLdRg9cGMRB9rtG4kgkVRcYA7QFhgQL0MJBPwuJs=; b=YjjldAacVli3a8yS7pvR9AiNeQZcngHLl85x5zwlzKCQP2+j7PHVOP/1E9IuZhyWtq b7rHDXKLYPVUBOBpyd3w5eHASFh+062meZimkrqJVqlT3Z3wzang8xUVU2dp9YHbzdRw +IqPTjzdHW9PuLU/aW+HM8J8csBBXtoWrkwhxaXy4RmLPsYEshPQmIOqEPV75bhUVK29 O0mHQDR/EqHZ2fTtGL8HI6+qcuqqw4rui4rHccTHnL1WKzp2Bl/5h+ySBY1Zrvdjtb8Y 85ogoJn13rL8RaqTh3whUG+BmIOg6V9a1e+5RPAbd66CRuqo8aXRoJSpwM9esPvTTvbL WwqQ== X-Gm-Message-State: AFeK/H0qzJklHEfy0wzdzjJUMCFLkqgioJ5a0zcK4RwzxiK99Gya+5YEhy76wupanpqHXQOq X-Received: by 10.28.169.199 with SMTP id s190mr12049216wme.2.1490265677354; Thu, 23 Mar 2017 03:41:17 -0700 (PDT) Received: from build.net (build.baylibre.com. [37.187.146.144]) by smtp.gmail.com with ESMTPSA id b91sm5339871wrd.29.2017.03.23.03.41.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 23 Mar 2017 03:41:16 -0700 (PDT) From: Neil Armstrong To: khilman@baylibre.com, carlo@caione.org, linus.walleij@linaro.org Cc: Neil Armstrong , linux-gpio@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/2] ARM64: dts: meson-gxl: Add missing pinctrl pins groups Date: Thu, 23 Mar 2017 11:41:11 +0100 Message-Id: <20170323104112.16558-3-narmstrong@baylibre.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170323104112.16558-1-narmstrong@baylibre.com> References: <20170323104112.16558-1-narmstrong@baylibre.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add pinctrl pins nodes following the additions of missing pins in the pinctrl driver. Signed-off-by: Neil Armstrong Acked-by: Linus Walleij --- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 32 ++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index 79c387a..e05a6a1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -103,6 +103,13 @@ }; }; + uart_ao_b_0_1_pins: uart_ao_b_0_1 { + mux { + groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1"; + function = "uart_ao_b"; + }; + }; + uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { mux { groups = "uart_cts_ao_b", @@ -118,6 +125,14 @@ }; }; + i2c_ao_pins: i2c_ao { + mux { + groups = "i2c_sck_ao", + "i2c_sda_ao"; + function = "i2c_ao"; + }; + }; + pwm_ao_a_3_pins: pwm_ao_a_3 { mux { groups = "pwm_ao_a_3"; @@ -138,6 +153,13 @@ function = "pwm_ao_b"; }; }; + + pwm_ao_b_6_pins: pwm_ao_b_6 { + mux { + groups = "pwm_ao_b_6"; + function = "pwm_ao_b"; + }; + }; }; }; @@ -168,6 +190,16 @@ }; }; + nor_pins: nor { + mux { + groups = "nor_d", + "nor_q", + "nor_c", + "nor_cs"; + function = "nor"; + }; + }; + sdcard_pins: sdcard { mux { groups = "sdcard_d0",