From patchwork Mon Mar 14 14:26:07 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mika Westerberg X-Patchwork-Id: 597053 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3qP0RV0jPpz9t0t for ; Tue, 15 Mar 2016 01:26:14 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933247AbcCNO0M (ORCPT ); Mon, 14 Mar 2016 10:26:12 -0400 Received: from mga02.intel.com ([134.134.136.20]:6790 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932864AbcCNO0M (ORCPT ); Mon, 14 Mar 2016 10:26:12 -0400 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP; 14 Mar 2016 07:26:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,335,1455004800"; d="scan'208";a="923675582" Received: from lahna.fi.intel.com (HELO lahna) ([10.237.72.56]) by fmsmga001.fm.intel.com with SMTP; 14 Mar 2016 07:26:08 -0700 Received: by lahna (sSMTP sendmail emulation); Mon, 14 Mar 2016 16:26:07 +0200 Date: Mon, 14 Mar 2016 16:26:07 +0200 From: "Westerberg, Mika" To: Linus Walleij Cc: "Zheng, Qi" , "Zha, Qipeng" , "linux-gpio@vger.kernel.org" Subject: Re: [PATCH 2/3] pinctrl:Intel: clear interrupt status for every IRQ setup Message-ID: <20160314142607.GI1793@lahna.fi.intel.com> References: <1457715962-108484-1-git-send-email-qipeng.zha@intel.com> <1457715962-108484-2-git-send-email-qipeng.zha@intel.com> <20160311094517.GO1796@lahna.fi.intel.com> <0DD381DBF8F68D419C32ACFCEB28EB2521D10345@SHSMSX101.ccr.corp.intel.com> <20160314084457.GX1796@lahna.fi.intel.com> <20160314125436.GG1793@lahna.fi.intel.com> <20160314130041.GH1793@lahna.fi.intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20160314130041.GH1793@lahna.fi.intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Mon, Mar 14, 2016 at 03:00:41PM +0200, Westerberg, Mika wrote: > > > > Your set_type() is supporting edges but have all IRQs > > > handled by handle_simple_irq() rather than handle_edge_irq() > > > for the edges, which gives a more robust control flow > > > from IRQ to ACK to calling the handler. > > > > > > Zheng/Mika: please look at how the level/edge > > > IRQs are handled in drivers/gpio/gpio-pl061.c > > > where I *tried* to do things right, switching handler > > > in .set_type() using irq_set_handler_locked(). I think > > > you may need to use handle_edge_irq() for the edge IRQs > > > and handle_level_irq() for the level IRQs just like I do > > > in the PL061 driver. > > > > The driver is already doing that as far as I can tell (see > > intel_gpio_irq_type()). > > I will check again if we are still missing something there. Maybe we can implement ->enable() that clears the status right before interrupt is unmasked? Something like below. --- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index c0f5586218c4..b4873a4e25d5 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -648,6 +648,33 @@ static const struct gpio_chip intel_gpio_chip = { .set = intel_gpio_set, }; +static void intel_gpio_irq_enable(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct intel_pinctrl *pctrl = gpiochip_get_data(gc); + const struct intel_community *community; + unsigned pin = irqd_to_hwirq(d); + unsigned long flags; + + spin_lock_irqsave(&pctrl->lock, flags); + + community = intel_get_community(pctrl, pin); + if (community) { + unsigned padno = pin_to_padno(community, pin); + unsigned gpp_offset = padno % community->gpp_size; + unsigned gpp = padno / community->gpp_size; + unsigned value; + + writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4); + + value = readl(community->regs + community->ie_offset + gpp * 4); + value |= BIT(gpp_offset); + writel(value, community->regs + community->ie_offset + gpp * 4); + } + + spin_unlock_irqrestore(&pctrl->lock, flags); +} + static void intel_gpio_irq_ack(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); @@ -856,6 +883,7 @@ static irqreturn_t intel_gpio_irq(int irq, void *data) static struct irq_chip intel_gpio_irqchip = { .name = "intel-gpio", + .irq_enable = intel_gpio_irq_enable, .irq_ack = intel_gpio_irq_ack, .irq_mask = intel_gpio_irq_mask, .irq_unmask = intel_gpio_irq_unmask,