From patchwork Fri Sep 21 11:55:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 973187 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42GsVW6RGMz9sCc for ; Fri, 21 Sep 2018 21:55:31 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390142AbeIURoB (ORCPT ); Fri, 21 Sep 2018 13:44:01 -0400 Received: from relmlor3.renesas.com ([210.160.252.173]:23472 "EHLO relmlie2.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2390100AbeIURoA (ORCPT ); Fri, 21 Sep 2018 13:44:00 -0400 Received: from unknown (HELO relmlir1.idc.renesas.com) ([10.200.68.151]) by relmlie2.idc.renesas.com with ESMTP; 21 Sep 2018 20:55:27 +0900 Received: from relmlii1.idc.renesas.com (relmlii1.idc.renesas.com [10.200.68.65]) by relmlir1.idc.renesas.com (Postfix) with ESMTP id B320187A95; Fri, 21 Sep 2018 20:55:27 +0900 (JST) X-IronPort-AV: E=Sophos;i="5.54,284,1534777200"; d="scan'208";a="291574207" Received: from unknown (HELO fabrizio-dev.ree.adwin.renesas.com) ([10.226.36.250]) by relmlii1.idc.renesas.com with ESMTP; 21 Sep 2018 20:55:23 +0900 From: Fabrizio Castro To: Ulf Hansson , Rob Herring , Mark Rutland , Laurent Pinchart , Geert Uytterhoeven , Linus Walleij , Wolfram Sang Cc: Fabrizio Castro , Simon Horman , Magnus Damm , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Chris Paterson , Biju Das Subject: [PATCH 2/4] pinctrl: sh-pfc: r8a77470: Add SDHI2 voltage switch Date: Fri, 21 Sep 2018 12:55:09 +0100 Message-Id: <1537530911-443-3-git-send-email-fabrizio.castro@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1537530911-443-1-git-send-email-fabrizio.castro@bp.renesas.com> References: <1537530911-443-1-git-send-email-fabrizio.castro@bp.renesas.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add SH_PFC_PIN_CFG_IO_VOLTAGE definition for the SDHI2 pins capable of switching voltage. Please note that with the RZ/G1C only 1 bit of the POC Control Register is used to control each interface. Signed-off-by: Fabrizio Castro Reviewed-by: Biju Das Acked-by: Wolfram Sang --- drivers/pinctrl/sh-pfc/pfc-r8a77470.c | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c index 9d3ed43..a1248e2 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c @@ -17,7 +17,19 @@ PORT_GP_1(3, 27, fn, sfx), \ PORT_GP_1(3, 28, fn, sfx), \ PORT_GP_1(3, 29, fn, sfx), \ - PORT_GP_26(4, fn, sfx), \ + PORT_GP_14(4, fn, sfx), \ + PORT_GP_CFG_1(4, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(4, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(4, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(4, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(4, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(4, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_1(4, 20, fn, sfx), \ + PORT_GP_1(4, 21, fn, sfx), \ + PORT_GP_1(4, 22, fn, sfx), \ + PORT_GP_1(4, 23, fn, sfx), \ + PORT_GP_1(4, 24, fn, sfx), \ + PORT_GP_1(4, 25, fn, sfx), \ PORT_GP_32(5, fn, sfx) enum { @@ -2321,9 +2333,27 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; +static int r8a77470_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, + u32 *pocctrl) +{ + unsigned int _bank = pin >> 5; + unsigned int _pin = pin & 0x1f; + *pocctrl = 0xe60600b0; + + if (_bank == 4 && _pin >= 14 && _pin <= 19) + return 1; + + return -EINVAL; +} + +static const struct sh_pfc_soc_operations r8a77470_pinmux_ops = { + .pin_to_pocctrl = r8a77470_pin_to_pocctrl, +}; + #ifdef CONFIG_PINCTRL_PFC_R8A77470 const struct sh_pfc_soc_info r8a77470_pinmux_info = { .name = "r8a77470_pfc", + .ops = &r8a77470_pinmux_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },