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Signed-off-by: Abel Vesa Suggested-by: Sascha Hauer --- drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-composite.c | 126 ++++++++++++++++++++++++++++++++++++++++ drivers/clk/imx/clk.h | 9 +++ 3 files changed, 136 insertions(+) create mode 100644 drivers/clk/imx/clk-composite.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index b87513c..4fabb0a 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -3,6 +3,7 @@ obj-y += \ clk.o \ clk-busy.o \ + clk-composite.o \ clk-cpu.o \ clk-fixup-div.o \ clk-fixup-mux.o \ diff --git a/drivers/clk/imx/clk-composite.c b/drivers/clk/imx/clk-composite.c new file mode 100644 index 0000000..717c6f1 --- /dev/null +++ b/drivers/clk/imx/clk-composite.c @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2018 NXP + */ + +#include +#include +#include +#include + +#include "clk.h" + +#define PCG_PREDIV_SHIFT 16 +#define PCG_PREDIV_WIDTH 3 + +#define PCG_DIV_SHIFT 0 +#define PCG_DIV_WIDTH 6 + +#define PCG_PCS_SHIFT 24 +#define PCG_PCS_MASK 0x7 + +#define PCG_CGC_SHIFT 28 + +static unsigned long imx_clk_composite_divider_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return clk_divider_ops.recalc_rate(hw, parent_rate); +} + +static long imx_clk_composite_divider_round_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long *prate) +{ + return clk_divider_ops.round_rate(hw, rate, prate); +} + +static int imx_clk_composite_divider_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + struct clk_divider *divider = to_clk_divider(hw); + int value; + unsigned long flags = 0; + u32 val; + + value = divider_get_val(rate, parent_rate, NULL, + PCG_PREDIV_WIDTH, CLK_DIVIDER_ROUND_CLOSEST); + if (value < 0) + return value; + + spin_lock_irqsave(divider->lock, flags); + + val = clk_readl(divider->reg); + val &= ~((clk_div_mask(divider->width) << divider->shift) | + (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT)); + + val |= (u32)value << divider->shift; + val |= (u32)value << PCG_DIV_SHIFT; + clk_writel(val, divider->reg); + + spin_unlock_irqrestore(divider->lock, flags); + + return 0; +} + +static const struct clk_ops imx_clk_composite_divider_ops = { + .recalc_rate = imx_clk_composite_divider_recalc_rate, + .round_rate = imx_clk_composite_divider_round_rate, + .set_rate = imx_clk_composite_divider_set_rate, +}; + +struct clk *imx_clk_composite_flags(const char *name, + const char **parent_names, + int num_parents, void __iomem *reg, + unsigned long flags) +{ + struct clk_hw *mux_hw = NULL, *div_hw = NULL, *gate_hw = NULL; + struct clk_divider *div = NULL; + struct clk_gate *gate = NULL; + struct clk_mux *mux = NULL; + struct clk *clk; + + mux = kzalloc(sizeof(*mux), GFP_KERNEL); + if (!mux) + return ERR_PTR(-ENOMEM); + mux_hw = &mux->hw; + mux->reg = reg; + mux->shift = PCG_PCS_SHIFT; + mux->mask = PCG_PCS_MASK; + + div = kzalloc(sizeof(*div), GFP_KERNEL); + if (!div) { + kfree(mux); + return ERR_PTR(-ENOMEM); + } + div_hw = &div->hw; + div->reg = reg; + div->shift = PCG_PREDIV_SHIFT; + div->width = PCG_PREDIV_WIDTH; + div->lock = &imx_ccm_lock; + div->flags = CLK_DIVIDER_ROUND_CLOSEST; + + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) { + kfree(mux); + kfree(div); + return ERR_PTR(-ENOMEM); + } + gate_hw = &gate->hw; + gate->reg = reg; + gate->bit_idx = PCG_CGC_SHIFT; + + flags |= CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE; + + clk = clk_register_composite(NULL, name, parent_names, num_parents, + mux_hw, &clk_mux_ops, div_hw, + &imx_clk_composite_divider_ops, gate_hw, + &clk_gate_ops, flags); + if (IS_ERR(clk)) { + kfree(mux); + kfree(div); + kfree(gate); + } + + return clk; +} diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 12b3fd6..9dbb680 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -232,4 +232,13 @@ struct clk *imx_clk_cpu(const char *name, const char *parent_name, struct clk *div, struct clk *mux, struct clk *pll, struct clk *step); +struct clk *imx_clk_composite_flags(const char *name, const char **parent_names, + int num_parents, void __iomem *reg, unsigned long flags); + +#define imx_clk_composite(name, parent_names, reg) \ + imx_clk_composite_flags(name, parent_names, ARRAY_SIZE(parent_names), reg, 0) + +#define imx_clk_composite_critical(name, parent_names, reg) \ + imx_clk_composite_flags(name, parent_names, ARRAY_SIZE(parent_names), reg, CLK_IS_CRITICAL) + #endif