From patchwork Wed Dec 6 18:48:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Kaneko X-Patchwork-Id: 845287 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ODOA4Zqs"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3ysSM32jccz9s72 for ; Thu, 7 Dec 2017 05:49:03 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751945AbdLFStB (ORCPT ); Wed, 6 Dec 2017 13:49:01 -0500 Received: from mail-pg0-f68.google.com ([74.125.83.68]:45547 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751815AbdLFStA (ORCPT ); Wed, 6 Dec 2017 13:49:00 -0500 Received: by mail-pg0-f68.google.com with SMTP id m25so2573249pgv.12; Wed, 06 Dec 2017 10:49:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=yW+l8k1hZxVBTHdcg0bxkEiFjRB6badLFCgpiK87wpk=; b=ODOA4Zqs1ARgiVEL4s+offKawHE5laIpRDOmgI8jiVSK7F5+bLHvQew/B/QAQzxFwu B07+npWtaWe8ZMC8iUdreFtWCHqYnjwmy9YUlj938Lgf688atrzM5NMocN2XVxX3UwSL sUIH3XV+O5Pq6hbGMYykWxAkW6YxIA/cTbiJXA8zxAuO0n53T7Er+I3BBrAvc7Q1Q4xa pnLN+zO27nqxblkQ/HgAdzkV1W8t90JPXwToE/YjHAdCkDrPYVH0EzVkhGACpR2mwN2V SW1uekHOCl6jfqM0P2R2+XxTwUhOqQSAzidH4Ndyrq8Sutbn3bHNtuEP2pjSBdDoqo7C 4+lA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=yW+l8k1hZxVBTHdcg0bxkEiFjRB6badLFCgpiK87wpk=; b=NUQMmWav+bGNQjRXTw+TRH0mJpZgryApNEGdWJv/DCSE/sbxh3tR92y3cEsicupE+B mJAABzUzURswSZXnYbqhiqR3+xqfFZEPAPQ/ZTLqKPub9fgA0+iPyr0hzh4y+zeZLEXp dFWerKX/ltcsWW08LtBcH9hGNYEURl3K2aGKWwVZqcehMeb3MTj/zoKbuhLY1TVdiWuw k9HoBwWRH9f+oeaMOMVGzWDLFckcwQf0jGSuvfmT/kAKVvUSyHnXud8UU+q6zZBxxNiv 55WlKkva7idXcPTv5XccBgK16In/6JECkrwrvJbMMnxTORx9kWLm0UJfnq5JAYGgdGgr iU7w== X-Gm-Message-State: AJaThX4/PGyCuc8H5pPpyxUzbHhMCWg2GoVwA0/+0j8qCGoPDxSQ1ZZz vyy3/aZJfG59Duoo70yE2T9qyg== X-Google-Smtp-Source: AGs4zMbiN5XrAcE9EW3NcD4jHc/J4AB241ayhHtA0Q1Q164AZPCQc/ALgg3vm3W7/Np27nWqER/2EA== X-Received: by 10.99.117.12 with SMTP id q12mr22463112pgc.412.1512586139565; Wed, 06 Dec 2017 10:48:59 -0800 (PST) Received: from localhost.localdomain (KD118152108246.ppp-bb.dion.ne.jp. [118.152.108.246]) by smtp.gmail.com with ESMTPSA id a78sm5896528pfl.155.2017.12.06.10.48.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 06 Dec 2017 10:48:59 -0800 (PST) From: Yoshihiro Kaneko To: linux-gpio@vger.kernel.org Cc: Linus Walleij , Simon Horman , Magnus Damm , Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org Subject: [PATCH] gpio: gpio-rcar: Support S2RAM Date: Thu, 7 Dec 2017 03:48:35 +0900 Message-Id: <1512586115-4698-1-git-send-email-ykaneko0929@gmail.com> X-Mailer: git-send-email 1.9.1 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Hien Dang This patch adds an implementation that saves and restores the state of GPIO configuration on suspend and resume. Signed-off-by: Hien Dang Signed-off-by: Takeshi Kihara Signed-off-by: Yoshihiro Kaneko --- This patch is based on the for-next branch of linux-gpio tree. drivers/gpio/gpio-rcar.c | 89 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c index e76de57..c99a2c5 100644 --- a/drivers/gpio/gpio-rcar.c +++ b/drivers/gpio/gpio-rcar.c @@ -31,6 +31,16 @@ #include #include +struct gpio_rcar_bank_info { + bool iointsel; + bool inoutsel; + bool outdt; + bool active_high_rising_edge; + bool level_trigger; + bool both; + bool intmsk; +}; + struct gpio_rcar_priv { void __iomem *base; spinlock_t lock; @@ -41,6 +51,7 @@ struct gpio_rcar_priv { unsigned int irq_parent; bool has_both_edge_trigger; bool needs_clk; + struct gpio_rcar_bank_info bank_info[32]; }; #define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */ @@ -415,6 +426,83 @@ static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins) return 0; } +#ifdef CONFIG_PM_SLEEP +static int gpio_rcar_suspend(struct device *dev) +{ + struct gpio_rcar_priv *p = dev_get_drvdata(dev); + int offset; + u32 bit_mask; + struct gpio_rcar_bank_info *bank_info; + + for (offset = 0; offset < p->gpio_chip.ngpio; offset++) { + bank_info = &p->bank_info[offset]; + bit_mask = BIT(offset); + bank_info->iointsel = !!(gpio_rcar_read(p, IOINTSEL) & + bit_mask); + + /* I/O pin */ + if (!bank_info->iointsel) { + bank_info->inoutsel = !!(gpio_rcar_read(p, INOUTSEL) & + bit_mask); + bank_info->outdt = !!(gpio_rcar_read(p, OUTDT) & + bit_mask); + /* Interrupt pin */ + } else { + bank_info->intmsk = !!(gpio_rcar_read(p, INTMSK) & + bit_mask); + bank_info->active_high_rising_edge = + !(!!(gpio_rcar_read(p, POSNEG) & bit_mask)); + bank_info->level_trigger = + !(!!(gpio_rcar_read(p, EDGLEVEL) & bit_mask)); + bank_info->both = !!(gpio_rcar_read(p, BOTHEDGE) & + bit_mask); + } + } + + return 0; +} + +static int gpio_rcar_resume(struct device *dev) +{ + struct gpio_rcar_priv *p = dev_get_drvdata(dev); + int offset; + struct gpio_rcar_bank_info *bank_info; + + for (offset = 0; offset < p->gpio_chip.ngpio; offset++) { + bank_info = &p->bank_info[offset]; + /* I/O pin */ + if (!bank_info->iointsel) { + if (bank_info->inoutsel) + gpio_rcar_direction_output(&p->gpio_chip, + offset, + bank_info->outdt); + else + gpio_rcar_direction_input(&p->gpio_chip, + offset); + /* Interrupt pin */ + } else { + gpio_rcar_config_interrupt_input_mode( + p, + offset, + bank_info->active_high_rising_edge, + bank_info->level_trigger, + bank_info->both); + + if (bank_info->intmsk) + gpio_rcar_write(p, MSKCLR, BIT(offset)); + } + } + + return 0; +} + +static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, + gpio_rcar_suspend, gpio_rcar_resume); +#define DEV_PM_OPS (&gpio_rcar_pm_ops) +#else +#define DEV_PM_OPS NULL +#endif /* CONFIG_PM_SLEEP*/ + static int gpio_rcar_probe(struct platform_device *pdev) { struct gpio_rcar_priv *p; @@ -536,6 +624,7 @@ static int gpio_rcar_remove(struct platform_device *pdev) .remove = gpio_rcar_remove, .driver = { .name = "gpio_rcar", + .pm = DEV_PM_OPS, .of_match_table = of_match_ptr(gpio_rcar_of_table), } };