From patchwork Sat Sep 30 12:13:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 820206 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3y46lk0cdKz9t3f for ; Sat, 30 Sep 2017 22:13:38 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752863AbdI3MNW (ORCPT ); Sat, 30 Sep 2017 08:13:22 -0400 Received: from lucky1.263xmail.com ([211.157.147.130]:46922 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752157AbdI3MNI (ORCPT ); Sat, 30 Sep 2017 08:13:08 -0400 Received: from david.wu?rock-chips.com (unknown [192.168.167.138]) by lucky1.263xmail.com (Postfix) with ESMTP id 6355A1F00D5; Sat, 30 Sep 2017 20:12:57 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id 8EC8137E; Sat, 30 Sep 2017 20:12:58 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: <232707d8885bf019887c8f63b1964d1e> X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from unknown (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith SMTP id 26965GLGH7D; Sat, 30 Sep 2017 20:12:59 +0800 (CST) From: David Wu To: heiko@sntech.de, linus.walleij@linaro.org Cc: huangtao@rock-chips.com, andy.yan@rock-chips.com, linux-rockchip@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, David Wu Subject: [PATCH 2/2] pinctrl: rockchip: Fix the correct routing config for the gmac-m1 pins of rmii and rgmii Date: Sat, 30 Sep 2017 20:13:21 +0800 Message-Id: <1506773601-27315-3-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506773601-27315-1-git-send-email-david.wu@rock-chips.com> References: <1506773601-27315-1-git-send-email-david.wu@rock-chips.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org If the gmac-m1 optimization(bit10) is selected, the gpio function of gmac pins is not valid. We may use the rmii mode for gmac interface, the pins such as rx_d2, rx_d3, which the rgmii mode used, but rmii not used could be taken as gpio function. So gmac_rxd0m1 selects the bit2, and gmac_rxd0m3 select bit10 is more correct. Signed-off-by: David Wu Reviewed-by: Heiko Stuebner --- drivers/pinctrl/pinctrl-rockchip.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index c7c9beb..9e0cabf 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -900,12 +900,19 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, .route_offset = 0x50, .route_val = BIT(16) | BIT(16 + 1) | BIT(0), }, { - /* gmac-m1-optimized_rxd0 */ + /* gmac-m1_rxd0 */ .bank_num = 1, .pin = 11, .func = 2, .route_offset = 0x50, - .route_val = BIT(16 + 2) | BIT(16 + 10) | BIT(2) | BIT(10), + .route_val = BIT(16 + 2) | BIT(2), + }, { + /* gmac-m1-optimized_rxd3 */ + .bank_num = 1, + .pin = 14, + .func = 2, + .route_offset = 0x50, + .route_val = BIT(16 + 10) | BIT(10), }, { /* pdm_sdi0m0 */ .bank_num = 2,