From patchwork Wed Jul 12 16:55:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Kaneko X-Patchwork-Id: 787375 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3x74q46M9Pz9s3T for ; Thu, 13 Jul 2017 02:56:32 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="MKYgYQHH"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932154AbdGLQ4a (ORCPT ); Wed, 12 Jul 2017 12:56:30 -0400 Received: from mail-pg0-f66.google.com ([74.125.83.66]:36463 "EHLO mail-pg0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932083AbdGLQ41 (ORCPT ); Wed, 12 Jul 2017 12:56:27 -0400 Received: by mail-pg0-f66.google.com with SMTP id y129so3679104pgy.3; Wed, 12 Jul 2017 09:56:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=c2MsyADFQf4q2Xr5qB58qaHoLo8ohNh2O1qLlvAx47U=; b=MKYgYQHHOuqZlD+N6N1tcvO0pXxKngD3IL/nYO6wCjHwZesDrsBbsJP1dVnzhd3SOe fo1W3Hnb3tFmPcrOb3g+HooVaZZJRN8jmxBG7JgpEvGQaw75OIJDqNl+D+rV0DzRo5A2 E38i4+ge82X3cAshS84WRBN4oQjmzM7CB93qZqc+UoJC65LfSjx6beLSQCv5XU34yAmj wtGmffC9vQTS3dPVrt3tiRSRQjr/uG/IRspIBL2g/x8OycRGhrPgj9P3mN560UDRPevD 2pYC4s5SPS9yLm6wPyFv1GQiulC0t8Y/KOKxbeKCoDLA+ROTnWyQxgNy7IFRl9rFv71T 1xHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=c2MsyADFQf4q2Xr5qB58qaHoLo8ohNh2O1qLlvAx47U=; b=MQ+2UCc//eoVZjt1SqxuID18T6QXydPqRhrvm6a8qvCe48tBK323o59tMj1voY5kcu 2O4csbp+xyaSzR8vkdhGW+Hk1bO39/lMqRWFwvpiHhfHn6m5Bh07gRDHoWhCmzBzBJ+r g+LGo1W+1eX8g7LQcg3BxNed4rDEYTCrPchcUIF7IHSGbe9sT93ULmbx9/+k9PATwcUE wmnYr8anGIux3pHX8i3WvMPV5jF89yTLYfg3nf8FA30MUZqNMs3JA2oow8YhRLLcFmSc sFNd8/+BDOjYxQzjpEpqr7emTALqgrhrO7zaQom56gV+rjcF9JzuYzUVMiw5HOUO/AC2 A2jA== X-Gm-Message-State: AIVw112+wEATG5C6b52HtErEdIpjjDNZ8E6DaQLUMFYqap6g7I/RXRHx SfzjT2J9Xay14JFf X-Received: by 10.84.215.219 with SMTP id g27mr5287346plj.203.1499878586502; Wed, 12 Jul 2017 09:56:26 -0700 (PDT) Received: from localhost.localdomain (KD118152108246.ppp-bb.dion.ne.jp. [118.152.108.246]) by smtp.gmail.com with ESMTPSA id p68sm6919132pfj.26.2017.07.12.09.56.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 12 Jul 2017 09:56:26 -0700 (PDT) From: Yoshihiro Kaneko To: linux-gpio@vger.kernel.org Cc: Linus Walleij , Laurent Pinchart , Geert Uytterhoeven , Simon Horman , Magnus Damm , linux-renesas-soc@vger.kernel.org Subject: [PATCH 08/14] pinctrl: sh-pfc: r8a7796: Fix MSIOF3_{SS1, SS2}_E pins function definitions Date: Thu, 13 Jul 2017 01:55:41 +0900 Message-Id: <1499878547-3452-9-git-send-email-ykaneko0929@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1499878547-3452-1-git-send-email-ykaneko0929@gmail.com> References: <1499878547-3452-1-git-send-email-ykaneko0929@gmail.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Takeshi Kihara This patch fixes the implementation incorrect of IPSR register value definitions for MSIOF3_{SS1,SS2}_E pins function. This is a correction to the incorrect implementation of IPSR register pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware User's Manual Rev.0.51E or later. Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support") Signed-off-by: Takeshi Kihara Signed-off-by: Yoshihiro Kaneko --- drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c index 80007b9..866cbe4 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c @@ -221,8 +221,8 @@ #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)