From patchwork Wed Jul 12 16:55:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Kaneko X-Patchwork-Id: 787368 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3x74pl1zsRz9s3T for ; Thu, 13 Jul 2017 02:56:15 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="UWmj+7OA"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753953AbdGLQ4M (ORCPT ); Wed, 12 Jul 2017 12:56:12 -0400 Received: from mail-pg0-f68.google.com ([74.125.83.68]:36377 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753659AbdGLQ4L (ORCPT ); Wed, 12 Jul 2017 12:56:11 -0400 Received: by mail-pg0-f68.google.com with SMTP id y129so3678401pgy.3; Wed, 12 Jul 2017 09:56:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xqzZGTp2cM9I/GMFwFe87+nbwMuWD7XQkJiEXxIeZ40=; b=UWmj+7OA5h4oUSguOu9PFDByNNO/0ojauyYz1M7CvsYDUDa2iBeS2b979ofkd1DmZW MMP5MwlJd9quTgWprO6qmoPzUzMDWdOjPgMjCrJixQ5ehSrBnrUKzKqNh6GQLd3pWxma hYBCETNidKIRAGjcRbq2xhVZGpA3D3yBHBBRZxh30wMjZU+3MuSoh6c+94+RNnTvwoYz eWjtEBTvqSHz7iSaeFKyo4BCNMS3BLZ2UMFfRIzmz9Qw+i2yFGaxRhFh6vMknuMi+fzn t0j6Cl8DSWynX7uMKUYxwx5bBN+jngZdeSE46fmAZlLABzRPW22PUT4APGz9cAVNeTuF GsmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xqzZGTp2cM9I/GMFwFe87+nbwMuWD7XQkJiEXxIeZ40=; b=cACOa2J4mrcqcLtB3OVpwjNDH3LLQpsICl6NaDrJvoGUByeIqah55GZ97jKeTpniTT c/cDv/2FVn9aCJjF6hbMvN94ShSJNUzbS6ebL11eArfKnMOI4wXvRnaveu3g6dbgHd0T chVjzCV2xR3lPn3I20K5JHtycblO5Z4RvrpFeSE0XIdBiw6ZIQEtd6+/V8zuxdcEEX+J bzcuZds8JEZZPfuZjmWzSBPx+CFEuG1ECmjlkwE6dS/YqKrScIDuBXlX8ZsqfPTPI2hN ju2aKAqa+h6PQiNNmDqGvozOL7FfyZ4xzl+GDEqzIXVTgBfWPLa60l/6Z/oQvwlLslps Lzyw== X-Gm-Message-State: AIVw113Uu6+QI4IGNz/ankXAsaHr1i04ZIEXWRB/umlWDhBM5bFNVPoX 3Hc+zBu3O7NWcoi8 X-Received: by 10.98.73.65 with SMTP id w62mr56518333pfa.61.1499878570035; Wed, 12 Jul 2017 09:56:10 -0700 (PDT) Received: from localhost.localdomain (KD118152108246.ppp-bb.dion.ne.jp. [118.152.108.246]) by smtp.gmail.com with ESMTPSA id p68sm6919132pfj.26.2017.07.12.09.56.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 12 Jul 2017 09:56:09 -0700 (PDT) From: Yoshihiro Kaneko To: linux-gpio@vger.kernel.org Cc: Linus Walleij , Laurent Pinchart , Geert Uytterhoeven , Simon Horman , Magnus Damm , linux-renesas-soc@vger.kernel.org Subject: [PATCH 01/14] pinctrl: sh-pfc: r8a7796: Fix MOD_SEL1 bit[25:24] to 0x3 when using STP_ISEN_1_D Date: Thu, 13 Jul 2017 01:55:34 +0900 Message-Id: <1499878547-3452-2-git-send-email-ykaneko0929@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1499878547-3452-1-git-send-email-ykaneko0929@gmail.com> References: <1499878547-3452-1-git-send-email-ykaneko0929@gmail.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Takeshi Kihara This patch fixes the implementation incorrect of MOD_SEL1 bit[25:24] value when STP_ISEN_1_D pin function is selected for IPSR17 bit[27:24]. This is a correction to the incorrect implementation of MOD_SEL register pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware User's Manual Rev.0.51E or later. Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support") Signed-off-by: Takeshi Kihara Signed-off-by: Yoshihiro Kaneko Reviewed-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c index 98bf5d0..b2fb66f 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c @@ -1461,7 +1461,7 @@ enum { PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B), PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1), PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3), - PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_2), + PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3), PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4), PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1), PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU_1),