From patchwork Tue Feb 28 17:04:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charles Keepax X-Patchwork-Id: 733677 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vXlnK6L6Cz9s8D for ; Wed, 1 Mar 2017 04:24:37 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751553AbdB1RYL (ORCPT ); Tue, 28 Feb 2017 12:24:11 -0500 Received: from mx0b-001ae601.pphosted.com ([67.231.152.168]:55095 "EHLO mx0b-001ae601.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751457AbdB1RYJ (ORCPT ); Tue, 28 Feb 2017 12:24:09 -0500 Received: from pps.filterd (m0077474.ppops.net [127.0.0.1]) by mx0b-001ae601.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v1SGwnwP019114; Tue, 28 Feb 2017 11:03:32 -0600 Authentication-Results: ppops.net; spf=none smtp.mailfrom=ckeepax@opensource.wolfsonmicro.com Received: from mail3.cirrus.com ([87.246.76.56]) by mx0b-001ae601.pphosted.com with ESMTP id 28u77qn80k-1; Tue, 28 Feb 2017 11:03:31 -0600 Received: from EX17.ad.cirrus.com (ex17.ad.cirrus.com [172.20.9.81]) by mail3.cirrus.com (Postfix) with ESMTP id D17C3611CE83; Tue, 28 Feb 2017 11:04:48 -0600 (CST) Received: from imbe.wolfsonmicro.main (198.61.95.81) by EX17.ad.cirrus.com (172.20.9.81) with Microsoft SMTP Server id 14.3.301.0; Tue, 28 Feb 2017 17:03:30 +0000 Received: from algalon.ad.cirrus.com (algalon.ad.cirrus.com [198.90.223.36]) by imbe.wolfsonmicro.main (8.14.4/8.14.4) with ESMTP id v1SH37R2022301; Tue, 28 Feb 2017 17:03:07 GMT From: Charles Keepax To: , CC: , , , , , Subject: [PATCH v2] pinctrl: samsung: Calculate GPIO base for pinctrl_add_gpio_range Date: Tue, 28 Feb 2017 17:04:35 +0000 Message-ID: <1488301475-10804-1-git-send-email-ckeepax@opensource.wolfsonmicro.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <20170228090143.GG2742@localhost.localdomain> References: <20170228090143.GG2742@localhost.localdomain> MIME-Version: 1.0 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1612050000 definitions=main-1702280151 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org As the pinctrl is now added before the GPIOs are registered we need to manually calculate what the GPIO base will be, otherwise the base for each gpio_range will be set to zero. Fortunately the driver already assigns a GPIO base, in samsung_gpiolib_register, and uses the same calculation it does for the pin_base. Meaning the two will always be the same and allowing us to reuse the pinbase and avoid the issue. Signed-off-by: Charles Keepax Acked-by: Tomasz Figa --- Changes since v1: - Use grange.base in samsung_gpiolib_register to make it more clear the two are related in the driver. Thanks, Charles drivers/pinctrl/samsung/pinctrl-samsung.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index ddc8d6b..27d5157 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -882,7 +882,7 @@ static int samsung_pinctrl_register(struct platform_device *pdev, pin_bank->grange.id = bank; pin_bank->grange.pin_base = drvdata->pin_base + pin_bank->pin_base; - pin_bank->grange.base = pin_bank->gpio_chip.base; + pin_bank->grange.base = pin_bank->grange.pin_base; pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; pin_bank->grange.gc = &pin_bank->gpio_chip; pinctrl_add_gpio_range(drvdata->pctl_dev, &pin_bank->grange); @@ -928,7 +928,7 @@ static int samsung_gpiolib_register(struct platform_device *pdev, bank->gpio_chip = samsung_gpiolib_chip; gc = &bank->gpio_chip; - gc->base = drvdata->pin_base + bank->pin_base; + gc->base = bank->grange.base; gc->ngpio = bank->nr_pins; gc->parent = &pdev->dev; gc->of_node = bank->of_node;