From patchwork Tue Nov 22 10:20:12 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 697630 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3tNMP60hdmz9t17 for ; Tue, 22 Nov 2016 21:37:46 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932539AbcKVKhT (ORCPT ); Tue, 22 Nov 2016 05:37:19 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:3615 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932508AbcKVKhQ (ORCPT ); Tue, 22 Nov 2016 05:37:16 -0500 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Tue, 22 Nov 2016 02:36:27 -0800 Received: from HQMAIL108.nvidia.com ([172.20.13.39]) by hqnvupgp07.nvidia.com (PGP Universal service); Mon, 21 Nov 2016 14:35:55 -0800 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Mon, 21 Nov 2016 14:35:55 -0800 Received: from BGMAIL102.nvidia.com (10.25.59.11) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 22 Nov 2016 10:37:14 +0000 Received: from HQMAIL104.nvidia.com (172.18.146.11) by bgmail102.nvidia.com (10.25.59.11) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 22 Nov 2016 10:37:10 +0000 Received: from ldewanganubuntu-System-Product-Name.nvidia.com (172.20.13.39) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1210.3 via Frontend Transport; Tue, 22 Nov 2016 10:37:03 +0000 From: Laxman Dewangan To: , , , CC: , , , , , , , , Laxman Dewangan Subject: [PATCH V3 1/2] pinctrl: tegra: Add DT binding for io pads control Date: Tue, 22 Nov 2016 15:50:12 +0530 Message-ID: <1479810013-29894-2-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1479810013-29894-1-git-send-email-ldewangan@nvidia.com> References: <1479810013-29894-1-git-send-email-ldewangan@nvidia.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org NVIDIA Tegra124 and later SoCs support the multi-voltage level and low power state of some of its IO pads. The IO pads can work in the voltage of the 1.8V and 3.3V of IO voltage from IO power rail sources. When IO interfaces are not used then IO pads can be configure in low power state to reduce the power consumption from that IO pads. On Tegra124, the voltage level of IO power rail source is auto detected by hardware(SoC) and hence it is only require to configure in low power mode if IO pads are not used. On T210 onwards, the auto-detection of voltage level from IO power rail is removed from SoC and hence SW need to configure the PMC register explicitly to set proper voltage in IO pads based on IO rail power source voltage. Add DT binding document for detailing the DT properties for configuring IO pads voltage levels and its power state. Signed-off-by: Laxman Dewangan --- Changes from V1: New in series based on pinctrl driver requirement. Changes from V2: Updated the statement to say 1.8V and 3.3V as nominal voltage. Corrected DT example by adding -supply and taken care of V2 review from Rob. --- .../bindings/pinctrl/nvidia,tegra-io-pad.txt | 126 +++++++++++++++++++++ 1 file changed, 126 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra-io-pad.txt diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra-io-pad.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra-io-pad.txt new file mode 100644 index 0000000..a88c484 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra-io-pad.txt @@ -0,0 +1,126 @@ +NVIDIA Tegra PMC IO pad controller + +NVIDIA Tegra124 and later SoCs support the multi-voltage level and low power +state of some of its IO pads. When IO interface are not used then IO pads can +be configure in low power state to reduce the power from that IO pads. The IO +pads can work in the nominal IO voltage of 1.8V and 3.3V from power rail +sources. + +On Tegra124, the voltage of IO power rail source is auto detected by SoC and +hence it is only require to configure in low power mode if IO pads are not +used. + +On T210 onwards, the HW based auto-detection for IO voltage is removed and +hence SW need to configure the PMC register explicitly, to set proper voltage +in IO pads, based on IO rail power source voltage. + +The voltage configurations and low power state of IO pads should be done in +boot if it is not going to change otherwise dynamically based on IO rail +voltage on that IO pads and usage of IO pads + +The DT property of the IO pads must be under the node of pmc i.e. +pmc@7000e400 for Tegra124 onwards. + +Please refer to in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +Tegra's pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for an +IO pads, or a list of IO pads. This configuration can include the voltage and +power enable/disable control + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. Each subnode only affects those +parameters that are explicitly listed. Unspecified is represented as an absent +property, + +See the TRM to determine which properties and values apply to each IO pads. + +Required subnode-properties: +========================== +- pins : An array of strings. Each string contains the name of an IO pads. Valid + values for these names are listed below. + +Optional subnode-properties: +========================== +Following properties are supported from generic pin configuration explained +in . +low-power-enable: enable low power mode. +low-power-disable: disable low power mode. + +Valid values for pin for T124 are: + audio, bb, cam, comp, csia, csib, csie, dsi, dsib, dsic, dsid, hdmi, + hsic, hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, + pex-ctrl, sdmmc1, sdmmc3, sdmmc4, sys-ddc, uart, usb0, usb1, usb2, + usb-bias + +Valid values for pin for T210 are: + audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, + dbg, debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, + gpio, hdmi, hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, + pex-ctrl, sdmmc1, sdmmc3, spi, spi-hv, uart, usb-bias, usb0, + usb1, usb2, usb3. + +To find out the IO rail voltage for setting the voltage of IO pad by SW, +the regulator supply handle must provided from the DT and it is explained +in the regulator DT binding document + . +For example, for GPIO rail the supply name is vddio-gpio and regulator +handle is supplied from DT as + vddio-gpio-supply = <®ulator_xyz>; + +For T210, following IO pads support the 1.8V/3.3V and the corresponding +IO voltage pin names are as follows: + audio -> vddio-audio + audio-hv -> vddio-audio-hv + cam ->vddio-cam + dbg -> vddio-dbg + dmic -> vddio-dmic + gpio -> vddio-gpio + pex-ctrl -> vddio-pex-ctrl + sdmmc1 -> vddio-sdmmc1 + sdmmc3 -> vddio-sdmmc3 + spi -> vddio-spi + spi-hv -> vddio-spi-hv + uart -> vddio-uart + +Example: + i2c@7000d000 { + pmic@3c { + regulators { + vddio_sdmmc1: ldo2 { + /* Regulator entries for LDO2 */ + }; + + vdd_cam: ldo3 { + /* Regulator entries for LDO3 */ + }; + }; + }; + }; + + pmc@7000e400 { + vddio-cam-supply = <&vdd_cam>; + vddio-sdmmc1-supply = <&vddio_sdmmc1>; + + pinctrl-names = "default"; + pinctrl-0 = <&tegra_io_pad_volt_default>; + tegra_io_pad_volt_default: common { + audio-hv { + pins = "audio-hv"; + low-power-disable; + }; + + gpio { + pins = "gpio"; + low-power-disable; + }; + + audio { + pins = "audio", "dmic", "sdmmc3"; + low-power-enable; + }; + }; + + };