From patchwork Wed Oct 19 15:21:13 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 684192 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3szbMG2MXYz9tkc for ; Thu, 20 Oct 2016 02:24:10 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b=SsDT30ax; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S944860AbcJSPVw (ORCPT ); Wed, 19 Oct 2016 11:21:52 -0400 Received: from mail-qt0-f172.google.com ([209.85.216.172]:33163 "EHLO mail-qt0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S944841AbcJSPVr (ORCPT ); Wed, 19 Oct 2016 11:21:47 -0400 Received: by mail-qt0-f172.google.com with SMTP id s49so23889264qta.0 for ; Wed, 19 Oct 2016 08:21:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0E8WnISw9vf1yQEJ1JxBE5VMlZi2lq2Rc0/aayslZ+s=; b=SsDT30axtoXg/yLMV4KVRpGB8HqpxDXG3dy3iNqYokWf4GfB9ieJmAqhGeOPavHjRp ieAJtz1hTvglSPJo2YtY3I3RAX6zyuKxQAacNbYHy+CIIZImmJgmMM8ZaUok3Befl2/e hMJ1bG/8OIGhvMHxkL7uKgsZsah8hgfB3GSrwSQCEvIVJQhSI/1mePTBSUNH4iWsq1NK y0Do5KxctGq5p35scweZ8ku0m/Tb+WCrUvjbh6/EfmBVNjo84MEFMKDi9Gv3gHhQicGW dB1o461RuloXGExptI4UhvJkiXgxPRwqSqCZ3iQe6sEhSOLtZ2SAd38Di4XSbN9/8hW6 2qzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0E8WnISw9vf1yQEJ1JxBE5VMlZi2lq2Rc0/aayslZ+s=; b=aVwvBor942Dz/9OJU3CIdK+95gwy7AygYXoW8fyGadcooK9ej70nBYf1h8PZ5PxToB 5Xr19Zssbjr6ZoaHoTE1B6pLNiMx97C5uf0tAgb+EriBZXO8wCk1DBgem1vr/3QO0krk vvvAL6MzGrLF49tr9nVwM/ZvNrGFnf6H3/ZAghtgrRg0MVSuMPZK5uzHuxmvvlRaKJnu z4HBbFuozxGziz7G+qHqZGCF9Yjcf3Dw8yh7DnsWad8Uq93UKoe3FvlSEg2C2sal8bH2 d0TfuCCpgHVDWqY1gEtzjh2swF3LloHO5zZa/mVAAQ+pXW/N0V4vulISab+cILgSpzJW pFMQ== X-Gm-Message-State: AA6/9Rnl6Rke4BNw9PIuVUae3zStwpcXQFKHUTGrGmZc2G/dW0zOT/fZTBC/jQJDpfJwmS49 X-Received: by 10.28.22.17 with SMTP id 17mr5304620wmw.128.1476890497227; Wed, 19 Oct 2016 08:21:37 -0700 (PDT) Received: from boomer.baylibre.com ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id f2sm69725653wjr.2.2016.10.19.08.21.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Oct 2016 08:21:36 -0700 (PDT) From: Jerome Brunet To: Carlo Caione , Kevin Hilman , Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring Cc: Jerome Brunet , linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Linus Walleij , Catalin Marinas , Will Deacon , Russell King Subject: [PATCH v2 2/9] dt-bindings: interrupt-controller: add DT binding for meson GPIO interrupt controller Date: Wed, 19 Oct 2016 17:21:13 +0200 Message-Id: <1476890480-8884-3-git-send-email-jbrunet@baylibre.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1476890480-8884-1-git-send-email-jbrunet@baylibre.com> References: <1476890480-8884-1-git-send-email-jbrunet@baylibre.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This commit adds the device tree bindings description for Amlogic's GPIO interrupt controller available on the meson8, meson8b and gxbb SoC families Signed-off-by: Jerome Brunet --- Rob, I did not include the Ack you gave for the RFC as bindings have slightly changed. Only the interrupt property has be removed following a discussion I had with Marc .../amlogic,meson-gpio-intc.txt | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt new file mode 100644 index 000000000000..2464d9a0865d --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt @@ -0,0 +1,31 @@ +Amlogic meson GPIO interrupt controller + +Meson SoCs contains an interrupt controller which is able watch the SoC pads +and generate an interrupt on edges or level. The controller is essentially a +256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge +or level and polarity. We don’t expose all 256 mux inputs because the +documentation shows that upper part is not mapped to any pad. The actual number +of interrupt exposed depends on the SoC. + +Required properties: + +- compatible : should be either + "amlogic,meson8-gpio-intc” for meson8 SoCs (AML7826MX) or + “amlogic,meson8b-gpio-intc” for meson8b SoCs (S805) or + “amlogic,meson-gxbb-gpio-intc” for GXBB SoCs (S905) +- interrupt-parent : a phandle to the GIC the interrupts are routed to. + Usually this is provided at the root level of the device tree as it is + common to most of the SoC +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller. +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value must be 2. + +Example: + +gpio_interrupt: interrupt-controller@9880 { + compatible = "amlogic,meson-gxbb-gpio-intc"; + reg = <0x0 0x9880 0x0 0x10>; + interrupt-controller; + #interrupt-cells = <2>; +};