From patchwork Wed Oct 19 10:08:24 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 684208 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3szblB4GSXz9t0p for ; Thu, 20 Oct 2016 02:41:26 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b=OKoKwM9G; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S943947AbcJSPlL (ORCPT ); Wed, 19 Oct 2016 11:41:11 -0400 Received: from mail-lf0-f44.google.com ([209.85.215.44]:33778 "EHLO mail-lf0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S945369AbcJSPlI (ORCPT ); Wed, 19 Oct 2016 11:41:08 -0400 Received: by mail-lf0-f44.google.com with SMTP id x79so32016572lff.0 for ; Wed, 19 Oct 2016 08:41:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CBIKugDPvE6YZkZlIZ4fS4SNIQVRR1eJoF92Ln/1e7A=; b=OKoKwM9GwsUDXGg5JcDmir4/oZeB2gx9ddXt8+acHKRzh6xDC/bbexUxwf/WWMUk+J 8LpHrmg5BdEAabRe+2J2Hj9WO37gvwaEgyr61I8VXbFaNFuA+Pt3RqwIhAE3omc8fYpz muTcOtKHWDFbaxkjnpq4hdl/mPEO2vGRNEodBChj3ZuClE7KOOycMgZSqmnLhn3P4wsz tWFsIc+ESHIjvDmtxTdqAq1mMRK/F2bG2MhJX0hdtR0WvvsKOr6NnuDKUp+rBxQ3GR3y /xoRj6Y7U+p0TGq5DSP1hErQOYaENQAnQqpbWHGp+8Mrar2dkgOzsRNHKMIXxv3qWcqe 1cog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CBIKugDPvE6YZkZlIZ4fS4SNIQVRR1eJoF92Ln/1e7A=; b=Vpw5ruA+mPEXhso2VSHHYhQ58wUDydqoHamBAm4A5T/mvJjzuzqTAaSdxB4Ub5IQ7/ CL72RegBJpYWNe3dlrW8I0glvhsNaI31ZubZ3UpykvEByx1F9JGYlY7oSYwYo3SZIeaK EeeGcQw9LkiwUpuvIQ2G6QQ1YizC5Wzjr8d+/hhcxcHyk4nLvrD4O5Wc+CgvoaY4KH12 GAdzkAKKDKIdYPzTnK1EgWCKub9GI9daPRPgJvOd6Gl7C/ty2H0RQNgyKC4HCudVv9Hg bVd9HB6g2Kh5sgnFXGdrRn6TgEO4HpmhFTFqCifBApWYZsz3P0eMi9/XP373Pvi45M20 rpug== X-Gm-Message-State: AA6/9RnikmtidbbZuz+XrvecsTPTUe46wVvLBQ7oSP8M9S/x+3WRVil3GhfimCoKgOU/7/yw X-Received: by 10.28.18.5 with SMTP id 5mr4364798wms.35.1476871743690; Wed, 19 Oct 2016 03:09:03 -0700 (PDT) Received: from boomer.baylibre.com ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id l15sm4199066wmd.7.2016.10.19.03.09.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Oct 2016 03:09:03 -0700 (PDT) From: Jerome Brunet To: Carlo Caione , Kevin Hilman , Linus Walleij Cc: Jerome Brunet , linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Catalin Marinas , Will Deacon , Russell King Subject: [PATCH 4/9] pinctrl: meson: allow gpio to request irq Date: Wed, 19 Oct 2016 12:08:24 +0200 Message-Id: <1476871709-8359-5-git-send-email-jbrunet@baylibre.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1476871709-8359-1-git-send-email-jbrunet@baylibre.com> References: <1476871709-8359-1-git-send-email-jbrunet@baylibre.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add the ability for gpio to request irq from the gpio interrupt controller if present. We have to specificaly that the parent interrupt controller is the gpio interrupt controller because gpio on meson SoCs can't generate interrupt directly on the GIC. Signed-off-by: Jerome Brunet --- drivers/pinctrl/Kconfig | 2 + drivers/pinctrl/meson/pinctrl-meson.c | 77 ++++++++++++++++++++++++++++++++++- drivers/pinctrl/meson/pinctrl-meson.h | 1 + 3 files changed, 79 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 0e75d94972ba..d5bfbfcddab0 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -126,7 +126,9 @@ config PINCTRL_MESON select PINCONF select GENERIC_PINCONF select GPIOLIB + select IRQ_DOMAIN select OF_GPIO + select OF_IRQ select REGMAP_MMIO config PINCTRL_OXNAS diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c index 57122eda155a..fd3c1d44978b 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.c +++ b/drivers/pinctrl/meson/pinctrl-meson.c @@ -50,6 +50,7 @@ #include #include #include +#include #include #include #include @@ -481,6 +482,58 @@ static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value) value ? BIT(bit) : 0); } +static int meson_gpio_to_hwirq(struct meson_bank *bank, unsigned int offset) +{ + unsigned int hwirq; + + if (bank->irq_first < 0) + /* this bank cannot generate irqs */ + return -1; + + hwirq = offset - bank->first + bank->irq_first; + + if (hwirq > bank->irq_last) + /* this pin cannot generate irqs */ + return -1; + + return hwirq; +} + +static int meson_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) +{ + struct meson_pinctrl *pc = gpiochip_get_data(chip); + struct meson_bank *bank; + struct irq_fwspec fwspec; + unsigned int hwirq; + int ret; + + ret = meson_get_bank(pc, offset, &bank); + if (ret) + return ret; + + /* + * The interrupt controller might be missing, in such case we can't + * provide an interrupt for a pin + */ + if (is_fwnode_irqchip(pc->fwnode)) { + dev_info(pc->dev, "interrupt controller not found\n"); + return 0; + } + + hwirq = meson_gpio_to_hwirq(bank, offset); + if (hwirq < 0) { + dev_dbg(pc->dev, "no interrupt for pin %u\n", offset); + return 0; + } + + fwspec.fwnode = pc->fwnode; + fwspec.param_count = 2; + fwspec.param[0] = hwirq; + fwspec.param[1] = IRQ_TYPE_NONE; + + return irq_create_fwspec_mapping(&fwspec); +} + static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio) { struct meson_pinctrl *pc = gpiochip_get_data(chip); @@ -539,6 +592,7 @@ static int meson_gpiolib_register(struct meson_pinctrl *pc) pc->chip.direction_output = meson_gpio_direction_output; pc->chip.get = meson_gpio_get; pc->chip.set = meson_gpio_set; + pc->chip.to_irq = meson_gpio_to_irq; pc->chip.base = pc->data->pin_base; pc->chip.ngpio = pc->data->num_pins; pc->chip.can_sleep = false; @@ -598,6 +652,27 @@ static struct regmap *meson_map_resource(struct meson_pinctrl *pc, return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config); } +static int meson_pinctrl_get_irq_gpio_intc(struct meson_pinctrl *pc, + struct device_node *node) +{ + struct device_node *np; + + np = of_irq_find_parent(node); + if (unlikely(!np)) { + dev_err(pc->dev, "interrupt parent not found\n"); + return -EINVAL; + } + + if (!of_device_is_compatible(np, pc->data->irq_compat)) { + dev_info(pc->dev, "gpio interrupt disabled\n"); + pc->fwnode = NULL; + } + + pc->fwnode = of_node_to_fwnode(np); + + return 0; +} + static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc, struct device_node *node) { @@ -643,7 +718,7 @@ static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc, return PTR_ERR(pc->reg_gpio); } - return 0; + return meson_pinctrl_get_irq_gpio_intc(pc, gpio_np); } static int meson_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h index b90d69e366df..2e6c83adbd1f 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.h +++ b/drivers/pinctrl/meson/pinctrl-meson.h @@ -123,6 +123,7 @@ struct meson_pinctrl { struct regmap *reg_gpio; struct gpio_chip chip; struct device_node *of_node; + struct fwnode_handle *fwnode; }; #define PIN(x, b) (b + x)