From patchwork Tue Sep 13 15:12:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 669413 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3sYSqB3Y35z9sC4 for ; Wed, 14 Sep 2016 01:13:10 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b=gpazB5L1; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756798AbcIMPNI (ORCPT ); Tue, 13 Sep 2016 11:13:08 -0400 Received: from mail-lf0-f44.google.com ([209.85.215.44]:35341 "EHLO mail-lf0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753562AbcIMPNI (ORCPT ); Tue, 13 Sep 2016 11:13:08 -0400 Received: by mail-lf0-f44.google.com with SMTP id l131so112669529lfl.2 for ; Tue, 13 Sep 2016 08:13:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to; bh=PlV5dKQ/n0l45uF01oCoe9fR+JFqw8N7I1BZiUgGYts=; b=gpazB5L1RJxmH9dn6qKdFNfK/rvTkUHEfKnP6EL7LPaFV2BDzQbt4zP5Ai+ZURK0qu y7eOqtC+fRLCx6p/1LLZrt7BYKX1bO1At6G3pSZwwcw58CFHVo64ja9hctsv+VLStXlJ cZEukqnnU+AoDzQxfB+lkWN8fxyyea14Bf0NwUuIZtmka3BuEIOK2Tf30ImE5Ic5SXb7 tsrx35bbAYC4OU01Qce3kJJJncX3ocWOgB46QCu/f9IovefsNW/o/N+J1JR+sagoFT5p ENn1E/QrB7D4hZ9mm0IrIrV7vV1rx4vkAGgzirs7TjT7qNfaHf5dUvfMbY5jpcF3kr/c 20pA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to; bh=PlV5dKQ/n0l45uF01oCoe9fR+JFqw8N7I1BZiUgGYts=; b=L76ROhtqFwsOl7LsU2W9eWZIahGmEjzKRSQDSpczaZQuemqRENG4X+ooQ2iWJl260h kyZYeMIOIZ754OVyhWRQZ6W2MWNTVVkuoT4EfY0LENRt0psO4oM+JCYYJXWA3c0IcS2/ E4Av7Ev33gdMuR1gqiWmBQZbERLNFiN9qQ5Y49DGeWfo8yb4xxOyV4S1IkhbYjVte7dc Ni6Rrl9xEQEjrUx2d+FKGpudIKaDzoHcSUiT3DiRsaJ6o527D0hXL2ivk4ZOzUmKWIsh DJyDnGotpjKNr2S0kPmSUo2xspea1ufjgSyqeJcb/5tkXHU60DKKt6P6W8uKSkMhSi3+ Sfyg== X-Gm-Message-State: AE9vXwOQpMrGw6pdr+zfoupUf7LyOLgB9e6BYxdfEld7j/g8Dycc0LVTMoUZzruqU/02hHjV X-Received: by 10.194.103.3 with SMTP id fs3mr20948836wjb.115.1473779586181; Tue, 13 Sep 2016 08:13:06 -0700 (PDT) Received: from mogwai.baylibre.com ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id b128sm5813245wmb.21.2016.09.13.08.13.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 13 Sep 2016 08:13:05 -0700 (PDT) From: Jerome Brunet To: Linus Walleij , Kevin Hilman , Carlo Caione Cc: Jerome Brunet , linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org Subject: [RESEND PATCH v2 2/4] pinctrl: amlogic: gxbb: add nand pins Date: Tue, 13 Sep 2016 17:12:22 +0200 Message-Id: <1473779542-2635-2-git-send-email-jbrunet@baylibre.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1473779542-2635-1-git-send-email-jbrunet@baylibre.com> References: <1473779542-2635-1-git-send-email-jbrunet@baylibre.com> In-Reply-To: <1473409738-27175-1-git-send-email-jbrunet@baylibre.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add EE domains pins for the NAND flash controller. Even tough we have no driver for the NAND flash controller yet, we need to have these pins in pinctrl as the actual pin are shared with the spifc controller. The bootloader on the S905-P200 setup pinmux for the NAND controller so we need the kernel to properly deactivate this if necessary. Acked-by: Kevin Hilman Signed-off-by: Jerome Brunet --- drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c index 573901887cee..b06cc12f2500 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c @@ -176,6 +176,15 @@ static const unsigned int sdio_cmd_pins[] = { PIN(GPIOX_4, EE_OFF) }; static const unsigned int sdio_clk_pins[] = { PIN(GPIOX_5, EE_OFF) }; static const unsigned int sdio_irq_pins[] = { PIN(GPIOX_7, EE_OFF) }; +static const unsigned int nand_ce0_pins[] = { PIN(BOOT_8, EE_OFF) }; +static const unsigned int nand_ce1_pins[] = { PIN(BOOT_9, EE_OFF) }; +static const unsigned int nand_rb0_pins[] = { PIN(BOOT_10, EE_OFF) }; +static const unsigned int nand_ale_pins[] = { PIN(BOOT_11, EE_OFF) }; +static const unsigned int nand_cle_pins[] = { PIN(BOOT_12, EE_OFF) }; +static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_13, EE_OFF) }; +static const unsigned int nand_ren_wr_pins[] = { PIN(BOOT_14, EE_OFF) }; +static const unsigned int nand_dqs_pins[] = { PIN(BOOT_15, EE_OFF) }; + static const unsigned int uart_tx_a_pins[] = { PIN(GPIOX_12, EE_OFF) }; static const unsigned int uart_rx_a_pins[] = { PIN(GPIOX_13, EE_OFF) }; static const unsigned int uart_cts_a_pins[] = { PIN(GPIOX_14, EE_OFF) }; @@ -439,6 +448,14 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = { GROUP(nor_q, 5, 3), GROUP(nor_c, 5, 2), GROUP(nor_cs, 5, 0), + GROUP(nand_ce0, 4, 26), + GROUP(nand_ce1, 4, 27), + GROUP(nand_rb0, 4, 25), + GROUP(nand_ale, 4, 24), + GROUP(nand_cle, 4, 23), + GROUP(nand_wen_clk, 4, 22), + GROUP(nand_ren_wr, 4, 21), + GROUP(nand_dqs, 4, 20), /* Bank CARD */ GROUP(sdcard_d1, 2, 14), @@ -540,6 +557,11 @@ static const char * const sdio_groups[] = { "sdio_cmd", "sdio_clk", "sdio_irq", }; +static const char * const nand_groups[] = { + "nand_ce0", "nand_ce1", "nand_rb0", "nand_ale", "nand_cle", + "nand_wen_clk", "nand_ren_wr", "nand_dqs", +}; + static const char * const uart_a_groups[] = { "uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a", }; @@ -635,6 +657,7 @@ static struct meson_pmx_func meson_gxbb_periphs_functions[] = { FUNCTION(nor), FUNCTION(sdcard), FUNCTION(sdio), + FUNCTION(nand), FUNCTION(uart_a), FUNCTION(uart_b), FUNCTION(uart_c),