From patchwork Sat Jan 23 16:32:08 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Antoine Tenart X-Patchwork-Id: 572149 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id DCB30140A98 for ; Sun, 24 Jan 2016 03:32:49 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753934AbcAWQcO (ORCPT ); Sat, 23 Jan 2016 11:32:14 -0500 Received: from down.free-electrons.com ([37.187.137.238]:34703 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753580AbcAWQcM (ORCPT ); Sat, 23 Jan 2016 11:32:12 -0500 Received: by mail.free-electrons.com (Postfix, from userid 110) id EB393300; Sat, 23 Jan 2016 17:32:10 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost (21.107.128.77.rev.sfr.net [77.128.107.21]) by mail.free-electrons.com (Postfix) with ESMTPSA id B506D2A4; Sat, 23 Jan 2016 17:32:10 +0100 (CET) From: Antoine Tenart To: ptyser@xes-inc.com Cc: Antoine Tenart , lee.jones@linaro.org, linus.walleij@linaro.org, gnurou@gmail.com, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] mfd: lpc_ich: use a correct mask for the GPIO base address Date: Sat, 23 Jan 2016 17:32:08 +0100 Message-Id: <1453566729-30220-3-git-send-email-antoine.tenart@free-electrons.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1453566729-30220-1-git-send-email-antoine.tenart@free-electrons.com> References: <1453566729-30220-1-git-send-email-antoine.tenart@free-electrons.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The GPIO base address is read from the GPIOBASE register. The first bit must be cleared as it can be hardwired to 1 to represent the i/o space. Other bits are either containing the base address of are reserved. They should not be cleared as all the chipsets do not have the same reserved bits. Signed-off-by: Antoine Tenart --- drivers/mfd/lpc_ich.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c index b514f3cf140d..f13a5ded3958 100644 --- a/drivers/mfd/lpc_ich.c +++ b/drivers/mfd/lpc_ich.c @@ -921,7 +921,10 @@ static int lpc_ich_init_gpio(struct pci_dev *dev) gpe0_done: /* Setup GPIO base register */ pci_read_config_dword(dev, priv->gbase, &base_addr_cfg); - base_addr = base_addr_cfg & 0x0000ff80; + + /* Clear the i/o flag */ + base_addr = base_addr_cfg & ~BIT(0); + if (!base_addr) { dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n"); ret = -ENODEV;