From patchwork Tue Jun 9 23:24:29 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Hutchings X-Patchwork-Id: 482404 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id BE81D140758 for ; Wed, 10 Jun 2015 09:24:35 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753434AbbFIXYf (ORCPT ); Tue, 9 Jun 2015 19:24:35 -0400 Received: from ducie-dc1.codethink.co.uk ([185.25.241.215]:34437 "EHLO ducie-dc1.codethink.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752669AbbFIXYe (ORCPT ); Tue, 9 Jun 2015 19:24:34 -0400 Received: from localhost (localhost [127.0.0.1]) by ducie-dc1.codethink.co.uk (Postfix) with ESMTP id E4A5A46174E; Wed, 10 Jun 2015 00:24:32 +0100 (BST) X-Virus-Scanned: Debian amavisd-new at ducie-dc1.codethink.co.uk Received: from ducie-dc1.codethink.co.uk ([127.0.0.1]) by localhost (ducie-dc1.codethink.co.uk [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id BhhrIxLOYMvf; Wed, 10 Jun 2015 00:24:30 +0100 (BST) Received: from xylophone (shadbolt.e.decadent.org.uk [88.96.1.126]) by ducie-dc1.codethink.co.uk (Postfix) with ESMTPSA id DB25D461762; Wed, 10 Jun 2015 00:24:29 +0100 (BST) Message-ID: <1433892269.12074.55.camel@codethink.co.uk> Subject: [PATCH v2 6/6] ARM: shmobile: lager: Enable UHS-I SDR-50 From: Ben Hutchings To: Ian Molton , linux-mmc@vger.kernel.org Cc: linux-sh@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@lists.codethink.co.uk, Sergei Shtylyov , Simon Horman , Kuninori Morimoto Date: Wed, 10 Jun 2015 00:24:29 +0100 In-Reply-To: <1433892104.12074.49.camel@codethink.co.uk> References: <1433892104.12074.49.camel@codethink.co.uk> Organization: Codethink Ltd. X-Mailer: Evolution 3.12.9-1+b1 Mime-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add the "1v8" pinctrl state and sd-uhs-sdr50 property to SDHI{0,2}. Signed-off-by: Ben Hutchings --- arch/arm/boot/dts/r8a7790-lager.dts | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 5f68e53c58ae..ff5eea8ea765 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -314,11 +314,21 @@ renesas,function = "sdhi0"; }; + sdhi0_pins_1v8: sd0_1v8 { + renesas,groups = "sdhi0_data4", "sdhi0_ctrl"; + renesas,function = "sdhi0_1v8"; + }; + sdhi2_pins: sd2 { renesas,groups = "sdhi2_data4", "sdhi2_ctrl"; renesas,function = "sdhi2"; }; + sdhi2_pins_1v8: sd2_1v8 { + renesas,groups = "sdhi2_data4", "sdhi2_ctrl"; + renesas,function = "sdhi2_1v8"; + }; + mmc1_pins: mmc1 { renesas,groups = "mmc1_data8", "mmc1_ctrl"; renesas,function = "mmc1"; @@ -486,7 +496,8 @@ &sdhi0 { pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&sdhi0_pins_1v8>; + pinctrl-names = "default", "1v8"; assigned-clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; assigned-clock-rates = <156000000>; @@ -494,12 +505,14 @@ vmmc-supply = <&vcc_sdhi0>; vqmmc-supply = <&vccq_sdhi0>; cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; + sd-uhs-sdr50; status = "okay"; }; &sdhi2 { pinctrl-0 = <&sdhi2_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&sdhi2_pins_1v8>; + pinctrl-names = "default", "1v8"; assigned-clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; assigned-clock-rates = <97500000>; @@ -507,6 +520,7 @@ vmmc-supply = <&vcc_sdhi2>; vqmmc-supply = <&vccq_sdhi2>; cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; + sd-uhs-sdr50; status = "okay"; };