From patchwork Wed May 20 08:42:31 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 474235 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 9BDD6140281 for ; Wed, 20 May 2015 18:46:22 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751609AbbETIqW (ORCPT ); Wed, 20 May 2015 04:46:22 -0400 Received: from condef007-v.nifty.com ([210.131.4.244]:45613 "EHLO condef007-v.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751504AbbETIqV (ORCPT ); Wed, 20 May 2015 04:46:21 -0400 Received: from conuserg012-v.nifty.com ([10.16.229.199])by condef007-v.nifty.com with ESMTP id t4K8hdb1018387 for ; Wed, 20 May 2015 17:43:39 +0900 Received: from beagle.diag.org (KD106139063102.au-net.ne.jp [106.139.63.102]) (authenticated) by conuserg012-v.nifty.com with ESMTP id t4K8gJQD000882; Wed, 20 May 2015 17:42:25 +0900 X-Nifty-SrcIP: [106.139.63.102] From: Masahiro Yamada To: linux-gpio@vger.kernel.org Cc: Masahiro Yamada , =?UTF-8?q?S=C3=B6ren=20Brinkmann?= , Michal Simek , Linus Walleij , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [RESEND PATCH 2/2] pinctrl: zynq: fix offset address for {SD0, SD1}_WP_CD_SEL Date: Wed, 20 May 2015 17:42:31 +0900 Message-Id: <1432111351-21336-3-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1432111351-21336-1-git-send-email-yamada.masahiro@socionext.com> References: <1432111351-21336-1-git-send-email-yamada.masahiro@socionext.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The address for SD0_WP_CD_SEL, SD1_WP_CD_SEL is 0xf8000830, 0xf8000834, respectively. Each offset address must be prefixed with 0x. Signed-off-by: Masahiro Yamada --- drivers/pinctrl/pinctrl-zynq.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c index 77c5a98..04748a4 100644 --- a/drivers/pinctrl/pinctrl-zynq.c +++ b/drivers/pinctrl/pinctrl-zynq.c @@ -745,15 +745,15 @@ static const struct zynq_pinmux_function zynq_pmux_functions[] = { DEFINE_ZYNQ_PINMUX_FUNCTION(spi1, 0x50), DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0, 0x40), DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0_pc, 0xc), - DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_wp, 0, 130, ZYNQ_SDIO_WP_MASK, + DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_wp, 0, 0x130, ZYNQ_SDIO_WP_MASK, ZYNQ_SDIO_WP_SHIFT), - DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_cd, 0, 130, ZYNQ_SDIO_CD_MASK, + DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_cd, 0, 0x130, ZYNQ_SDIO_CD_MASK, ZYNQ_SDIO_CD_SHIFT), DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1, 0x40), DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1_pc, 0xc), - DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_wp, 0, 134, ZYNQ_SDIO_WP_MASK, + DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_wp, 0, 0x134, ZYNQ_SDIO_WP_MASK, ZYNQ_SDIO_WP_SHIFT), - DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_cd, 0, 134, ZYNQ_SDIO_CD_MASK, + DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_cd, 0, 0x134, ZYNQ_SDIO_CD_MASK, ZYNQ_SDIO_CD_SHIFT), DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor, 4), DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor_cs1, 8),