From patchwork Thu May 14 10:48:54 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 472305 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 5016F1402B3 for ; Thu, 14 May 2015 20:49:13 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932880AbbENKtM (ORCPT ); Thu, 14 May 2015 06:49:12 -0400 Received: from relmlor4.renesas.com ([210.160.252.174]:17455 "EHLO relmlie3.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932742AbbENKtK (ORCPT ); Thu, 14 May 2015 06:49:10 -0400 Received: from unknown (HELO relmlir1.idc.renesas.com) ([10.200.68.151]) by relmlie3.idc.renesas.com with ESMTP; 14 May 2015 19:49:08 +0900 Received: from relmlac1.idc.renesas.com (relmlac1.idc.renesas.com [10.200.69.21]) by relmlir1.idc.renesas.com (Postfix) with ESMTP id 0EFA2551C7; Thu, 14 May 2015 19:49:08 +0900 (JST) Received: by relmlac1.idc.renesas.com (Postfix, from userid 0) id E94B38002E; Thu, 14 May 2015 19:49:07 +0900 (JST) Received: from relmlac1.idc.renesas.com (localhost [127.0.0.1]) by relmlac1.idc.renesas.com (Postfix) with ESMTP id E39208002D; Thu, 14 May 2015 19:49:07 +0900 (JST) Received: from relmlii2.idc.renesas.com [10.200.68.66] by relmlac1.idc.renesas.com with ESMTP id VAU06107; Thu, 14 May 2015 19:49:07 +0900 X-IronPort-AV: E=Sophos;i="5.13,427,1427727600"; d="scan'208";a="187349390" Received: from mail-sg1lp0093.outbound.protection.outlook.com (HELO APAC01-SG1-obe.outbound.protection.outlook.com) ([207.46.51.93]) by relmlii2.idc.renesas.com with ESMTP/TLS/AES256-SHA; 14 May 2015 19:49:07 +0900 Authentication-Results: ideasonboard.com; dkim=none (message not signed) header.d=none; Received: from localhost (211.11.155.147) by SG2PR06MB0917.apcprd06.prod.outlook.com (25.162.200.158) with Microsoft SMTP Server (TLS) id 15.1.160.19; Thu, 14 May 2015 10:49:05 +0000 From: Yoshihiro Shimoda To: , CC: , , Yoshihiro Shimoda Subject: [PATCH] sh-pfc: r8a7790: Add PWM pin groups and functions Date: Thu, 14 May 2015 19:48:54 +0900 Message-ID: <1431600534-4360-1-git-send-email-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 1.9.4.msysgit.1 MIME-Version: 1.0 X-Originating-IP: [211.11.155.147] X-ClientProxiedBy: OS2PR01CA0030.jpnprd01.prod.outlook.com (25.164.161.140) To SG2PR06MB0917.apcprd06.prod.outlook.com (25.162.200.158) X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:SG2PR06MB0917; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5005006)(3002001); SRVR:SG2PR06MB0917; BCL:0; PCL:0; RULEID:; SRVR:SG2PR06MB0917; X-Forefront-PRVS: 0576145E86 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10019020)(6009001)(6069001)(50466002)(48376002)(36756003)(87976001)(40100003)(122386002)(42382002)(229853001)(33646002)(50986999)(47776003)(66066001)(62966003)(77156002)(19580405001)(19580395003)(5001960100002)(107886002)(92566002)(78352002)(76506005)(42186005)(5001770100001)(189998001)(50226001)(46102003)(4001430100001)(2101003); DIR:OUT; SFP:1102; SCL:1; SRVR:SG2PR06MB0917; H:localhost; FPR:; SPF:None; MLV:sfv; LANG:en; X-OriginatorOrg: renesas.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 May 2015 10:49:05.5394 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: SG2PR06MB0917 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Signed-off-by: Yoshihiro Shimoda Reviewed-by: Geert Uytterhoeven Acked-by: Laurent Pinchart --- This patch is based on linux-pinctrl.git / for-next branch. (commit id = 1050c8f7b3f8f97ed3514ce800e7206207d5bbf9) I will write a patch for r8a7791 PWM later because I'm not sure that this patch is good or not. drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 101 +++++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index 22a5470..baab81e 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -2664,6 +2664,61 @@ static const unsigned int msiof3_tx_b_pins[] = { static const unsigned int msiof3_tx_b_mux[] = { MSIOF3_TXD_B_MARK, }; +/* - PWM -------------------------------------------------------------------- */ +static const unsigned int pwm0_pins[] = { + RCAR_GP_PIN(5, 29), +}; +static const unsigned int pwm0_mux[] = { + PWM0_MARK, +}; +static const unsigned int pwm0_b_pins[] = { + RCAR_GP_PIN(4, 30), +}; +static const unsigned int pwm0_b_mux[] = { + PWM0_B_MARK, +}; +static const unsigned int pwm1_pins[] = { + RCAR_GP_PIN(5, 30), +}; +static const unsigned int pwm1_mux[] = { + PWM1_MARK, +}; +static const unsigned int pwm1_b_pins[] = { + RCAR_GP_PIN(4, 31), +}; +static const unsigned int pwm1_b_mux[] = { + PWM1_B_MARK, +}; +static const unsigned int pwm2_pins[] = { + RCAR_GP_PIN(5, 31), +}; +static const unsigned int pwm2_mux[] = { + PWM2_MARK, +}; +static const unsigned int pwm3_pins[] = { + RCAR_GP_PIN(0, 16), +}; +static const unsigned int pwm3_mux[] = { + PWM3_MARK, +}; +static const unsigned int pwm4_pins[] = { + RCAR_GP_PIN(0, 17), +}; +static const unsigned int pwm4_mux[] = { + PWM4_MARK, +}; +static const unsigned int pwm5_pins[] = { + RCAR_GP_PIN(0, 18), +}; +static const unsigned int pwm5_mux[] = { + PWM5_MARK, +}; +static const unsigned int pwm6_pins[] = { + RCAR_GP_PIN(0, 19), +}; +static const unsigned int pwm6_mux[] = { + PWM6_MARK, +}; /* - QSPI ------------------------------------------------------------------- */ static const unsigned int qspi_ctrl_pins[] = { /* SPCLK, SSL */ @@ -4008,6 +4063,15 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(msiof3_sync_b), SH_PFC_PIN_GROUP(msiof3_rx_b), SH_PFC_PIN_GROUP(msiof3_tx_b), + SH_PFC_PIN_GROUP(pwm0), + SH_PFC_PIN_GROUP(pwm0_b), + SH_PFC_PIN_GROUP(pwm1), + SH_PFC_PIN_GROUP(pwm1_b), + SH_PFC_PIN_GROUP(pwm2), + SH_PFC_PIN_GROUP(pwm3), + SH_PFC_PIN_GROUP(pwm4), + SH_PFC_PIN_GROUP(pwm5), + SH_PFC_PIN_GROUP(pwm6), SH_PFC_PIN_GROUP(qspi_ctrl), SH_PFC_PIN_GROUP(qspi_data2), SH_PFC_PIN_GROUP(qspi_data4), @@ -4364,6 +4428,36 @@ static const char * const msiof3_groups[] = { "msiof3_tx_b", }; +static const char * const pwm0_groups[] = { + "pwm0", + "pwm0_b", +}; + +static const char * const pwm1_groups[] = { + "pwm1", + "pwm1_b", +}; + +static const char * const pwm2_groups[] = { + "pwm2", +}; + +static const char * const pwm3_groups[] = { + "pwm3", +}; + +static const char * const pwm4_groups[] = { + "pwm4", +}; + +static const char * const pwm5_groups[] = { + "pwm5", +}; + +static const char * const pwm6_groups[] = { + "pwm6", +}; + static const char * const qspi_groups[] = { "qspi_ctrl", "qspi_data2", @@ -4621,6 +4715,13 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), SH_PFC_FUNCTION(msiof3), + SH_PFC_FUNCTION(pwm0), + SH_PFC_FUNCTION(pwm1), + SH_PFC_FUNCTION(pwm2), + SH_PFC_FUNCTION(pwm3), + SH_PFC_FUNCTION(pwm4), + SH_PFC_FUNCTION(pwm5), + SH_PFC_FUNCTION(pwm6), SH_PFC_FUNCTION(qspi), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1),