From patchwork Sat May 9 07:53:44 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Maxime Coquelin X-Patchwork-Id: 470298 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id E5E9D140281 for ; Sat, 9 May 2015 17:59:42 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=zrLezvSU; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753765AbbEIHyR (ORCPT ); Sat, 9 May 2015 03:54:17 -0400 Received: from mail-wi0-f181.google.com ([209.85.212.181]:37144 "EHLO mail-wi0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753652AbbEIHyM (ORCPT ); Sat, 9 May 2015 03:54:12 -0400 Received: by widdi4 with SMTP id di4so48826974wid.0; Sat, 09 May 2015 00:54:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; bh=5xXCh6t20qwglphleqEzIZ0Y4Q8ewFWz463Pq+UnjGM=; b=zrLezvSU/In1B4sCmIzINUmXtMbmMv/+wC1SEMVD28ycAb3pb7wrd9SoXftQGkzTQ3 nqrpk3hHPqxLt2O46tAhTLC6VJCC6qoI9ERFvjPSYC1sGJ9MceF2DgDrS07Y7B56CGw+ +xOCDzJkwz556EK2ecCOkX/5B+uAB9nEgLxApxwZb4MAn0EunQ9+A7guS57+rw5n1ThV Y3mHaZaELVujQWo+ZgK/QUjfVwply5Y8nv260tJdn1ZRBD6+D4AQCSPh5vyCk9KFmoc+ tKSyGK7ZwR/hytmGUj+OZDKvndocSJ9eKBC/ql2w+jDJD99/ksFFOdSTwd5r/CTS9Ebq godg== X-Received: by 10.194.159.99 with SMTP id xb3mr3165681wjb.57.1431158050386; Sat, 09 May 2015 00:54:10 -0700 (PDT) Received: from lmecul0520.st.com. (213.143.7.84.rev.sfr.net. [84.7.143.213]) by mx.google.com with ESMTPSA id z12sm12098020wjq.12.2015.05.09.00.54.07 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 09 May 2015 00:54:09 -0700 (PDT) From: Maxime Coquelin To: u.kleine-koenig@pengutronix.de, afaerber@suse.de, geert@linux-m68k.org, Rob Herring , Philipp Zabel , Linus Walleij , Arnd Bergmann , stefan@agner.ch, pmeerw@pmeerw.net, pebolle@tiscali.nl, peter@hurleysoftware.com, andy.shevchenko@gmail.com, cw00.choi@samsung.com, Russell King , Daniel Lezcano , joe@perches.com, Vladimir Zapolskiy , lee.jones@linaro.org, Daniel Thompson Cc: Jonathan Corbet , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Andrew Morton , "David S. Miller" , Mauro Carvalho Chehab , Antti Palosaari , Tejun Heo , Will Deacon , Nikolay Borisov , Rusty Russell , Kees Cook , Michal Marek , linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, mcoquelin.stm32@gmail.com, Nicolae Rosia , Kamil Lulko Subject: [PATCH v8 02/16] ARM: ARMv7-M: Enlarge vector table up to 256 entries Date: Sat, 9 May 2015 09:53:44 +0200 Message-Id: <1431158038-3813-3-git-send-email-mcoquelin.stm32@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1431158038-3813-1-git-send-email-mcoquelin.stm32@gmail.com> References: <1431158038-3813-1-git-send-email-mcoquelin.stm32@gmail.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From Cortex-M reference manuals, the nvic supports up to 240 interrupts. So the number of entries in vectors table is up to 256. This patch adds a new config flag to specify the number of external interrupts. Some ifdeferies are added in order to respect the natural alignment without wasting too much space on smaller systems. Acked-by: Uwe Kleine-König Acked-by: Stefan Agner Tested-by: Chanwoo Choi Signed-off-by: Maxime Coquelin --- arch/arm/kernel/entry-v7m.S | 13 +++++++++---- arch/arm/mm/Kconfig | 15 +++++++++++++++ 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/arch/arm/kernel/entry-v7m.S b/arch/arm/kernel/entry-v7m.S index 8944f49..b6c8bb9 100644 --- a/arch/arm/kernel/entry-v7m.S +++ b/arch/arm/kernel/entry-v7m.S @@ -117,9 +117,14 @@ ENTRY(__switch_to) ENDPROC(__switch_to) .data - .align 8 +#if CONFIG_CPU_V7M_NUM_IRQ <= 112 + .align 9 +#else + .align 10 +#endif + /* - * Vector table (64 words => 256 bytes natural alignment) + * Vector table (Natural alignment need to be ensured) */ ENTRY(vector_table) .long 0 @ 0 - Reset stack pointer @@ -138,6 +143,6 @@ ENTRY(vector_table) .long __invalid_entry @ 13 - Reserved .long __pendsv_entry @ 14 - PendSV .long __invalid_entry @ 15 - SysTick - .rept 64 - 16 - .long __irq_entry @ 16..64 - External Interrupts + .rept CONFIG_CPU_V7M_NUM_IRQ + .long __irq_entry @ External Interrupts .endr diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index b4f92b9..6173aa3 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -604,6 +604,21 @@ config CPU_USE_DOMAINS This option enables or disables the use of domain switching via the set_fs() function. +config CPU_V7M_NUM_IRQ + int "Number of external interrupts connected to the NVIC" + depends on CPU_V7M + default 90 if ARCH_STM32 + default 38 if ARCH_EFM32 + default 240 + help + This option indicates the number of interrupts connected to the NVIC. + The value can be larger than the real number of interrupts supported + by the system, but must not be lower. + The default value is 240, corresponding to the maximum number of + interrupts supported by the NVIC on Cortex-M family. + + If unsure, keep default value. + # # CPU supports 36-bit I/O #