From patchwork Tue Apr 21 14:53:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 463167 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 85029140213 for ; Wed, 22 Apr 2015 00:56:38 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755075AbbDUO4i (ORCPT ); Tue, 21 Apr 2015 10:56:38 -0400 Received: from mail-by2on0115.outbound.protection.outlook.com ([207.46.100.115]:23057 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1755024AbbDUO4h (ORCPT ); Tue, 21 Apr 2015 10:56:37 -0400 Received: from BN3PR0301CA0020.namprd03.prod.outlook.com (25.160.180.158) by BLUPR03MB1361.namprd03.prod.outlook.com (25.163.80.27) with Microsoft SMTP Server (TLS) id 15.1.136.25; Tue, 21 Apr 2015 14:56:34 +0000 Received: from BY2FFO11FD003.protection.gbl (2a01:111:f400:7c0c::143) by BN3PR0301CA0020.outlook.office365.com (2a01:111:e400:4000::30) with Microsoft SMTP Server (TLS) id 15.1.136.25 via Frontend Transport; Tue, 21 Apr 2015 14:56:34 +0000 Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=freescale.com; freescale.mail.onmicrosoft.com; dkim=none (message not signed) header.d=none; Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Received: from az84smr01.freescale.net (192.88.158.2) by BY2FFO11FD003.mail.protection.outlook.com (10.1.14.125) with Microsoft SMTP Server (TLS) id 15.1.148.11 via Frontend Transport; Tue, 21 Apr 2015 14:56:34 +0000 Received: from shlinux2.ap.freescale.net (shlinux2.ap.freescale.net [10.192.224.44]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id t3LEuBP3005293; Tue, 21 Apr 2015 07:56:31 -0700 From: To: , , , CC: , , , Anson Huang , Frank Li Subject: [PATCH v5 07/11] ARM: imx: add msl support for imx7d Date: Tue, 21 Apr 2015 22:53:23 +0800 Message-ID: <1429628007-8892-8-git-send-email-Frank.Li@freescale.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1429628007-8892-1-git-send-email-Frank.Li@freescale.com> References: <1429628007-8892-1-git-send-email-Frank.Li@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:NLI; EFV:NLI; BMV:1; SFV:NSPM; SFS:(10019020)(6009001)(339900001)(199003)(189002)(50466002)(77096005)(77156002)(62966003)(47776003)(19580405001)(50226001)(2201001)(5001770100001)(86362001)(575784001)(2950100001)(19580395003)(92566002)(48376002)(36756003)(229853001)(105606002)(106466001)(87936001)(76176999)(50986999)(104016003)(86152002)(6806004)(85426001)(46102003)(4001430100001); DIR:OUT; SFP:1102; SCL:1; SRVR:BLUPR03MB1361; H:az84smr01.freescale.net; FPR:; SPF:Fail; MLV:sfv; A:1; MX:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BLUPR03MB1361; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5005006)(5002010); SRVR:BLUPR03MB1361; BCL:0; PCL:0; RULEID:; SRVR:BLUPR03MB1361; X-Forefront-PRVS: 0553CBB77A X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Apr 2015 14:56:34.1627 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.158.2]; Helo=[az84smr01.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR03MB1361 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Anson Huang Add i.MX7D MSL support. Signed-off-by: Anson Huang Signed-off-by: Frank Li --- arch/arm/mach-imx/Kconfig | 11 ++++++++++ arch/arm/mach-imx/Makefile | 1 + arch/arm/mach-imx/anatop.c | 5 ++++- arch/arm/mach-imx/common.h | 1 + arch/arm/mach-imx/cpu.c | 3 +++ arch/arm/mach-imx/hardware.h | 7 ++++++- arch/arm/mach-imx/mach-imx7d.c | 47 ++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-imx/mx7.h | 38 ++++++++++++++++++++++++++++++++++ arch/arm/mach-imx/mxc.h | 8 ++++++- arch/arm/mach-imx/platsmp.c | 19 +++++++++++++++++ 10 files changed, 137 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mach-imx/mach-imx7d.c create mode 100644 arch/arm/mach-imx/mx7.h diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 3a3d3e9..162f2c3 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -582,6 +582,17 @@ config SOC_IMX6SX help This enables support for Freescale i.MX6 SoloX processor. +config SOC_IMX7 + bool + select ARM_GIC + +config SOC_IMX7D + bool "i.MX7 Dual support" + select SOC_IMX7 + select PINCTRL_IMX7D + help + This enables support for Freescale i.MX7 Dual processor. + config SOC_VF610 bool "Vybrid Family VF610 support" select IRQ_DOMAIN_HIERARCHY diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 3244cf1..3d9d755 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -90,6 +90,7 @@ endif obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o mach-imx6sx.o +obj-$(CONFIG_SOC_IMX7D) += clk-imx7d.o mach-imx7d.o ifeq ($(CONFIG_SUSPEND),y) AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c index 7f262fe..231bb25 100644 --- a/arch/arm/mach-imx/anatop.c +++ b/arch/arm/mach-imx/anatop.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Freescale Semiconductor, Inc. + * Copyright (C) 2013-2015 Freescale Semiconductor, Inc. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -28,6 +28,7 @@ #define ANADIG_USB2_CHRG_DETECT 0x210 #define ANADIG_DIGPROG 0x260 #define ANADIG_DIGPROG_IMX6SL 0x280 +#define ANADIG_DIGPROG_IMX7D 0x800 #define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000 #define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x8 @@ -121,6 +122,8 @@ void __init imx_init_revision_from_anatop(void) WARN_ON(!anatop_base); if (of_device_is_compatible(np, "fsl,imx6sl-anatop")) offset = ANADIG_DIGPROG_IMX6SL; + if (of_device_is_compatible(np, "fsl,imx7d-anatop")) + offset = ANADIG_DIGPROG_IMX7D; digprog = readl_relaxed(anatop_base + offset); iounmap(anatop_base); diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 0f04e30..978c1a4 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -157,5 +157,6 @@ static inline void imx_init_l2cache(void) {} extern struct smp_operations imx_smp_ops; extern struct smp_operations ls1021a_smp_ops; +extern struct smp_operations imx_ca7_smp_ops; #endif diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index df42c14..a7fa92a 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -130,6 +130,9 @@ struct device * __init imx_soc_device_init(void) case MXC_CPU_IMX6Q: soc_id = "i.MX6Q"; break; + case MXC_CPU_IMX7D: + soc_id = "i.MX7D"; + break; default: soc_id = "Unknown"; } diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h index 76af2c0..747fe0b 100644 --- a/arch/arm/mach-imx/hardware.h +++ b/arch/arm/mach-imx/hardware.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2007, 2014 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2007, 2014-2015 Freescale Semiconductor, Inc. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de * * This program is free software; you can redistribute it and/or @@ -93,6 +93,10 @@ * CCM 0x020c4000+0x004000 -> 0xf42c4000+0x004000 * ANATOP 0x020c8000+0x004000 -> 0xf42c8000+0x004000 * UART4 0x021f0000+0x004000 -> 0xf42f0000+0x004000 + * mx7d: + * CCM 0x30380000+0x010000 -> 0xf5380000+0x010000 + * ANATOP 0x30360000+0x010000 -> 0xf5360000+0x010000 + * UART1 0x30860000+0x010000 -> 0xf5860000+0x010000 */ #define IMX_IO_P2V(x) ( \ (((x) & 0x80000000) >> 7) | \ @@ -112,6 +116,7 @@ #include "mx21.h" #include "mx27.h" #include "mx1.h" +#include "mx7.h" #define imx_map_entry(soc, name, _type) { \ .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \ diff --git a/arch/arm/mach-imx/mach-imx7d.c b/arch/arm/mach-imx/mach-imx7d.c new file mode 100644 index 0000000..7d8e126 --- /dev/null +++ b/arch/arm/mach-imx/mach-imx7d.c @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include "common.h" + +static void __init imx7d_init_machine(void) +{ + struct device *parent; + + parent = imx_soc_device_init(); + if (parent == NULL) + pr_warn("failed to initialize soc device\n"); + + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + imx_anatop_init(); +} + +static void __init imx7d_init_irq(void) +{ + imx_init_revision_from_anatop(); + imx_src_init(); + irqchip_init(); +} + +static const char *imx7d_dt_compat[] __initconst = { + "fsl,imx7d", + NULL, +}; + +DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual (Device Tree)") + .smp = smp_ops(imx_ca7_smp_ops), + .init_irq = imx7d_init_irq, + .init_machine = imx7d_init_machine, + .dt_compat = imx7d_dt_compat, + .restart = mxc_restart, +MACHINE_END diff --git a/arch/arm/mach-imx/mx7.h b/arch/arm/mach-imx/mx7.h new file mode 100644 index 0000000..bfef936 --- /dev/null +++ b/arch/arm/mach-imx/mx7.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * * This program is free software; you can redistribute it and/or modify + * * it under the terms of the GNU General Public License version 2 as + * * published by the Free Software Foundation. + * */ + +#ifndef __ASM_ARCH_MX7_IOMAP_H__ +#define __ASM_ARCH_MX7_IOMAP_H__ + +#define MX7D_IO_P2V(x) IMX_IO_P2V(x) +#define MX7D_IO_ADDRESS(x) IOMEM(MX7D_IO_P2V(x)) + +#define MX7D_CCM_BASE_ADDR 0x30380000 +#define MX7D_CCM_SIZE 0x10000 +#define MX7D_IOMUXC_BASE_ADDR 0x30330000 +#define MX7D_IOMUXC_SIZE 0x10000 +#define MX7D_ANATOP_BASE_ADDR 0x30360000 +#define MX7D_ANATOP_SIZE 0x10000 +#define MX7D_GPC_BASE_ADDR 0x303a0000 +#define MX7D_GPC_SIZE 0x10000 +#define MX7D_SRC_BASE_ADDR 0x30390000 +#define MX7D_SRC_SIZE 0x10000 +#define MX7D_DDRC_BASE_ADDR 0x307a0000 +#define MX7D_DDRC_SIZE 0x10000 +#define MX7D_AIPS1_BASE_ADDR 0x30000000 +#define MX7D_AIPS1_SIZE 0x400000 +#define MX7D_AIPS2_BASE_ADDR 0x30400000 +#define MX7D_AIPS2_SIZE 0x400000 +#define MX7D_AIPS3_BASE_ADDR 0x30900000 +#define MX7D_AIPS3_SIZE 0x300000 + +#define TT_ATTRIB_NON_CACHEABLE_1M 0x802 +#define MX7_IRAM_TLB_SIZE 0x4000 +#endif diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h index 4c1343d..e55c1e7 100644 --- a/arch/arm/mach-imx/mxc.h +++ b/arch/arm/mach-imx/mxc.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2007, 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2007, 2010-2015 Freescale Semiconductor, Inc. * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) * * This program is free software; you can redistribute it and/or @@ -38,6 +38,7 @@ #define MXC_CPU_IMX6DL 0x61 #define MXC_CPU_IMX6SX 0x62 #define MXC_CPU_IMX6Q 0x63 +#define MXC_CPU_IMX7D 0x72 #define IMX_CHIP_REVISION_1_0 0x10 #define IMX_CHIP_REVISION_1_1 0x11 @@ -185,6 +186,11 @@ static inline bool cpu_is_imx6q(void) return __mxc_cpu_type == MXC_CPU_IMX6Q; } +static inline bool cpu_is_imx7d(void) +{ + return __mxc_cpu_type == MXC_CPU_IMX7D; +} + struct cpu_op { u32 cpu_rate; }; diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c index 7f27001..a0d7774 100644 --- a/arch/arm/mach-imx/platsmp.c +++ b/arch/arm/mach-imx/platsmp.c @@ -98,6 +98,25 @@ struct smp_operations imx_smp_ops __initdata = { #endif }; + +static void __init imx_ca7_smp_init_cpus(void) +{ + int i, ncores; + unsigned long val; + + asm volatile("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); + ncores = ((val >> 24) & 0x3) + 1; + if (setup_max_cpus < ncores) + ncores = (setup_max_cpus) ? setup_max_cpus : 1; + + for (i = ncores; i < NR_CPUS; i++) + set_cpu_possible(i, false); +} + +struct smp_operations imx_ca7_smp_ops __initdata = { + .smp_init_cpus = imx_ca7_smp_init_cpus +}; + #define DCFG_CCSR_SCRATCHRW1 0x200 static int ls1021a_boot_secondary(unsigned int cpu, struct task_struct *idle)