From patchwork Fri Apr 3 21:16:03 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joachim Eastwood X-Patchwork-Id: 458070 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id C3FD314010F for ; Sat, 4 Apr 2015 08:16:47 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="verification failed; unprotected key" header.d=gmail.com header.i=@gmail.com header.b=AANJ0ID6; dkim-adsp=none (unprotected policy); dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752514AbbDCVQq (ORCPT ); Fri, 3 Apr 2015 17:16:46 -0400 Received: from mail-la0-f54.google.com ([209.85.215.54]:35116 "EHLO mail-la0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752112AbbDCVQo (ORCPT ); Fri, 3 Apr 2015 17:16:44 -0400 Received: by lahf3 with SMTP id f3so85667659lah.2; Fri, 03 Apr 2015 14:16:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uhTxNxO64DLyBfXMHV7oiun7iP3/xQekg7pHiFuO7Sg=; b=AANJ0ID6r0T83itzNwjsIZ3i57ZVvU/l7lEw6KsUv5d5hkhubWEFYwK98FzukJgmIE GHEKduebsjNl4ZYUaqZfv/0j7n14pVOTKUngHKeBphcWWgF2mCpFIQdwnI29Fze71gBk bagWljg8AwE5UzxEfZQCRpzSJc0N0cJX/4NC0h5PWOhTJVbIAYxwP2IQhW47FGvJJd1J FqY6PJv5cH1CliVJ5Y4OcdqkSSgfvLRkUI7J9WU+kaOZFBCnDXWIe10pHpxEQzBtGhF2 atDRK1rRFfKAae9PcQQQhjfGuLTxnu4zKBbTDUtsagit9q0EgNvTcylXY69H2NHMwZQR GrHg== X-Received: by 10.152.45.101 with SMTP id l5mr3509604lam.95.1428095802383; Fri, 03 Apr 2015 14:16:42 -0700 (PDT) Received: from localhost.localdomain ([90.149.48.183]) by mx.google.com with ESMTPSA id lf12sm1015786lac.38.2015.04.03.14.16.41 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 03 Apr 2015 14:16:41 -0700 (PDT) From: Joachim Eastwood To: linus.walleij@linaro.org, gnurou@gmail.com, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: arnd@arndb.de, devicetree@vger.kernel.org, ariel.dalessandro@gmail.com, ezequiel@vanguardiasur.com.ar, Joachim Eastwood Subject: [PATCH 2/6] doc: dt: add documentation for lpc1850-scu pinctrl driver Date: Fri, 3 Apr 2015 23:16:03 +0200 Message-Id: <1428095767-6286-3-git-send-email-manabian@gmail.com> X-Mailer: git-send-email 1.8.0 In-Reply-To: <1428095767-6286-1-git-send-email-manabian@gmail.com> References: <1428095767-6286-1-git-send-email-manabian@gmail.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Signed-off-by: Joachim Eastwood --- .../bindings/pinctrl/nxp,lpc1850-scu.txt | 57 ++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nxp,lpc1850-scu.txt diff --git a/Documentation/devicetree/bindings/pinctrl/nxp,lpc1850-scu.txt b/Documentation/devicetree/bindings/pinctrl/nxp,lpc1850-scu.txt new file mode 100644 index 000000000000..b75eaa2517eb --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nxp,lpc1850-scu.txt @@ -0,0 +1,57 @@ +NXP LPC18xx/43xx SCU pin controller Device Tree Bindings +-------------------------------------------------------- + +Required properties: +- compatible : Should be "nxp,lpc1850-scu" +- reg : Address and length of the register set for the device +- clocks : Clock specifier (see clock bindings for details) + +The lpc1850-scu driver uses the generic pin multiplexing and generic pin +configuration documented in pinctrl-bindings.txt. + +The following generic nodes are supported: + - function + - pins + - bias-disable + - bias-pull-up + - bias-pull-down + - drive-strength + - input-enable + - input-disable + - input-schmitt-enable + - input-schmitt-disable + - slew-rate + +Not all pins support all properties so either refer to the NXP 1850/4350 +user manual or the pin table in the pinctrl-lpc18xx driver for supported +pin properties. + +Example: +pinctrl: scu@40086000 { + compatible = "nxp,lpc1850-scu"; + reg = <0x40086000 0x1000>; + clocks = <&ccu1 CLK_CPU_SCU>; + + i2c0_pins: i2c0-pins { + i2c0_pins_cfg { + pins = "i2c0_scl", "i2c0_sda"; + function = "i2c0"; + input-enable; + }; + }; + + uart0_pins: uart0-pins { + uart0_rx_cfg { + pins = "pf_11"; + function = "uart0"; + bias-disable; + input-enable; + }; + + uart0_tx_cfg { + pins = "pf_10"; + function = "uart0"; + bias-disable; + }; + }; +};