From patchwork Fri Mar 27 09:44:26 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ken Xue X-Patchwork-Id: 455366 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3E6BD14007F for ; Fri, 27 Mar 2015 21:11:51 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751555AbbC0KLt (ORCPT ); Fri, 27 Mar 2015 06:11:49 -0400 Received: from mail-bl2on0136.outbound.protection.outlook.com ([65.55.169.136]:61344 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751334AbbC0KLq (ORCPT ); Fri, 27 Mar 2015 06:11:46 -0400 Received: from BY1PR0201CA0003.namprd02.prod.outlook.com (25.160.191.141) by BY2PR02MB1299.namprd02.prod.outlook.com (25.162.79.18) with Microsoft SMTP Server (TLS) id 15.1.118.21; Fri, 27 Mar 2015 09:56:18 +0000 Received: from BY2FFO11FD049.protection.gbl (2a01:111:f400:7c0c::121) by BY1PR0201CA0003.outlook.office365.com (2a01:111:e400:4814::13) with Microsoft SMTP Server (TLS) id 15.1.125.19 via Frontend Transport; Fri, 27 Mar 2015 09:56:18 +0000 Received: from atltwp02.amd.com (165.204.84.222) by BY2FFO11FD049.mail.protection.outlook.com (10.1.15.186) with Microsoft SMTP Server id 15.1.125.13 via Frontend Transport; Fri, 27 Mar 2015 09:56:18 +0000 X-WSS-ID: 0NLV7LO-08-U44-02 X-M-MSG: Received: from satlvexedge02.amd.com (satlvexedge02.amd.com [10.177.96.29]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by atltwp02.amd.com (Axway MailGate 5.3.1) with ESMTPS id 2FF8CD1602F; Fri, 27 Mar 2015 04:56:12 -0500 (CDT) Received: from SATLEXDAG02.amd.com (10.181.40.5) by SATLVEXEDGE02.amd.com (10.177.96.29) with Microsoft SMTP Server (TLS) id 14.3.195.1; Fri, 27 Mar 2015 04:56:26 -0500 Received: from SCYBEXDAG01.amd.com (10.34.11.11) by SATLEXDAG02.amd.com (10.181.40.5) with Microsoft SMTP Server (TLS) id 14.3.195.1; Fri, 27 Mar 2015 05:56:16 -0400 Received: from [10.237.74.21] (10.237.74.21) by SCYBEXDAG01.amd.com (10.34.11.11) with Microsoft SMTP Server id 14.3.195.1; Fri, 27 Mar 2015 17:56:12 +0800 Message-ID: <1427449466.2874.2.camel@kxue-X58A-UD3R> Subject: [Patch] pinctrl: fix warning from static analysis tools for AMD GPIO driver From: Ken Xue To: Linus Walleij CC: "linux-gpio@vger.kernel.org" Date: Fri, 27 Mar 2015 17:44:26 +0800 In-Reply-To: <1425087698.14876.28.camel@kxue-X58A-UD3R> References: <1422949788.18208.4.camel@kxue-X58A-UD3R> <1425087698.14876.28.camel@kxue-X58A-UD3R> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-EOPAttributedMessage: 0 Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) Authentication-Results: spf=none (sender IP is 165.204.84.222) smtp.mailfrom=Ken.Xue@amd.com; linaro.org; dkim=none (message not signed) header.d=none; X-Forefront-Antispam-Report: CIP:165.204.84.222; CTRY:US; IPV:NLI; EFV:NLI; BMV:1; SFV:NSPM; SFS:(10019020)(6009001)(428002)(189002)(199003)(62966003)(77156002)(101416001)(50986999)(23676002)(76176999)(47776003)(5820100001)(92566002)(2950100001)(50226001)(103116003)(33646002)(87936001)(110136001)(33716001)(46102003)(19580395003)(19580405001)(77096005)(229853001)(105586002)(106466001)(86362001)(50466002)(3940600001)(217873001); DIR:OUT; SFP:1102; SCL:1; SRVR:BY2PR02MB1299; H:atltwp02.amd.com; FPR:; SPF:None; MLV:sfv; MX:1; A:1; LANG:en; X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BY2PR02MB1299; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5002010)(5005006); SRVR:BY2PR02MB1299; BCL:0; PCL:0; RULEID:; SRVR:BY2PR02MB1299; X-Forefront-PRVS: 0528942FD8 X-OriginatorOrg: amd4.onmicrosoft.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Mar 2015 09:56:18.1896 (UTC) X-MS-Exchange-CrossTenant-Id: fde4dada-be84-483f-92cc-e026cbee8e96 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fde4dada-be84-483f-92cc-e026cbee8e96; Ip=[165.204.84.222]; Helo=[atltwp02.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY2PR02MB1299 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Fix inconsistent spinlock of AMD GPIO driver which can be recognized by static analysis tool smatch. Declare constant Variables with Sparse's suggestion. Signed-off-by: Ken Xue --- drivers/pinctrl/pinctrl-amd.c | 19 +++++++++---------- drivers/pinctrl/pinctrl-amd.h | 12 ++++++------ 2 files changed, 15 insertions(+), 16 deletions(-) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 3fe9ec4..7de3b64 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include @@ -119,8 +118,9 @@ static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, unsigned debounce) { - u32 pin_reg; u32 time; + u32 pin_reg; + int ret = 0; unsigned long flags; struct amd_gpio *gpio_dev = to_amd_gpio(gc); @@ -166,7 +166,7 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, pin_reg |= BIT(DB_TMR_LARGE_OFF); } else { pin_reg &= ~DB_CNTRl_MASK; - return -EINVAL; + ret = -EINVAL; } } else { pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); @@ -177,7 +177,7 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, writel(pin_reg, gpio_dev->base + offset * 4); spin_unlock_irqrestore(&gpio_dev->lock, flags); - return 0; + return ret; } #ifdef CONFIG_DEBUG_FS @@ -463,14 +463,12 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) default: dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); ret = -EINVAL; - goto exit; } pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; writel(pin_reg, gpio_dev->base + (d->hwirq)*4); spin_unlock_irqrestore(&gpio_dev->lock, flags); -exit: return ret; } @@ -635,8 +633,9 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *configs, unsigned num_configs) { int i; - u32 pin_reg; u32 arg; + int ret = 0; + u32 pin_reg; unsigned long flags; enum pin_config_param param; struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); @@ -675,14 +674,14 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, default: dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", param); - return -ENOTSUPP; + ret = -ENOTSUPP; } writel(pin_reg, gpio_dev->base + pin*4); } spin_unlock_irqrestore(&gpio_dev->lock, flags); - return 0; + return ret; } static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, @@ -739,7 +738,7 @@ static struct pinctrl_desc amd_pinctrl_desc = { static int amd_gpio_probe(struct platform_device *pdev) { int ret = 0; - u32 irq_base; + int irq_base; struct resource *res; struct amd_gpio *gpio_dev; diff --git a/drivers/pinctrl/pinctrl-amd.h b/drivers/pinctrl/pinctrl-amd.h index 37e72aa..7bfea47 100644 --- a/drivers/pinctrl/pinctrl-amd.h +++ b/drivers/pinctrl/pinctrl-amd.h @@ -217,13 +217,13 @@ static const struct pinctrl_pin_desc kerncz_pins[] = { PINCTRL_PIN(177, "GPIO_177"), }; -const unsigned i2c0_pins[] = {145, 146}; -const unsigned i2c1_pins[] = {147, 148}; -const unsigned i2c2_pins[] = {113, 114}; -const unsigned i2c3_pins[] = {19, 20}; +static const unsigned i2c0_pins[] = {145, 146}; +static const unsigned i2c1_pins[] = {147, 148}; +static const unsigned i2c2_pins[] = {113, 114}; +static const unsigned i2c3_pins[] = {19, 20}; -const unsigned uart0_pins[] = {135, 136, 137, 138, 139}; -const unsigned uart1_pins[] = {140, 141, 142, 143, 144}; +static const unsigned uart0_pins[] = {135, 136, 137, 138, 139}; +static const unsigned uart1_pins[] = {140, 141, 142, 143, 144}; static const struct amd_pingroup kerncz_groups[] = { {