From patchwork Thu Mar 19 17:25:39 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: grygorii.strashko@linaro.org X-Patchwork-Id: 452096 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 18DA2140083 for ; Fri, 20 Mar 2015 04:30:59 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965098AbbCSRa5 (ORCPT ); Thu, 19 Mar 2015 13:30:57 -0400 Received: from mail-lb0-f176.google.com ([209.85.217.176]:36484 "EHLO mail-lb0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755779AbbCSR0A (ORCPT ); Thu, 19 Mar 2015 13:26:00 -0400 Received: by lbblx11 with SMTP id lx11so35865832lbb.3 for ; Thu, 19 Mar 2015 10:25:58 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PNhPX+jSl+Vfh+VcpPAlW484C+oyJc3QKG9o1+eUerk=; b=Vc8rydKX+V/Aid8rtSycduKtDx+hSbidKvqB2nSPaED6hn5H5CTaWtXTIjKAhAFudF eF2f5gvYcDnMckt8P1yv82WVxG9faL0ZCylcE/qZRBibsh47VXRq//RigIn3z3qHY/qi u0I1UkgqbTRd7yR4QevmzvFbVQ3xdvCdaKDlNF4oJ2PgydvZRb1m00b/2xp2vPCI52lq 0Pvs6jsT5Yzp89lH0ozAQvPYsbsrgPtrh19DcC2Kta6BKWHYsGKIsIeAHh3gyMlXC+vz smU5ffeV/rQ7atliPtvjw8ddknuQ4fseteqzDmH/hBWJLcDTQu2d9HJAli+6atIBEpW4 97fA== X-Gm-Message-State: ALoCoQm0jBJVbFhCKUiSNsGahnYehuMIFtfPYWLM9jIascS3Byto668eoMNc1WJ5oZCnnXw0f2rq X-Received: by 10.152.10.1 with SMTP id e1mr4878340lab.40.1426785958507; Thu, 19 Mar 2015 10:25:58 -0700 (PDT) Received: from localhost ([195.238.92.128]) by mx.google.com with ESMTPSA id x4sm410589lba.22.2015.03.19.10.25.57 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 19 Mar 2015 10:25:57 -0700 (PDT) From: To: Javier Martinez Canillas , Linus Walleij , Alexandre Courbot , ssantosh@kernel.org, Kevin Hilman , tony@atomide.com Cc: linux-omap@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Grygorii Strashko Subject: [PATCH 3/8] gpio: omap: convert debounce functions switch to use gpio offset Date: Thu, 19 Mar 2015 19:25:39 +0200 Message-Id: <1426785944-17255-4-git-send-email-grygorii.strashko@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1426785944-17255-1-git-send-email-grygorii.strashko@linaro.org> References: <1426785944-17255-1-git-send-email-grygorii.strashko@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Grygorii Strashko Convert debounce functions to use GPIO offset instead of system GPIO numbers. This allows to drop unneeded conversations between system GPIO <-> GPIO offset which are done in many places and many times. It is safe to do now because: - gpiolib always passes GPIO offset to GPIO controller - OMAP GPIO driver converted to use IRQ domain This is preparation step before removing: #define GPIO_INDEX(bank, gpio) #define GPIO_BIT(bank, gpio) int omap_irq_to_gpio() Signed-off-by: Grygorii Strashko Acked-by: Javier Martinez Canillas --- drivers/gpio/gpio-omap.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c index 7aeee7b..2df693b 100644 --- a/drivers/gpio/gpio-omap.c +++ b/drivers/gpio/gpio-omap.c @@ -208,13 +208,13 @@ static inline void omap_gpio_dbck_disable(struct gpio_bank *bank) /** * omap2_set_gpio_debounce - low level gpio debounce time * @bank: the gpio bank we're acting upon - * @gpio: the gpio number on this @gpio + * @offset: the gpio number on this @bank * @debounce: debounce time to use * * OMAP's debounce time is in 31us steps so we need * to convert and round up to the closest unit. */ -static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, +static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset, unsigned debounce) { void __iomem *reg; @@ -231,7 +231,7 @@ static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, else debounce = (debounce / 0x1f) - 1; - l = GPIO_BIT(bank, gpio); + l = BIT(offset); clk_prepare_enable(bank->dbck); reg = bank->base + bank->regs->debounce; @@ -266,16 +266,16 @@ static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, /** * omap_clear_gpio_debounce - clear debounce settings for a gpio * @bank: the gpio bank we're acting upon - * @gpio: the gpio number on this @gpio + * @offset: the gpio number on this @bank * * If a gpio is using debounce, then clear the debounce enable bit and if * this is the only gpio in this bank using debounce, then clear the debounce * time too. The debounce clock will also be disabled when calling this function * if this is the only gpio in the bank using debounce. */ -static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned gpio) +static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset) { - u32 gpio_bit = GPIO_BIT(bank, gpio); + u32 gpio_bit = BIT(offset); if (!bank->dbck_flag) return; @@ -659,7 +659,7 @@ static void omap_reset_gpio(struct gpio_bank *bank, int gpio) omap_set_gpio_irqenable(bank, gpio, 0); omap_clear_gpio_irqstatus(bank, gpio); omap_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); - omap_clear_gpio_debounce(bank, gpio); + omap_clear_gpio_debounce(bank, GPIO_INDEX(bank, gpio)); } /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */